1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <logbuff.h> 23 #include <malloc.h> 24 #include <mapmem.h> 25 #include <os.h> 26 #include <post.h> 27 #include <relocate.h> 28 #include <spi.h> 29 #include <status_led.h> 30 #include <timer.h> 31 #include <trace.h> 32 #include <video.h> 33 #include <watchdog.h> 34 #ifdef CONFIG_MACH_TYPE 35 #include <asm/mach-types.h> 36 #endif 37 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 38 #include <asm/mp.h> 39 #endif 40 #include <asm/io.h> 41 #include <asm/sections.h> 42 #include <dm/root.h> 43 #include <linux/errno.h> 44 45 /* 46 * Pointer to initial global data area 47 * 48 * Here we initialize it if needed. 49 */ 50 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 51 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 53 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 54 #else 55 DECLARE_GLOBAL_DATA_PTR; 56 #endif 57 58 /* 59 * TODO(sjg@chromium.org): IMO this code should be 60 * refactored to a single function, something like: 61 * 62 * void led_set_state(enum led_colour_t colour, int on); 63 */ 64 /************************************************************************ 65 * Coloured LED functionality 66 ************************************************************************ 67 * May be supplied by boards if desired 68 */ 69 __weak void coloured_LED_init(void) {} 70 __weak void red_led_on(void) {} 71 __weak void red_led_off(void) {} 72 __weak void green_led_on(void) {} 73 __weak void green_led_off(void) {} 74 __weak void yellow_led_on(void) {} 75 __weak void yellow_led_off(void) {} 76 __weak void blue_led_on(void) {} 77 __weak void blue_led_off(void) {} 78 79 /* 80 * Why is gd allocated a register? Prior to reloc it might be better to 81 * just pass it around to each function in this file? 82 * 83 * After reloc one could argue that it is hardly used and doesn't need 84 * to be in a register. Or if it is it should perhaps hold pointers to all 85 * global data for all modules, so that post-reloc we can avoid the massive 86 * literal pool we get on ARM. Or perhaps just encourage each module to use 87 * a structure... 88 */ 89 90 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 91 static int init_func_watchdog_init(void) 92 { 93 # if defined(CONFIG_HW_WATCHDOG) && \ 94 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 95 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 96 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 97 defined(CONFIG_IMX_WATCHDOG)) 98 hw_watchdog_init(); 99 puts(" Watchdog enabled\n"); 100 # endif 101 WATCHDOG_RESET(); 102 103 return 0; 104 } 105 106 int init_func_watchdog_reset(void) 107 { 108 WATCHDOG_RESET(); 109 110 return 0; 111 } 112 #endif /* CONFIG_WATCHDOG */ 113 114 __weak void board_add_ram_info(int use_default) 115 { 116 /* please define platform specific board_add_ram_info() */ 117 } 118 119 static int init_baud_rate(void) 120 { 121 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 122 return 0; 123 } 124 125 static int display_text_info(void) 126 { 127 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 128 ulong bss_start, bss_end, text_base; 129 130 bss_start = (ulong)&__bss_start; 131 bss_end = (ulong)&__bss_end; 132 133 #ifdef CONFIG_SYS_TEXT_BASE 134 text_base = CONFIG_SYS_TEXT_BASE; 135 #else 136 text_base = CONFIG_SYS_MONITOR_BASE; 137 #endif 138 139 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 140 text_base, bss_start, bss_end); 141 #endif 142 143 return 0; 144 } 145 146 static int announce_dram_init(void) 147 { 148 puts("DRAM: "); 149 return 0; 150 } 151 152 static int show_dram_config(void) 153 { 154 unsigned long long size; 155 156 #ifdef CONFIG_NR_DRAM_BANKS 157 int i; 158 159 debug("\nRAM Configuration:\n"); 160 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 161 size += gd->bd->bi_dram[i].size; 162 debug("Bank #%d: %llx ", i, 163 (unsigned long long)(gd->bd->bi_dram[i].start)); 164 #ifdef DEBUG 165 print_size(gd->bd->bi_dram[i].size, "\n"); 166 #endif 167 } 168 debug("\nDRAM: "); 169 #else 170 size = gd->ram_size; 171 #endif 172 173 print_size(size, ""); 174 board_add_ram_info(0); 175 putc('\n'); 176 177 return 0; 178 } 179 180 __weak int dram_init_banksize(void) 181 { 182 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 183 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 184 gd->bd->bi_dram[0].size = get_effective_memsize(); 185 #endif 186 187 return 0; 188 } 189 190 #if defined(CONFIG_SYS_I2C) 191 static int init_func_i2c(void) 192 { 193 puts("I2C: "); 194 #ifdef CONFIG_SYS_I2C 195 i2c_init_all(); 196 #else 197 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 198 #endif 199 puts("ready\n"); 200 return 0; 201 } 202 #endif 203 204 #if defined(CONFIG_HARD_SPI) 205 static int init_func_spi(void) 206 { 207 puts("SPI: "); 208 spi_init(); 209 puts("ready\n"); 210 return 0; 211 } 212 #endif 213 214 static int setup_mon_len(void) 215 { 216 #if defined(__ARM__) || defined(__MICROBLAZE__) 217 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 218 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 219 gd->mon_len = (ulong)&_end - (ulong)_init; 220 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 221 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 222 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) 223 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 224 #elif defined(CONFIG_SYS_MONITOR_BASE) 225 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 226 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 227 #endif 228 return 0; 229 } 230 231 __weak int arch_cpu_init(void) 232 { 233 return 0; 234 } 235 236 __weak int mach_cpu_init(void) 237 { 238 return 0; 239 } 240 241 /* Get the top of usable RAM */ 242 __weak ulong board_get_usable_ram_top(ulong total_size) 243 { 244 #ifdef CONFIG_SYS_SDRAM_BASE 245 /* 246 * Detect whether we have so much RAM that it goes past the end of our 247 * 32-bit address space. If so, clip the usable RAM so it doesn't. 248 */ 249 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 250 /* 251 * Will wrap back to top of 32-bit space when reservations 252 * are made. 253 */ 254 return 0; 255 #endif 256 return gd->ram_top; 257 } 258 259 static int setup_dest_addr(void) 260 { 261 debug("Monitor len: %08lX\n", gd->mon_len); 262 /* 263 * Ram is setup, size stored in gd !! 264 */ 265 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 266 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 267 /* 268 * Subtract specified amount of memory to hide so that it won't 269 * get "touched" at all by U-Boot. By fixing up gd->ram_size 270 * the Linux kernel should now get passed the now "corrected" 271 * memory size and won't touch it either. This should work 272 * for arch/ppc and arch/powerpc. Only Linux board ports in 273 * arch/powerpc with bootwrapper support, that recalculate the 274 * memory size from the SDRAM controller setup will have to 275 * get fixed. 276 */ 277 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 278 #endif 279 #ifdef CONFIG_SYS_SDRAM_BASE 280 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 281 #endif 282 gd->ram_top += get_effective_memsize(); 283 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 284 gd->relocaddr = gd->ram_top; 285 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 286 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 287 /* 288 * We need to make sure the location we intend to put secondary core 289 * boot code is reserved and not used by any part of u-boot 290 */ 291 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 292 gd->relocaddr = determine_mp_bootpg(NULL); 293 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 294 } 295 #endif 296 return 0; 297 } 298 299 #if defined(CONFIG_LOGBUFFER) 300 static int reserve_logbuffer(void) 301 { 302 #ifndef CONFIG_ALT_LB_ADDR 303 /* reserve kernel log buffer */ 304 gd->relocaddr -= LOGBUFF_RESERVE; 305 debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, 306 gd->relocaddr); 307 #endif 308 309 return 0; 310 } 311 #endif 312 313 #ifdef CONFIG_PRAM 314 /* reserve protected RAM */ 315 static int reserve_pram(void) 316 { 317 ulong reg; 318 319 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 320 gd->relocaddr -= (reg << 10); /* size is in kB */ 321 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 322 gd->relocaddr); 323 return 0; 324 } 325 #endif /* CONFIG_PRAM */ 326 327 /* Round memory pointer down to next 4 kB limit */ 328 static int reserve_round_4k(void) 329 { 330 gd->relocaddr &= ~(4096 - 1); 331 return 0; 332 } 333 334 #ifdef CONFIG_ARM 335 __weak int reserve_mmu(void) 336 { 337 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 338 /* reserve TLB table */ 339 gd->arch.tlb_size = PGTABLE_SIZE; 340 gd->relocaddr -= gd->arch.tlb_size; 341 342 /* round down to next 64 kB limit */ 343 gd->relocaddr &= ~(0x10000 - 1); 344 345 gd->arch.tlb_addr = gd->relocaddr; 346 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 347 gd->arch.tlb_addr + gd->arch.tlb_size); 348 349 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 350 /* 351 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 352 * with location within secure ram. 353 */ 354 gd->arch.tlb_allocated = gd->arch.tlb_addr; 355 #endif 356 #endif 357 358 return 0; 359 } 360 #endif 361 362 static int reserve_video(void) 363 { 364 #ifdef CONFIG_DM_VIDEO 365 ulong addr; 366 int ret; 367 368 addr = gd->relocaddr; 369 ret = video_reserve(&addr); 370 if (ret) 371 return ret; 372 gd->relocaddr = addr; 373 #elif defined(CONFIG_LCD) 374 # ifdef CONFIG_FB_ADDR 375 gd->fb_base = CONFIG_FB_ADDR; 376 # else 377 /* reserve memory for LCD display (always full pages) */ 378 gd->relocaddr = lcd_setmem(gd->relocaddr); 379 gd->fb_base = gd->relocaddr; 380 # endif /* CONFIG_FB_ADDR */ 381 #elif defined(CONFIG_VIDEO) && \ 382 (!defined(CONFIG_PPC)) && \ 383 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 384 !defined(CONFIG_M68K) 385 /* reserve memory for video display (always full pages) */ 386 gd->relocaddr = video_setmem(gd->relocaddr); 387 gd->fb_base = gd->relocaddr; 388 #endif 389 390 return 0; 391 } 392 393 static int reserve_trace(void) 394 { 395 #ifdef CONFIG_TRACE 396 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 397 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 398 debug("Reserving %dk for trace data at: %08lx\n", 399 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 400 #endif 401 402 return 0; 403 } 404 405 static int reserve_uboot(void) 406 { 407 /* 408 * reserve memory for U-Boot code, data & bss 409 * round down to next 4 kB limit 410 */ 411 gd->relocaddr -= gd->mon_len; 412 gd->relocaddr &= ~(4096 - 1); 413 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 414 /* round down to next 64 kB limit so that IVPR stays aligned */ 415 gd->relocaddr &= ~(65536 - 1); 416 #endif 417 418 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 419 gd->relocaddr); 420 421 gd->start_addr_sp = gd->relocaddr; 422 423 return 0; 424 } 425 426 /* reserve memory for malloc() area */ 427 static int reserve_malloc(void) 428 { 429 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 430 debug("Reserving %dk for malloc() at: %08lx\n", 431 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 432 return 0; 433 } 434 435 /* (permanently) allocate a Board Info struct */ 436 static int reserve_board(void) 437 { 438 if (!gd->bd) { 439 gd->start_addr_sp -= sizeof(bd_t); 440 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 441 memset(gd->bd, '\0', sizeof(bd_t)); 442 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 443 sizeof(bd_t), gd->start_addr_sp); 444 } 445 return 0; 446 } 447 448 static int setup_machine(void) 449 { 450 #ifdef CONFIG_MACH_TYPE 451 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 452 #endif 453 return 0; 454 } 455 456 static int reserve_global_data(void) 457 { 458 gd->start_addr_sp -= sizeof(gd_t); 459 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 460 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 461 sizeof(gd_t), gd->start_addr_sp); 462 return 0; 463 } 464 465 static int reserve_fdt(void) 466 { 467 #ifndef CONFIG_OF_EMBED 468 /* 469 * If the device tree is sitting immediately above our image then we 470 * must relocate it. If it is embedded in the data section, then it 471 * will be relocated with other data. 472 */ 473 if (gd->fdt_blob) { 474 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 475 476 gd->start_addr_sp -= gd->fdt_size; 477 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 478 debug("Reserving %lu Bytes for FDT at: %08lx\n", 479 gd->fdt_size, gd->start_addr_sp); 480 } 481 #endif 482 483 return 0; 484 } 485 486 static int reserve_bootstage(void) 487 { 488 #ifdef CONFIG_BOOTSTAGE 489 int size = bootstage_get_size(); 490 491 gd->start_addr_sp -= size; 492 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 493 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 494 gd->start_addr_sp); 495 #endif 496 497 return 0; 498 } 499 500 int arch_reserve_stacks(void) 501 { 502 return 0; 503 } 504 505 static int reserve_stacks(void) 506 { 507 /* make stack pointer 16-byte aligned */ 508 gd->start_addr_sp -= 16; 509 gd->start_addr_sp &= ~0xf; 510 511 /* 512 * let the architecture-specific code tailor gd->start_addr_sp and 513 * gd->irq_sp 514 */ 515 return arch_reserve_stacks(); 516 } 517 518 static int display_new_sp(void) 519 { 520 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 521 522 return 0; 523 } 524 525 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 526 defined(CONFIG_SH) 527 static int setup_board_part1(void) 528 { 529 bd_t *bd = gd->bd; 530 531 /* 532 * Save local variables to board info struct 533 */ 534 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 535 bd->bi_memsize = gd->ram_size; /* size in bytes */ 536 537 #ifdef CONFIG_SYS_SRAM_BASE 538 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 539 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 540 #endif 541 542 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 543 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 544 #endif 545 #if defined(CONFIG_M68K) 546 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 547 #endif 548 #if defined(CONFIG_MPC83xx) 549 bd->bi_immrbar = CONFIG_SYS_IMMR; 550 #endif 551 552 return 0; 553 } 554 #endif 555 556 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 557 static int setup_board_part2(void) 558 { 559 bd_t *bd = gd->bd; 560 561 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 562 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 563 #if defined(CONFIG_CPM2) 564 bd->bi_cpmfreq = gd->arch.cpm_clk; 565 bd->bi_brgfreq = gd->arch.brg_clk; 566 bd->bi_sccfreq = gd->arch.scc_clk; 567 bd->bi_vco = gd->arch.vco_out; 568 #endif /* CONFIG_CPM2 */ 569 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 570 bd->bi_pcifreq = gd->pci_clk; 571 #endif 572 #if defined(CONFIG_EXTRA_CLOCK) 573 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 574 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 575 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 576 #endif 577 578 return 0; 579 } 580 #endif 581 582 #ifdef CONFIG_POST 583 static int init_post(void) 584 { 585 post_bootmode_init(); 586 post_run(NULL, POST_ROM | post_bootmode_get(0)); 587 588 return 0; 589 } 590 #endif 591 592 static int reloc_fdt(void) 593 { 594 #ifndef CONFIG_OF_EMBED 595 if (gd->flags & GD_FLG_SKIP_RELOC) 596 return 0; 597 if (gd->new_fdt) { 598 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 599 gd->fdt_blob = gd->new_fdt; 600 } 601 #endif 602 603 return 0; 604 } 605 606 static int reloc_bootstage(void) 607 { 608 #ifdef CONFIG_BOOTSTAGE 609 if (gd->flags & GD_FLG_SKIP_RELOC) 610 return 0; 611 if (gd->new_bootstage) { 612 int size = bootstage_get_size(); 613 614 debug("Copying bootstage from %p to %p, size %x\n", 615 gd->bootstage, gd->new_bootstage, size); 616 memcpy(gd->new_bootstage, gd->bootstage, size); 617 gd->bootstage = gd->new_bootstage; 618 } 619 #endif 620 621 return 0; 622 } 623 624 static int setup_reloc(void) 625 { 626 if (gd->flags & GD_FLG_SKIP_RELOC) { 627 debug("Skipping relocation due to flag\n"); 628 return 0; 629 } 630 631 #ifdef CONFIG_SYS_TEXT_BASE 632 #ifdef ARM 633 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 634 #elif defined(CONFIG_M68K) 635 /* 636 * On all ColdFire arch cpu, monitor code starts always 637 * just after the default vector table location, so at 0x400 638 */ 639 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 640 #else 641 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 642 #endif 643 #endif 644 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 645 646 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 647 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 648 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 649 gd->start_addr_sp); 650 651 return 0; 652 } 653 654 #ifdef CONFIG_OF_BOARD_FIXUP 655 static int fix_fdt(void) 656 { 657 return board_fix_fdt((void *)gd->fdt_blob); 658 } 659 #endif 660 661 /* ARM calls relocate_code from its crt0.S */ 662 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 663 !CONFIG_IS_ENABLED(X86_64) 664 665 static int jump_to_copy(void) 666 { 667 if (gd->flags & GD_FLG_SKIP_RELOC) 668 return 0; 669 /* 670 * x86 is special, but in a nice way. It uses a trampoline which 671 * enables the dcache if possible. 672 * 673 * For now, other archs use relocate_code(), which is implemented 674 * similarly for all archs. When we do generic relocation, hopefully 675 * we can make all archs enable the dcache prior to relocation. 676 */ 677 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 678 /* 679 * SDRAM and console are now initialised. The final stack can now 680 * be setup in SDRAM. Code execution will continue in Flash, but 681 * with the stack in SDRAM and Global Data in temporary memory 682 * (CPU cache) 683 */ 684 arch_setup_gd(gd->new_gd); 685 board_init_f_r_trampoline(gd->start_addr_sp); 686 #else 687 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 688 #endif 689 690 return 0; 691 } 692 #endif 693 694 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 695 static int initf_bootstage(void) 696 { 697 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 698 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 699 int ret; 700 701 ret = bootstage_init(!from_spl); 702 if (ret) 703 return ret; 704 if (from_spl) { 705 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 706 CONFIG_BOOTSTAGE_STASH_SIZE); 707 708 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 709 if (ret && ret != -ENOENT) { 710 debug("Failed to unstash bootstage: err=%d\n", ret); 711 return ret; 712 } 713 } 714 715 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 716 717 return 0; 718 } 719 720 static int initf_console_record(void) 721 { 722 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 723 return console_record_init(); 724 #else 725 return 0; 726 #endif 727 } 728 729 static int initf_dm(void) 730 { 731 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 732 int ret; 733 734 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 735 ret = dm_init_and_scan(true); 736 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 737 if (ret) 738 return ret; 739 #endif 740 #ifdef CONFIG_TIMER_EARLY 741 ret = dm_timer_init(); 742 if (ret) 743 return ret; 744 #endif 745 746 return 0; 747 } 748 749 /* Architecture-specific memory reservation */ 750 __weak int reserve_arch(void) 751 { 752 return 0; 753 } 754 755 __weak int arch_cpu_init_dm(void) 756 { 757 return 0; 758 } 759 760 static const init_fnc_t init_sequence_f[] = { 761 setup_mon_len, 762 #ifdef CONFIG_OF_CONTROL 763 fdtdec_setup, 764 #endif 765 #ifdef CONFIG_TRACE 766 trace_early_init, 767 #endif 768 initf_malloc, 769 initf_bootstage, /* uses its own timer, so does not need DM */ 770 initf_console_record, 771 #if defined(CONFIG_HAVE_FSP) 772 arch_fsp_init, 773 #endif 774 arch_cpu_init, /* basic arch cpu dependent setup */ 775 mach_cpu_init, /* SoC/machine dependent CPU setup */ 776 initf_dm, 777 arch_cpu_init_dm, 778 #if defined(CONFIG_BOARD_EARLY_INIT_F) 779 board_early_init_f, 780 #endif 781 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 782 /* get CPU and bus clocks according to the environment variable */ 783 get_clocks, /* get CPU and bus clocks (etc.) */ 784 #endif 785 #if !defined(CONFIG_M68K) 786 timer_init, /* initialize timer */ 787 #endif 788 #if defined(CONFIG_BOARD_POSTCLK_INIT) 789 board_postclk_init, 790 #endif 791 env_init, /* initialize environment */ 792 init_baud_rate, /* initialze baudrate settings */ 793 serial_init, /* serial communications setup */ 794 console_init_f, /* stage 1 init of console */ 795 display_options, /* say that we are here */ 796 display_text_info, /* show debugging info if required */ 797 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 798 defined(CONFIG_X86) 799 checkcpu, 800 #endif 801 #if defined(CONFIG_DISPLAY_CPUINFO) 802 print_cpuinfo, /* display cpu info (and speed) */ 803 #endif 804 #if defined(CONFIG_DTB_RESELECT) 805 embedded_dtb_select, 806 #endif 807 #if defined(CONFIG_DISPLAY_BOARDINFO) 808 show_board_info, 809 #endif 810 INIT_FUNC_WATCHDOG_INIT 811 #if defined(CONFIG_MISC_INIT_F) 812 misc_init_f, 813 #endif 814 INIT_FUNC_WATCHDOG_RESET 815 #if defined(CONFIG_SYS_I2C) 816 init_func_i2c, 817 #endif 818 #if defined(CONFIG_HARD_SPI) 819 init_func_spi, 820 #endif 821 announce_dram_init, 822 dram_init, /* configure available RAM banks */ 823 #ifdef CONFIG_POST 824 post_init_f, 825 #endif 826 INIT_FUNC_WATCHDOG_RESET 827 #if defined(CONFIG_SYS_DRAM_TEST) 828 testdram, 829 #endif /* CONFIG_SYS_DRAM_TEST */ 830 INIT_FUNC_WATCHDOG_RESET 831 832 #ifdef CONFIG_POST 833 init_post, 834 #endif 835 INIT_FUNC_WATCHDOG_RESET 836 /* 837 * Now that we have DRAM mapped and working, we can 838 * relocate the code and continue running from DRAM. 839 * 840 * Reserve memory at end of RAM for (top down in that order): 841 * - area that won't get touched by U-Boot and Linux (optional) 842 * - kernel log buffer 843 * - protected RAM 844 * - LCD framebuffer 845 * - monitor code 846 * - board info struct 847 */ 848 setup_dest_addr, 849 #if defined(CONFIG_LOGBUFFER) 850 reserve_logbuffer, 851 #endif 852 #ifdef CONFIG_PRAM 853 reserve_pram, 854 #endif 855 reserve_round_4k, 856 #ifdef CONFIG_ARM 857 reserve_mmu, 858 #endif 859 reserve_video, 860 reserve_trace, 861 reserve_uboot, 862 reserve_malloc, 863 reserve_board, 864 setup_machine, 865 reserve_global_data, 866 reserve_fdt, 867 reserve_bootstage, 868 reserve_arch, 869 reserve_stacks, 870 dram_init_banksize, 871 show_dram_config, 872 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 873 defined(CONFIG_SH) 874 setup_board_part1, 875 #endif 876 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 877 INIT_FUNC_WATCHDOG_RESET 878 setup_board_part2, 879 #endif 880 display_new_sp, 881 #ifdef CONFIG_OF_BOARD_FIXUP 882 fix_fdt, 883 #endif 884 INIT_FUNC_WATCHDOG_RESET 885 reloc_fdt, 886 reloc_bootstage, 887 setup_reloc, 888 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 889 copy_uboot_to_ram, 890 do_elf_reloc_fixups, 891 clear_bss, 892 #endif 893 #if defined(CONFIG_XTENSA) 894 clear_bss, 895 #endif 896 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 897 !CONFIG_IS_ENABLED(X86_64) 898 jump_to_copy, 899 #endif 900 NULL, 901 }; 902 903 void board_init_f(ulong boot_flags) 904 { 905 gd->flags = boot_flags; 906 gd->have_console = 0; 907 908 if (initcall_run_list(init_sequence_f)) 909 hang(); 910 911 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 912 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 913 /* NOTREACHED - jump_to_copy() does not return */ 914 hang(); 915 #endif 916 } 917 918 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 919 /* 920 * For now this code is only used on x86. 921 * 922 * init_sequence_f_r is the list of init functions which are run when 923 * U-Boot is executing from Flash with a semi-limited 'C' environment. 924 * The following limitations must be considered when implementing an 925 * '_f_r' function: 926 * - 'static' variables are read-only 927 * - Global Data (gd->xxx) is read/write 928 * 929 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 930 * supported). It _should_, if possible, copy global data to RAM and 931 * initialise the CPU caches (to speed up the relocation process) 932 * 933 * NOTE: At present only x86 uses this route, but it is intended that 934 * all archs will move to this when generic relocation is implemented. 935 */ 936 static const init_fnc_t init_sequence_f_r[] = { 937 #if !CONFIG_IS_ENABLED(X86_64) 938 init_cache_f_r, 939 #endif 940 941 NULL, 942 }; 943 944 void board_init_f_r(void) 945 { 946 if (initcall_run_list(init_sequence_f_r)) 947 hang(); 948 949 /* 950 * The pre-relocation drivers may be using memory that has now gone 951 * away. Mark serial as unavailable - this will fall back to the debug 952 * UART if available. 953 */ 954 gd->flags &= ~GD_FLG_SERIAL_READY; 955 956 /* 957 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 958 * Transfer execution from Flash to RAM by calculating the address 959 * of the in-RAM copy of board_init_r() and calling it 960 */ 961 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 962 963 /* NOTREACHED - board_init_r() does not return */ 964 hang(); 965 } 966 #endif /* CONFIG_X86 */ 967