1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 44 /* 45 * Pointer to initial global data area 46 * 47 * Here we initialize it if needed. 48 */ 49 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 50 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 51 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 52 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 53 #else 54 DECLARE_GLOBAL_DATA_PTR; 55 #endif 56 57 /* 58 * TODO(sjg@chromium.org): IMO this code should be 59 * refactored to a single function, something like: 60 * 61 * void led_set_state(enum led_colour_t colour, int on); 62 */ 63 /************************************************************************ 64 * Coloured LED functionality 65 ************************************************************************ 66 * May be supplied by boards if desired 67 */ 68 __weak void coloured_LED_init(void) {} 69 __weak void red_led_on(void) {} 70 __weak void red_led_off(void) {} 71 __weak void green_led_on(void) {} 72 __weak void green_led_off(void) {} 73 __weak void yellow_led_on(void) {} 74 __weak void yellow_led_off(void) {} 75 __weak void blue_led_on(void) {} 76 __weak void blue_led_off(void) {} 77 78 /* 79 * Why is gd allocated a register? Prior to reloc it might be better to 80 * just pass it around to each function in this file? 81 * 82 * After reloc one could argue that it is hardly used and doesn't need 83 * to be in a register. Or if it is it should perhaps hold pointers to all 84 * global data for all modules, so that post-reloc we can avoid the massive 85 * literal pool we get on ARM. Or perhaps just encourage each module to use 86 * a structure... 87 */ 88 89 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 90 static int init_func_watchdog_init(void) 91 { 92 # if defined(CONFIG_HW_WATCHDOG) && \ 93 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 94 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 95 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 96 defined(CONFIG_IMX_WATCHDOG)) 97 hw_watchdog_init(); 98 puts(" Watchdog enabled\n"); 99 # endif 100 WATCHDOG_RESET(); 101 102 return 0; 103 } 104 105 int init_func_watchdog_reset(void) 106 { 107 WATCHDOG_RESET(); 108 109 return 0; 110 } 111 #endif /* CONFIG_WATCHDOG */ 112 113 __weak void board_add_ram_info(int use_default) 114 { 115 /* please define platform specific board_add_ram_info() */ 116 } 117 118 static int init_baud_rate(void) 119 { 120 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 121 return 0; 122 } 123 124 static int display_text_info(void) 125 { 126 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 127 ulong bss_start, bss_end, text_base; 128 129 bss_start = (ulong)&__bss_start; 130 bss_end = (ulong)&__bss_end; 131 132 #ifdef CONFIG_SYS_TEXT_BASE 133 text_base = CONFIG_SYS_TEXT_BASE; 134 #else 135 text_base = CONFIG_SYS_MONITOR_BASE; 136 #endif 137 138 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 139 text_base, bss_start, bss_end); 140 #endif 141 142 return 0; 143 } 144 145 static int announce_dram_init(void) 146 { 147 puts("DRAM: "); 148 return 0; 149 } 150 151 static int show_dram_config(void) 152 { 153 unsigned long long size; 154 155 #ifdef CONFIG_NR_DRAM_BANKS 156 int i; 157 158 debug("\nRAM Configuration:\n"); 159 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 160 size += gd->bd->bi_dram[i].size; 161 debug("Bank #%d: %llx ", i, 162 (unsigned long long)(gd->bd->bi_dram[i].start)); 163 #ifdef DEBUG 164 print_size(gd->bd->bi_dram[i].size, "\n"); 165 #endif 166 } 167 debug("\nDRAM: "); 168 #else 169 size = gd->ram_size; 170 #endif 171 172 print_size(size, ""); 173 board_add_ram_info(0); 174 putc('\n'); 175 176 return 0; 177 } 178 179 __weak int dram_init_banksize(void) 180 { 181 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 182 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 183 gd->bd->bi_dram[0].size = get_effective_memsize(); 184 #endif 185 186 return 0; 187 } 188 189 #if defined(CONFIG_SYS_I2C) 190 static int init_func_i2c(void) 191 { 192 puts("I2C: "); 193 #ifdef CONFIG_SYS_I2C 194 i2c_init_all(); 195 #else 196 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 197 #endif 198 puts("ready\n"); 199 return 0; 200 } 201 #endif 202 203 #if defined(CONFIG_VID) 204 __weak int init_func_vid(void) 205 { 206 return 0; 207 } 208 #endif 209 210 #if defined(CONFIG_HARD_SPI) 211 static int init_func_spi(void) 212 { 213 puts("SPI: "); 214 spi_init(); 215 puts("ready\n"); 216 return 0; 217 } 218 #endif 219 220 static int setup_mon_len(void) 221 { 222 #if defined(__ARM__) || defined(__MICROBLAZE__) 223 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 224 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 225 gd->mon_len = (ulong)&_end - (ulong)_init; 226 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 227 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 228 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 229 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 230 #elif defined(CONFIG_SYS_MONITOR_BASE) 231 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 232 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 233 #endif 234 return 0; 235 } 236 237 __weak int arch_cpu_init(void) 238 { 239 return 0; 240 } 241 242 __weak int mach_cpu_init(void) 243 { 244 return 0; 245 } 246 247 /* Get the top of usable RAM */ 248 __weak ulong board_get_usable_ram_top(ulong total_size) 249 { 250 #ifdef CONFIG_SYS_SDRAM_BASE 251 /* 252 * Detect whether we have so much RAM that it goes past the end of our 253 * 32-bit address space. If so, clip the usable RAM so it doesn't. 254 */ 255 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 256 /* 257 * Will wrap back to top of 32-bit space when reservations 258 * are made. 259 */ 260 return 0; 261 #endif 262 return gd->ram_top; 263 } 264 265 static int setup_dest_addr(void) 266 { 267 debug("Monitor len: %08lX\n", gd->mon_len); 268 /* 269 * Ram is setup, size stored in gd !! 270 */ 271 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 272 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 273 /* 274 * Subtract specified amount of memory to hide so that it won't 275 * get "touched" at all by U-Boot. By fixing up gd->ram_size 276 * the Linux kernel should now get passed the now "corrected" 277 * memory size and won't touch it either. This should work 278 * for arch/ppc and arch/powerpc. Only Linux board ports in 279 * arch/powerpc with bootwrapper support, that recalculate the 280 * memory size from the SDRAM controller setup will have to 281 * get fixed. 282 */ 283 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 284 #endif 285 #ifdef CONFIG_SYS_SDRAM_BASE 286 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 287 #endif 288 gd->ram_top += get_effective_memsize(); 289 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 290 gd->relocaddr = gd->ram_top; 291 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 292 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 293 /* 294 * We need to make sure the location we intend to put secondary core 295 * boot code is reserved and not used by any part of u-boot 296 */ 297 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 298 gd->relocaddr = determine_mp_bootpg(NULL); 299 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 300 } 301 #endif 302 return 0; 303 } 304 305 #ifdef CONFIG_PRAM 306 /* reserve protected RAM */ 307 static int reserve_pram(void) 308 { 309 ulong reg; 310 311 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 312 gd->relocaddr -= (reg << 10); /* size is in kB */ 313 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 314 gd->relocaddr); 315 return 0; 316 } 317 #endif /* CONFIG_PRAM */ 318 319 /* Round memory pointer down to next 4 kB limit */ 320 static int reserve_round_4k(void) 321 { 322 gd->relocaddr &= ~(4096 - 1); 323 return 0; 324 } 325 326 #ifdef CONFIG_ARM 327 __weak int reserve_mmu(void) 328 { 329 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 330 /* reserve TLB table */ 331 gd->arch.tlb_size = PGTABLE_SIZE; 332 gd->relocaddr -= gd->arch.tlb_size; 333 334 /* round down to next 64 kB limit */ 335 gd->relocaddr &= ~(0x10000 - 1); 336 337 gd->arch.tlb_addr = gd->relocaddr; 338 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 339 gd->arch.tlb_addr + gd->arch.tlb_size); 340 341 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 342 /* 343 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 344 * with location within secure ram. 345 */ 346 gd->arch.tlb_allocated = gd->arch.tlb_addr; 347 #endif 348 #endif 349 350 return 0; 351 } 352 #endif 353 354 static int reserve_video(void) 355 { 356 #ifdef CONFIG_DM_VIDEO 357 ulong addr; 358 int ret; 359 360 addr = gd->relocaddr; 361 ret = video_reserve(&addr); 362 if (ret) 363 return ret; 364 gd->relocaddr = addr; 365 #elif defined(CONFIG_LCD) 366 # ifdef CONFIG_FB_ADDR 367 gd->fb_base = CONFIG_FB_ADDR; 368 # else 369 /* reserve memory for LCD display (always full pages) */ 370 gd->relocaddr = lcd_setmem(gd->relocaddr); 371 gd->fb_base = gd->relocaddr; 372 # endif /* CONFIG_FB_ADDR */ 373 #elif defined(CONFIG_VIDEO) && \ 374 (!defined(CONFIG_PPC)) && \ 375 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 376 !defined(CONFIG_M68K) 377 /* reserve memory for video display (always full pages) */ 378 gd->relocaddr = video_setmem(gd->relocaddr); 379 gd->fb_base = gd->relocaddr; 380 #endif 381 382 return 0; 383 } 384 385 static int reserve_trace(void) 386 { 387 #ifdef CONFIG_TRACE 388 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 389 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 390 debug("Reserving %dk for trace data at: %08lx\n", 391 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 392 #endif 393 394 return 0; 395 } 396 397 static int reserve_uboot(void) 398 { 399 /* 400 * reserve memory for U-Boot code, data & bss 401 * round down to next 4 kB limit 402 */ 403 gd->relocaddr -= gd->mon_len; 404 gd->relocaddr &= ~(4096 - 1); 405 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 406 /* round down to next 64 kB limit so that IVPR stays aligned */ 407 gd->relocaddr &= ~(65536 - 1); 408 #endif 409 410 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 411 gd->relocaddr); 412 413 gd->start_addr_sp = gd->relocaddr; 414 415 return 0; 416 } 417 418 /* reserve memory for malloc() area */ 419 static int reserve_malloc(void) 420 { 421 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 422 debug("Reserving %dk for malloc() at: %08lx\n", 423 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 424 return 0; 425 } 426 427 /* (permanently) allocate a Board Info struct */ 428 static int reserve_board(void) 429 { 430 if (!gd->bd) { 431 gd->start_addr_sp -= sizeof(bd_t); 432 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 433 memset(gd->bd, '\0', sizeof(bd_t)); 434 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 435 sizeof(bd_t), gd->start_addr_sp); 436 } 437 return 0; 438 } 439 440 static int setup_machine(void) 441 { 442 #ifdef CONFIG_MACH_TYPE 443 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 444 #endif 445 return 0; 446 } 447 448 static int reserve_global_data(void) 449 { 450 gd->start_addr_sp -= sizeof(gd_t); 451 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 452 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 453 sizeof(gd_t), gd->start_addr_sp); 454 return 0; 455 } 456 457 static int reserve_fdt(void) 458 { 459 #ifndef CONFIG_OF_EMBED 460 /* 461 * If the device tree is sitting immediately above our image then we 462 * must relocate it. If it is embedded in the data section, then it 463 * will be relocated with other data. 464 */ 465 if (gd->fdt_blob) { 466 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 467 468 gd->start_addr_sp -= gd->fdt_size; 469 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 470 debug("Reserving %lu Bytes for FDT at: %08lx\n", 471 gd->fdt_size, gd->start_addr_sp); 472 } 473 #endif 474 475 return 0; 476 } 477 478 static int reserve_bootstage(void) 479 { 480 #ifdef CONFIG_BOOTSTAGE 481 int size = bootstage_get_size(); 482 483 gd->start_addr_sp -= size; 484 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 485 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 486 gd->start_addr_sp); 487 #endif 488 489 return 0; 490 } 491 492 int arch_reserve_stacks(void) 493 { 494 return 0; 495 } 496 497 static int reserve_stacks(void) 498 { 499 /* make stack pointer 16-byte aligned */ 500 gd->start_addr_sp -= 16; 501 gd->start_addr_sp &= ~0xf; 502 503 /* 504 * let the architecture-specific code tailor gd->start_addr_sp and 505 * gd->irq_sp 506 */ 507 return arch_reserve_stacks(); 508 } 509 510 static int display_new_sp(void) 511 { 512 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 513 514 return 0; 515 } 516 517 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 518 defined(CONFIG_SH) 519 static int setup_board_part1(void) 520 { 521 bd_t *bd = gd->bd; 522 523 /* 524 * Save local variables to board info struct 525 */ 526 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 527 bd->bi_memsize = gd->ram_size; /* size in bytes */ 528 529 #ifdef CONFIG_SYS_SRAM_BASE 530 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 531 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 532 #endif 533 534 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 535 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 536 #endif 537 #if defined(CONFIG_M68K) 538 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 539 #endif 540 #if defined(CONFIG_MPC83xx) 541 bd->bi_immrbar = CONFIG_SYS_IMMR; 542 #endif 543 544 return 0; 545 } 546 #endif 547 548 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 549 static int setup_board_part2(void) 550 { 551 bd_t *bd = gd->bd; 552 553 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 554 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 555 #if defined(CONFIG_CPM2) 556 bd->bi_cpmfreq = gd->arch.cpm_clk; 557 bd->bi_brgfreq = gd->arch.brg_clk; 558 bd->bi_sccfreq = gd->arch.scc_clk; 559 bd->bi_vco = gd->arch.vco_out; 560 #endif /* CONFIG_CPM2 */ 561 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 562 bd->bi_pcifreq = gd->pci_clk; 563 #endif 564 #if defined(CONFIG_EXTRA_CLOCK) 565 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 566 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 567 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 568 #endif 569 570 return 0; 571 } 572 #endif 573 574 #ifdef CONFIG_POST 575 static int init_post(void) 576 { 577 post_bootmode_init(); 578 post_run(NULL, POST_ROM | post_bootmode_get(0)); 579 580 return 0; 581 } 582 #endif 583 584 static int reloc_fdt(void) 585 { 586 #ifndef CONFIG_OF_EMBED 587 if (gd->flags & GD_FLG_SKIP_RELOC) 588 return 0; 589 if (gd->new_fdt) { 590 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 591 gd->fdt_blob = gd->new_fdt; 592 } 593 #endif 594 595 return 0; 596 } 597 598 static int reloc_bootstage(void) 599 { 600 #ifdef CONFIG_BOOTSTAGE 601 if (gd->flags & GD_FLG_SKIP_RELOC) 602 return 0; 603 if (gd->new_bootstage) { 604 int size = bootstage_get_size(); 605 606 debug("Copying bootstage from %p to %p, size %x\n", 607 gd->bootstage, gd->new_bootstage, size); 608 memcpy(gd->new_bootstage, gd->bootstage, size); 609 gd->bootstage = gd->new_bootstage; 610 } 611 #endif 612 613 return 0; 614 } 615 616 static int setup_reloc(void) 617 { 618 if (gd->flags & GD_FLG_SKIP_RELOC) { 619 debug("Skipping relocation due to flag\n"); 620 return 0; 621 } 622 623 #ifdef CONFIG_SYS_TEXT_BASE 624 #ifdef ARM 625 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 626 #elif defined(CONFIG_M68K) 627 /* 628 * On all ColdFire arch cpu, monitor code starts always 629 * just after the default vector table location, so at 0x400 630 */ 631 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 632 #else 633 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 634 #endif 635 #endif 636 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 637 638 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 639 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 640 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 641 gd->start_addr_sp); 642 643 return 0; 644 } 645 646 #ifdef CONFIG_OF_BOARD_FIXUP 647 static int fix_fdt(void) 648 { 649 return board_fix_fdt((void *)gd->fdt_blob); 650 } 651 #endif 652 653 /* ARM calls relocate_code from its crt0.S */ 654 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 655 !CONFIG_IS_ENABLED(X86_64) 656 657 static int jump_to_copy(void) 658 { 659 if (gd->flags & GD_FLG_SKIP_RELOC) 660 return 0; 661 /* 662 * x86 is special, but in a nice way. It uses a trampoline which 663 * enables the dcache if possible. 664 * 665 * For now, other archs use relocate_code(), which is implemented 666 * similarly for all archs. When we do generic relocation, hopefully 667 * we can make all archs enable the dcache prior to relocation. 668 */ 669 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 670 /* 671 * SDRAM and console are now initialised. The final stack can now 672 * be setup in SDRAM. Code execution will continue in Flash, but 673 * with the stack in SDRAM and Global Data in temporary memory 674 * (CPU cache) 675 */ 676 arch_setup_gd(gd->new_gd); 677 board_init_f_r_trampoline(gd->start_addr_sp); 678 #else 679 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 680 #endif 681 682 return 0; 683 } 684 #endif 685 686 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 687 static int initf_bootstage(void) 688 { 689 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 690 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 691 int ret; 692 693 ret = bootstage_init(!from_spl); 694 if (ret) 695 return ret; 696 if (from_spl) { 697 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 698 CONFIG_BOOTSTAGE_STASH_SIZE); 699 700 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 701 if (ret && ret != -ENOENT) { 702 debug("Failed to unstash bootstage: err=%d\n", ret); 703 return ret; 704 } 705 } 706 707 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 708 709 return 0; 710 } 711 712 static int initf_console_record(void) 713 { 714 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 715 return console_record_init(); 716 #else 717 return 0; 718 #endif 719 } 720 721 static int initf_dm(void) 722 { 723 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 724 int ret; 725 726 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 727 ret = dm_init_and_scan(true); 728 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 729 if (ret) 730 return ret; 731 #endif 732 #ifdef CONFIG_TIMER_EARLY 733 ret = dm_timer_init(); 734 if (ret) 735 return ret; 736 #endif 737 738 return 0; 739 } 740 741 /* Architecture-specific memory reservation */ 742 __weak int reserve_arch(void) 743 { 744 return 0; 745 } 746 747 __weak int arch_cpu_init_dm(void) 748 { 749 return 0; 750 } 751 752 static const init_fnc_t init_sequence_f[] = { 753 setup_mon_len, 754 #ifdef CONFIG_OF_CONTROL 755 fdtdec_setup, 756 #endif 757 #ifdef CONFIG_TRACE 758 trace_early_init, 759 #endif 760 initf_malloc, 761 log_init, 762 initf_bootstage, /* uses its own timer, so does not need DM */ 763 initf_console_record, 764 #if defined(CONFIG_HAVE_FSP) 765 arch_fsp_init, 766 #endif 767 arch_cpu_init, /* basic arch cpu dependent setup */ 768 mach_cpu_init, /* SoC/machine dependent CPU setup */ 769 initf_dm, 770 arch_cpu_init_dm, 771 #if defined(CONFIG_BOARD_EARLY_INIT_F) 772 board_early_init_f, 773 #endif 774 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 775 /* get CPU and bus clocks according to the environment variable */ 776 get_clocks, /* get CPU and bus clocks (etc.) */ 777 #endif 778 #if !defined(CONFIG_M68K) 779 timer_init, /* initialize timer */ 780 #endif 781 #if defined(CONFIG_BOARD_POSTCLK_INIT) 782 board_postclk_init, 783 #endif 784 env_init, /* initialize environment */ 785 init_baud_rate, /* initialze baudrate settings */ 786 serial_init, /* serial communications setup */ 787 console_init_f, /* stage 1 init of console */ 788 display_options, /* say that we are here */ 789 display_text_info, /* show debugging info if required */ 790 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 791 defined(CONFIG_X86) 792 checkcpu, 793 #endif 794 #if defined(CONFIG_DISPLAY_CPUINFO) 795 print_cpuinfo, /* display cpu info (and speed) */ 796 #endif 797 #if defined(CONFIG_DTB_RESELECT) 798 embedded_dtb_select, 799 #endif 800 #if defined(CONFIG_DISPLAY_BOARDINFO) 801 show_board_info, 802 #endif 803 INIT_FUNC_WATCHDOG_INIT 804 #if defined(CONFIG_MISC_INIT_F) 805 misc_init_f, 806 #endif 807 INIT_FUNC_WATCHDOG_RESET 808 #if defined(CONFIG_SYS_I2C) 809 init_func_i2c, 810 #endif 811 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 812 init_func_vid, 813 #endif 814 #if defined(CONFIG_HARD_SPI) 815 init_func_spi, 816 #endif 817 announce_dram_init, 818 dram_init, /* configure available RAM banks */ 819 #ifdef CONFIG_POST 820 post_init_f, 821 #endif 822 INIT_FUNC_WATCHDOG_RESET 823 #if defined(CONFIG_SYS_DRAM_TEST) 824 testdram, 825 #endif /* CONFIG_SYS_DRAM_TEST */ 826 INIT_FUNC_WATCHDOG_RESET 827 828 #ifdef CONFIG_POST 829 init_post, 830 #endif 831 INIT_FUNC_WATCHDOG_RESET 832 /* 833 * Now that we have DRAM mapped and working, we can 834 * relocate the code and continue running from DRAM. 835 * 836 * Reserve memory at end of RAM for (top down in that order): 837 * - area that won't get touched by U-Boot and Linux (optional) 838 * - kernel log buffer 839 * - protected RAM 840 * - LCD framebuffer 841 * - monitor code 842 * - board info struct 843 */ 844 setup_dest_addr, 845 #ifdef CONFIG_PRAM 846 reserve_pram, 847 #endif 848 reserve_round_4k, 849 #ifdef CONFIG_ARM 850 reserve_mmu, 851 #endif 852 reserve_video, 853 reserve_trace, 854 reserve_uboot, 855 reserve_malloc, 856 reserve_board, 857 setup_machine, 858 reserve_global_data, 859 reserve_fdt, 860 reserve_bootstage, 861 reserve_arch, 862 reserve_stacks, 863 dram_init_banksize, 864 show_dram_config, 865 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 866 defined(CONFIG_SH) 867 setup_board_part1, 868 #endif 869 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 870 INIT_FUNC_WATCHDOG_RESET 871 setup_board_part2, 872 #endif 873 display_new_sp, 874 #ifdef CONFIG_OF_BOARD_FIXUP 875 fix_fdt, 876 #endif 877 INIT_FUNC_WATCHDOG_RESET 878 reloc_fdt, 879 reloc_bootstage, 880 setup_reloc, 881 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 882 copy_uboot_to_ram, 883 do_elf_reloc_fixups, 884 clear_bss, 885 #endif 886 #if defined(CONFIG_XTENSA) 887 clear_bss, 888 #endif 889 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 890 !CONFIG_IS_ENABLED(X86_64) 891 jump_to_copy, 892 #endif 893 NULL, 894 }; 895 896 void board_init_f(ulong boot_flags) 897 { 898 gd->flags = boot_flags; 899 gd->have_console = 0; 900 901 if (initcall_run_list(init_sequence_f)) 902 hang(); 903 904 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 905 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 906 /* NOTREACHED - jump_to_copy() does not return */ 907 hang(); 908 #endif 909 } 910 911 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 912 /* 913 * For now this code is only used on x86. 914 * 915 * init_sequence_f_r is the list of init functions which are run when 916 * U-Boot is executing from Flash with a semi-limited 'C' environment. 917 * The following limitations must be considered when implementing an 918 * '_f_r' function: 919 * - 'static' variables are read-only 920 * - Global Data (gd->xxx) is read/write 921 * 922 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 923 * supported). It _should_, if possible, copy global data to RAM and 924 * initialise the CPU caches (to speed up the relocation process) 925 * 926 * NOTE: At present only x86 uses this route, but it is intended that 927 * all archs will move to this when generic relocation is implemented. 928 */ 929 static const init_fnc_t init_sequence_f_r[] = { 930 #if !CONFIG_IS_ENABLED(X86_64) 931 init_cache_f_r, 932 #endif 933 934 NULL, 935 }; 936 937 void board_init_f_r(void) 938 { 939 if (initcall_run_list(init_sequence_f_r)) 940 hang(); 941 942 /* 943 * The pre-relocation drivers may be using memory that has now gone 944 * away. Mark serial as unavailable - this will fall back to the debug 945 * UART if available. 946 * 947 * Do the same with log drivers since the memory may not be available. 948 */ 949 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 950 #ifdef CONFIG_TIMER 951 gd->timer = NULL; 952 #endif 953 954 /* 955 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 956 * Transfer execution from Flash to RAM by calculating the address 957 * of the in-RAM copy of board_init_r() and calling it 958 */ 959 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 960 961 /* NOTREACHED - board_init_r() does not return */ 962 hang(); 963 } 964 #endif /* CONFIG_X86 */ 965