1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2002-2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2002 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 9 * Marius Groeger <mgroeger@sysgo.de> 10 */ 11 12 #include <common.h> 13 #include <bloblist.h> 14 #include <console.h> 15 #include <cpu.h> 16 #include <dm.h> 17 #include <environment.h> 18 #include <fdtdec.h> 19 #include <fs.h> 20 #include <i2c.h> 21 #include <initcall.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #ifdef CONFIG_SPL 29 #include <spl.h> 30 #endif 31 #include <status_led.h> 32 #include <sysreset.h> 33 #include <timer.h> 34 #include <trace.h> 35 #include <video.h> 36 #include <watchdog.h> 37 #ifdef CONFIG_MACH_TYPE 38 #include <asm/mach-types.h> 39 #endif 40 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 41 #include <asm/mp.h> 42 #endif 43 #include <asm/io.h> 44 #include <asm/sections.h> 45 #include <dm/root.h> 46 #include <linux/errno.h> 47 48 /* 49 * Pointer to initial global data area 50 * 51 * Here we initialize it if needed. 52 */ 53 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 54 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 55 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 56 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 57 #else 58 DECLARE_GLOBAL_DATA_PTR; 59 #endif 60 61 /* 62 * TODO(sjg@chromium.org): IMO this code should be 63 * refactored to a single function, something like: 64 * 65 * void led_set_state(enum led_colour_t colour, int on); 66 */ 67 /************************************************************************ 68 * Coloured LED functionality 69 ************************************************************************ 70 * May be supplied by boards if desired 71 */ 72 __weak void coloured_LED_init(void) {} 73 __weak void red_led_on(void) {} 74 __weak void red_led_off(void) {} 75 __weak void green_led_on(void) {} 76 __weak void green_led_off(void) {} 77 __weak void yellow_led_on(void) {} 78 __weak void yellow_led_off(void) {} 79 __weak void blue_led_on(void) {} 80 __weak void blue_led_off(void) {} 81 82 /* 83 * Why is gd allocated a register? Prior to reloc it might be better to 84 * just pass it around to each function in this file? 85 * 86 * After reloc one could argue that it is hardly used and doesn't need 87 * to be in a register. Or if it is it should perhaps hold pointers to all 88 * global data for all modules, so that post-reloc we can avoid the massive 89 * literal pool we get on ARM. Or perhaps just encourage each module to use 90 * a structure... 91 */ 92 93 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 94 static int init_func_watchdog_init(void) 95 { 96 # if defined(CONFIG_HW_WATCHDOG) && \ 97 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 98 defined(CONFIG_SH) || \ 99 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 100 defined(CONFIG_IMX_WATCHDOG)) 101 hw_watchdog_init(); 102 puts(" Watchdog enabled\n"); 103 # endif 104 WATCHDOG_RESET(); 105 106 return 0; 107 } 108 109 int init_func_watchdog_reset(void) 110 { 111 WATCHDOG_RESET(); 112 113 return 0; 114 } 115 #endif /* CONFIG_WATCHDOG */ 116 117 __weak void board_add_ram_info(int use_default) 118 { 119 /* please define platform specific board_add_ram_info() */ 120 } 121 122 static int init_baud_rate(void) 123 { 124 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 125 return 0; 126 } 127 128 static int display_text_info(void) 129 { 130 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 131 ulong bss_start, bss_end, text_base; 132 133 bss_start = (ulong)&__bss_start; 134 bss_end = (ulong)&__bss_end; 135 136 #ifdef CONFIG_SYS_TEXT_BASE 137 text_base = CONFIG_SYS_TEXT_BASE; 138 #else 139 text_base = CONFIG_SYS_MONITOR_BASE; 140 #endif 141 142 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 143 text_base, bss_start, bss_end); 144 #endif 145 146 return 0; 147 } 148 149 #ifdef CONFIG_SYSRESET 150 static int print_resetinfo(void) 151 { 152 struct udevice *dev; 153 char status[256]; 154 int ret; 155 156 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); 157 if (ret) { 158 debug("%s: No sysreset device found (error: %d)\n", 159 __func__, ret); 160 /* Not all boards have sysreset drivers available during early 161 * boot, so don't fail if one can't be found. 162 */ 163 return 0; 164 } 165 166 if (!sysreset_get_status(dev, status, sizeof(status))) 167 printf("%s", status); 168 169 return 0; 170 } 171 #endif 172 173 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) 174 static int print_cpuinfo(void) 175 { 176 struct udevice *dev; 177 char desc[512]; 178 int ret; 179 180 ret = uclass_first_device_err(UCLASS_CPU, &dev); 181 if (ret) { 182 debug("%s: Could not get CPU device (err = %d)\n", 183 __func__, ret); 184 return ret; 185 } 186 187 ret = cpu_get_desc(dev, desc, sizeof(desc)); 188 if (ret) { 189 debug("%s: Could not get CPU description (err = %d)\n", 190 dev->name, ret); 191 return ret; 192 } 193 194 printf("CPU: %s\n", desc); 195 196 return 0; 197 } 198 #endif 199 200 static int announce_dram_init(void) 201 { 202 puts("DRAM: "); 203 return 0; 204 } 205 206 static int show_dram_config(void) 207 { 208 unsigned long long size; 209 210 #ifdef CONFIG_NR_DRAM_BANKS 211 int i; 212 213 debug("\nRAM Configuration:\n"); 214 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 215 size += gd->bd->bi_dram[i].size; 216 debug("Bank #%d: %llx ", i, 217 (unsigned long long)(gd->bd->bi_dram[i].start)); 218 #ifdef DEBUG 219 print_size(gd->bd->bi_dram[i].size, "\n"); 220 #endif 221 } 222 debug("\nDRAM: "); 223 #else 224 size = gd->ram_size; 225 #endif 226 227 print_size(size, ""); 228 board_add_ram_info(0); 229 putc('\n'); 230 231 return 0; 232 } 233 234 __weak int dram_init_banksize(void) 235 { 236 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 237 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 238 gd->bd->bi_dram[0].size = get_effective_memsize(); 239 #endif 240 241 return 0; 242 } 243 244 #if defined(CONFIG_SYS_I2C) 245 static int init_func_i2c(void) 246 { 247 puts("I2C: "); 248 #ifdef CONFIG_SYS_I2C 249 i2c_init_all(); 250 #else 251 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 252 #endif 253 puts("ready\n"); 254 return 0; 255 } 256 #endif 257 258 #if defined(CONFIG_VID) 259 __weak int init_func_vid(void) 260 { 261 return 0; 262 } 263 #endif 264 265 #if defined(CONFIG_HARD_SPI) 266 static int init_func_spi(void) 267 { 268 puts("SPI: "); 269 spi_init(); 270 puts("ready\n"); 271 return 0; 272 } 273 #endif 274 275 static int setup_mon_len(void) 276 { 277 #if defined(__ARM__) || defined(__MICROBLAZE__) 278 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 279 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 280 gd->mon_len = (ulong)&_end - (ulong)_init; 281 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 282 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 283 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 284 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 285 #elif defined(CONFIG_SYS_MONITOR_BASE) 286 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 287 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 288 #endif 289 return 0; 290 } 291 292 static int setup_spl_handoff(void) 293 { 294 #if CONFIG_IS_ENABLED(HANDOFF) 295 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF, 296 sizeof(struct spl_handoff)); 297 debug("Found SPL hand-off info %p\n", gd->spl_handoff); 298 #endif 299 300 return 0; 301 } 302 303 __weak int arch_cpu_init(void) 304 { 305 return 0; 306 } 307 308 __weak int mach_cpu_init(void) 309 { 310 return 0; 311 } 312 313 /* Get the top of usable RAM */ 314 __weak ulong board_get_usable_ram_top(ulong total_size) 315 { 316 #ifdef CONFIG_SYS_SDRAM_BASE 317 /* 318 * Detect whether we have so much RAM that it goes past the end of our 319 * 32-bit address space. If so, clip the usable RAM so it doesn't. 320 */ 321 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 322 /* 323 * Will wrap back to top of 32-bit space when reservations 324 * are made. 325 */ 326 return 0; 327 #endif 328 return gd->ram_top; 329 } 330 331 static int setup_dest_addr(void) 332 { 333 debug("Monitor len: %08lX\n", gd->mon_len); 334 /* 335 * Ram is setup, size stored in gd !! 336 */ 337 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 338 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 339 /* 340 * Subtract specified amount of memory to hide so that it won't 341 * get "touched" at all by U-Boot. By fixing up gd->ram_size 342 * the Linux kernel should now get passed the now "corrected" 343 * memory size and won't touch it either. This should work 344 * for arch/ppc and arch/powerpc. Only Linux board ports in 345 * arch/powerpc with bootwrapper support, that recalculate the 346 * memory size from the SDRAM controller setup will have to 347 * get fixed. 348 */ 349 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 350 #endif 351 #ifdef CONFIG_SYS_SDRAM_BASE 352 gd->ram_base = CONFIG_SYS_SDRAM_BASE; 353 #endif 354 gd->ram_top = gd->ram_base + get_effective_memsize(); 355 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 356 gd->relocaddr = gd->ram_top; 357 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 358 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 359 /* 360 * We need to make sure the location we intend to put secondary core 361 * boot code is reserved and not used by any part of u-boot 362 */ 363 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 364 gd->relocaddr = determine_mp_bootpg(NULL); 365 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 366 } 367 #endif 368 return 0; 369 } 370 371 #ifdef CONFIG_PRAM 372 /* reserve protected RAM */ 373 static int reserve_pram(void) 374 { 375 ulong reg; 376 377 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 378 gd->relocaddr -= (reg << 10); /* size is in kB */ 379 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 380 gd->relocaddr); 381 return 0; 382 } 383 #endif /* CONFIG_PRAM */ 384 385 /* Round memory pointer down to next 4 kB limit */ 386 static int reserve_round_4k(void) 387 { 388 gd->relocaddr &= ~(4096 - 1); 389 return 0; 390 } 391 392 #ifdef CONFIG_ARM 393 __weak int reserve_mmu(void) 394 { 395 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 396 /* reserve TLB table */ 397 gd->arch.tlb_size = PGTABLE_SIZE; 398 gd->relocaddr -= gd->arch.tlb_size; 399 400 /* round down to next 64 kB limit */ 401 gd->relocaddr &= ~(0x10000 - 1); 402 403 gd->arch.tlb_addr = gd->relocaddr; 404 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 405 gd->arch.tlb_addr + gd->arch.tlb_size); 406 407 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 408 /* 409 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 410 * with location within secure ram. 411 */ 412 gd->arch.tlb_allocated = gd->arch.tlb_addr; 413 #endif 414 #endif 415 416 return 0; 417 } 418 #endif 419 420 static int reserve_video(void) 421 { 422 #ifdef CONFIG_DM_VIDEO 423 ulong addr; 424 int ret; 425 426 addr = gd->relocaddr; 427 ret = video_reserve(&addr); 428 if (ret) 429 return ret; 430 gd->relocaddr = addr; 431 #elif defined(CONFIG_LCD) 432 # ifdef CONFIG_FB_ADDR 433 gd->fb_base = CONFIG_FB_ADDR; 434 # else 435 /* reserve memory for LCD display (always full pages) */ 436 gd->relocaddr = lcd_setmem(gd->relocaddr); 437 gd->fb_base = gd->relocaddr; 438 # endif /* CONFIG_FB_ADDR */ 439 #elif defined(CONFIG_VIDEO) && \ 440 (!defined(CONFIG_PPC)) && \ 441 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 442 !defined(CONFIG_M68K) 443 /* reserve memory for video display (always full pages) */ 444 gd->relocaddr = video_setmem(gd->relocaddr); 445 gd->fb_base = gd->relocaddr; 446 #endif 447 448 return 0; 449 } 450 451 static int reserve_trace(void) 452 { 453 #ifdef CONFIG_TRACE 454 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 455 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 456 debug("Reserving %dk for trace data at: %08lx\n", 457 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 458 #endif 459 460 return 0; 461 } 462 463 static int reserve_uboot(void) 464 { 465 if (!(gd->flags & GD_FLG_SKIP_RELOC)) { 466 /* 467 * reserve memory for U-Boot code, data & bss 468 * round down to next 4 kB limit 469 */ 470 gd->relocaddr -= gd->mon_len; 471 gd->relocaddr &= ~(4096 - 1); 472 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 473 /* round down to next 64 kB limit so that IVPR stays aligned */ 474 gd->relocaddr &= ~(65536 - 1); 475 #endif 476 477 debug("Reserving %ldk for U-Boot at: %08lx\n", 478 gd->mon_len >> 10, gd->relocaddr); 479 } 480 481 gd->start_addr_sp = gd->relocaddr; 482 483 return 0; 484 } 485 486 /* reserve memory for malloc() area */ 487 static int reserve_malloc(void) 488 { 489 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 490 debug("Reserving %dk for malloc() at: %08lx\n", 491 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 492 return 0; 493 } 494 495 /* (permanently) allocate a Board Info struct */ 496 static int reserve_board(void) 497 { 498 if (!gd->bd) { 499 gd->start_addr_sp -= sizeof(bd_t); 500 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 501 memset(gd->bd, '\0', sizeof(bd_t)); 502 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 503 sizeof(bd_t), gd->start_addr_sp); 504 } 505 return 0; 506 } 507 508 static int setup_machine(void) 509 { 510 #ifdef CONFIG_MACH_TYPE 511 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 512 #endif 513 return 0; 514 } 515 516 static int reserve_global_data(void) 517 { 518 gd->start_addr_sp -= sizeof(gd_t); 519 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 520 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 521 sizeof(gd_t), gd->start_addr_sp); 522 return 0; 523 } 524 525 static int reserve_fdt(void) 526 { 527 #ifndef CONFIG_OF_EMBED 528 /* 529 * If the device tree is sitting immediately above our image then we 530 * must relocate it. If it is embedded in the data section, then it 531 * will be relocated with other data. 532 */ 533 if (gd->fdt_blob) { 534 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 535 536 gd->start_addr_sp -= gd->fdt_size; 537 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 538 debug("Reserving %lu Bytes for FDT at: %08lx\n", 539 gd->fdt_size, gd->start_addr_sp); 540 } 541 #endif 542 543 return 0; 544 } 545 546 static int reserve_bootstage(void) 547 { 548 #ifdef CONFIG_BOOTSTAGE 549 int size = bootstage_get_size(); 550 551 gd->start_addr_sp -= size; 552 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 553 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 554 gd->start_addr_sp); 555 #endif 556 557 return 0; 558 } 559 560 __weak int arch_reserve_stacks(void) 561 { 562 return 0; 563 } 564 565 static int reserve_stacks(void) 566 { 567 /* make stack pointer 16-byte aligned */ 568 gd->start_addr_sp -= 16; 569 gd->start_addr_sp &= ~0xf; 570 571 /* 572 * let the architecture-specific code tailor gd->start_addr_sp and 573 * gd->irq_sp 574 */ 575 return arch_reserve_stacks(); 576 } 577 578 static int reserve_bloblist(void) 579 { 580 #ifdef CONFIG_BLOBLIST 581 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE; 582 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE); 583 #endif 584 585 return 0; 586 } 587 588 static int display_new_sp(void) 589 { 590 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 591 592 return 0; 593 } 594 595 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 596 defined(CONFIG_SH) 597 static int setup_board_part1(void) 598 { 599 bd_t *bd = gd->bd; 600 601 /* 602 * Save local variables to board info struct 603 */ 604 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 605 bd->bi_memsize = gd->ram_size; /* size in bytes */ 606 607 #ifdef CONFIG_SYS_SRAM_BASE 608 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 609 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 610 #endif 611 612 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 613 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 614 #endif 615 #if defined(CONFIG_M68K) 616 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 617 #endif 618 #if defined(CONFIG_MPC83xx) 619 bd->bi_immrbar = CONFIG_SYS_IMMR; 620 #endif 621 622 return 0; 623 } 624 #endif 625 626 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 627 static int setup_board_part2(void) 628 { 629 bd_t *bd = gd->bd; 630 631 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 632 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 633 #if defined(CONFIG_CPM2) 634 bd->bi_cpmfreq = gd->arch.cpm_clk; 635 bd->bi_brgfreq = gd->arch.brg_clk; 636 bd->bi_sccfreq = gd->arch.scc_clk; 637 bd->bi_vco = gd->arch.vco_out; 638 #endif /* CONFIG_CPM2 */ 639 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 640 bd->bi_pcifreq = gd->pci_clk; 641 #endif 642 #if defined(CONFIG_EXTRA_CLOCK) 643 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 644 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 645 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 646 #endif 647 648 return 0; 649 } 650 #endif 651 652 #ifdef CONFIG_POST 653 static int init_post(void) 654 { 655 post_bootmode_init(); 656 post_run(NULL, POST_ROM | post_bootmode_get(0)); 657 658 return 0; 659 } 660 #endif 661 662 static int reloc_fdt(void) 663 { 664 #ifndef CONFIG_OF_EMBED 665 if (gd->flags & GD_FLG_SKIP_RELOC) 666 return 0; 667 if (gd->new_fdt) { 668 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 669 gd->fdt_blob = gd->new_fdt; 670 } 671 #endif 672 673 return 0; 674 } 675 676 static int reloc_bootstage(void) 677 { 678 #ifdef CONFIG_BOOTSTAGE 679 if (gd->flags & GD_FLG_SKIP_RELOC) 680 return 0; 681 if (gd->new_bootstage) { 682 int size = bootstage_get_size(); 683 684 debug("Copying bootstage from %p to %p, size %x\n", 685 gd->bootstage, gd->new_bootstage, size); 686 memcpy(gd->new_bootstage, gd->bootstage, size); 687 gd->bootstage = gd->new_bootstage; 688 } 689 #endif 690 691 return 0; 692 } 693 694 static int reloc_bloblist(void) 695 { 696 #ifdef CONFIG_BLOBLIST 697 if (gd->flags & GD_FLG_SKIP_RELOC) 698 return 0; 699 if (gd->new_bloblist) { 700 int size = CONFIG_BLOBLIST_SIZE; 701 702 debug("Copying bloblist from %p to %p, size %x\n", 703 gd->bloblist, gd->new_bloblist, size); 704 memcpy(gd->new_bloblist, gd->bloblist, size); 705 gd->bloblist = gd->new_bloblist; 706 } 707 #endif 708 709 return 0; 710 } 711 712 static int setup_reloc(void) 713 { 714 if (gd->flags & GD_FLG_SKIP_RELOC) { 715 debug("Skipping relocation due to flag\n"); 716 return 0; 717 } 718 719 #ifdef CONFIG_SYS_TEXT_BASE 720 #ifdef ARM 721 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 722 #elif defined(CONFIG_M68K) 723 /* 724 * On all ColdFire arch cpu, monitor code starts always 725 * just after the default vector table location, so at 0x400 726 */ 727 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 728 #else 729 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 730 #endif 731 #endif 732 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 733 734 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 735 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 736 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 737 gd->start_addr_sp); 738 739 return 0; 740 } 741 742 #ifdef CONFIG_OF_BOARD_FIXUP 743 static int fix_fdt(void) 744 { 745 return board_fix_fdt((void *)gd->fdt_blob); 746 } 747 #endif 748 749 /* ARM calls relocate_code from its crt0.S */ 750 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 751 !CONFIG_IS_ENABLED(X86_64) 752 753 static int jump_to_copy(void) 754 { 755 if (gd->flags & GD_FLG_SKIP_RELOC) 756 return 0; 757 /* 758 * x86 is special, but in a nice way. It uses a trampoline which 759 * enables the dcache if possible. 760 * 761 * For now, other archs use relocate_code(), which is implemented 762 * similarly for all archs. When we do generic relocation, hopefully 763 * we can make all archs enable the dcache prior to relocation. 764 */ 765 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 766 /* 767 * SDRAM and console are now initialised. The final stack can now 768 * be setup in SDRAM. Code execution will continue in Flash, but 769 * with the stack in SDRAM and Global Data in temporary memory 770 * (CPU cache) 771 */ 772 arch_setup_gd(gd->new_gd); 773 board_init_f_r_trampoline(gd->start_addr_sp); 774 #else 775 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 776 #endif 777 778 return 0; 779 } 780 #endif 781 782 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 783 static int initf_bootstage(void) 784 { 785 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 786 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 787 int ret; 788 789 ret = bootstage_init(!from_spl); 790 if (ret) 791 return ret; 792 if (from_spl) { 793 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 794 CONFIG_BOOTSTAGE_STASH_SIZE); 795 796 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 797 if (ret && ret != -ENOENT) { 798 debug("Failed to unstash bootstage: err=%d\n", ret); 799 return ret; 800 } 801 } 802 803 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 804 805 return 0; 806 } 807 808 static int initf_console_record(void) 809 { 810 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 811 return console_record_init(); 812 #else 813 return 0; 814 #endif 815 } 816 817 static int initf_dm(void) 818 { 819 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 820 int ret; 821 822 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 823 ret = dm_init_and_scan(true); 824 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 825 if (ret) 826 return ret; 827 #endif 828 #ifdef CONFIG_TIMER_EARLY 829 ret = dm_timer_init(); 830 if (ret) 831 return ret; 832 #endif 833 834 return 0; 835 } 836 837 /* Architecture-specific memory reservation */ 838 __weak int reserve_arch(void) 839 { 840 return 0; 841 } 842 843 __weak int arch_cpu_init_dm(void) 844 { 845 return 0; 846 } 847 848 static const init_fnc_t init_sequence_f[] = { 849 setup_mon_len, 850 #ifdef CONFIG_OF_CONTROL 851 fdtdec_setup, 852 #endif 853 #ifdef CONFIG_TRACE 854 trace_early_init, 855 #endif 856 initf_malloc, 857 log_init, 858 initf_bootstage, /* uses its own timer, so does not need DM */ 859 #ifdef CONFIG_BLOBLIST 860 bloblist_init, 861 #endif 862 setup_spl_handoff, 863 initf_console_record, 864 #if defined(CONFIG_HAVE_FSP) 865 arch_fsp_init, 866 #endif 867 arch_cpu_init, /* basic arch cpu dependent setup */ 868 mach_cpu_init, /* SoC/machine dependent CPU setup */ 869 initf_dm, 870 arch_cpu_init_dm, 871 #if defined(CONFIG_BOARD_EARLY_INIT_F) 872 board_early_init_f, 873 #endif 874 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 875 /* get CPU and bus clocks according to the environment variable */ 876 get_clocks, /* get CPU and bus clocks (etc.) */ 877 #endif 878 #if !defined(CONFIG_M68K) 879 timer_init, /* initialize timer */ 880 #endif 881 #if defined(CONFIG_BOARD_POSTCLK_INIT) 882 board_postclk_init, 883 #endif 884 env_init, /* initialize environment */ 885 init_baud_rate, /* initialze baudrate settings */ 886 serial_init, /* serial communications setup */ 887 console_init_f, /* stage 1 init of console */ 888 display_options, /* say that we are here */ 889 display_text_info, /* show debugging info if required */ 890 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 891 checkcpu, 892 #endif 893 #if defined(CONFIG_SYSRESET) 894 print_resetinfo, 895 #endif 896 #if defined(CONFIG_DISPLAY_CPUINFO) 897 print_cpuinfo, /* display cpu info (and speed) */ 898 #endif 899 #if defined(CONFIG_DTB_RESELECT) 900 embedded_dtb_select, 901 #endif 902 #if defined(CONFIG_DISPLAY_BOARDINFO) 903 show_board_info, 904 #endif 905 INIT_FUNC_WATCHDOG_INIT 906 #if defined(CONFIG_MISC_INIT_F) 907 misc_init_f, 908 #endif 909 INIT_FUNC_WATCHDOG_RESET 910 #if defined(CONFIG_SYS_I2C) 911 init_func_i2c, 912 #endif 913 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 914 init_func_vid, 915 #endif 916 #if defined(CONFIG_HARD_SPI) 917 init_func_spi, 918 #endif 919 announce_dram_init, 920 dram_init, /* configure available RAM banks */ 921 #ifdef CONFIG_POST 922 post_init_f, 923 #endif 924 INIT_FUNC_WATCHDOG_RESET 925 #if defined(CONFIG_SYS_DRAM_TEST) 926 testdram, 927 #endif /* CONFIG_SYS_DRAM_TEST */ 928 INIT_FUNC_WATCHDOG_RESET 929 930 #ifdef CONFIG_POST 931 init_post, 932 #endif 933 INIT_FUNC_WATCHDOG_RESET 934 /* 935 * Now that we have DRAM mapped and working, we can 936 * relocate the code and continue running from DRAM. 937 * 938 * Reserve memory at end of RAM for (top down in that order): 939 * - area that won't get touched by U-Boot and Linux (optional) 940 * - kernel log buffer 941 * - protected RAM 942 * - LCD framebuffer 943 * - monitor code 944 * - board info struct 945 */ 946 setup_dest_addr, 947 #ifdef CONFIG_PRAM 948 reserve_pram, 949 #endif 950 reserve_round_4k, 951 #ifdef CONFIG_ARM 952 reserve_mmu, 953 #endif 954 reserve_video, 955 reserve_trace, 956 reserve_uboot, 957 reserve_malloc, 958 reserve_board, 959 setup_machine, 960 reserve_global_data, 961 reserve_fdt, 962 reserve_bootstage, 963 reserve_bloblist, 964 reserve_arch, 965 reserve_stacks, 966 dram_init_banksize, 967 show_dram_config, 968 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 969 defined(CONFIG_SH) 970 setup_board_part1, 971 #endif 972 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 973 INIT_FUNC_WATCHDOG_RESET 974 setup_board_part2, 975 #endif 976 display_new_sp, 977 #ifdef CONFIG_OF_BOARD_FIXUP 978 fix_fdt, 979 #endif 980 INIT_FUNC_WATCHDOG_RESET 981 reloc_fdt, 982 reloc_bootstage, 983 reloc_bloblist, 984 setup_reloc, 985 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 986 copy_uboot_to_ram, 987 do_elf_reloc_fixups, 988 clear_bss, 989 #endif 990 #if defined(CONFIG_XTENSA) 991 clear_bss, 992 #endif 993 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 994 !CONFIG_IS_ENABLED(X86_64) 995 jump_to_copy, 996 #endif 997 NULL, 998 }; 999 1000 void board_init_f(ulong boot_flags) 1001 { 1002 gd->flags = boot_flags; 1003 gd->have_console = 0; 1004 1005 if (initcall_run_list(init_sequence_f)) 1006 hang(); 1007 1008 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 1009 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ 1010 !defined(CONFIG_ARC) 1011 /* NOTREACHED - jump_to_copy() does not return */ 1012 hang(); 1013 #endif 1014 } 1015 1016 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 1017 /* 1018 * For now this code is only used on x86. 1019 * 1020 * init_sequence_f_r is the list of init functions which are run when 1021 * U-Boot is executing from Flash with a semi-limited 'C' environment. 1022 * The following limitations must be considered when implementing an 1023 * '_f_r' function: 1024 * - 'static' variables are read-only 1025 * - Global Data (gd->xxx) is read/write 1026 * 1027 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 1028 * supported). It _should_, if possible, copy global data to RAM and 1029 * initialise the CPU caches (to speed up the relocation process) 1030 * 1031 * NOTE: At present only x86 uses this route, but it is intended that 1032 * all archs will move to this when generic relocation is implemented. 1033 */ 1034 static const init_fnc_t init_sequence_f_r[] = { 1035 #if !CONFIG_IS_ENABLED(X86_64) 1036 init_cache_f_r, 1037 #endif 1038 1039 NULL, 1040 }; 1041 1042 void board_init_f_r(void) 1043 { 1044 if (initcall_run_list(init_sequence_f_r)) 1045 hang(); 1046 1047 /* 1048 * The pre-relocation drivers may be using memory that has now gone 1049 * away. Mark serial as unavailable - this will fall back to the debug 1050 * UART if available. 1051 * 1052 * Do the same with log drivers since the memory may not be available. 1053 */ 1054 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1055 #ifdef CONFIG_TIMER 1056 gd->timer = NULL; 1057 #endif 1058 1059 /* 1060 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1061 * Transfer execution from Flash to RAM by calculating the address 1062 * of the in-RAM copy of board_init_r() and calling it 1063 */ 1064 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1065 1066 /* NOTREACHED - board_init_r() does not return */ 1067 hang(); 1068 } 1069 #endif /* CONFIG_X86 */ 1070