1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2002-2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2002 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 9 * Marius Groeger <mgroeger@sysgo.de> 10 */ 11 12 #include <common.h> 13 #include <bloblist.h> 14 #include <console.h> 15 #include <cpu.h> 16 #include <dm.h> 17 #include <environment.h> 18 #include <fdtdec.h> 19 #include <fs.h> 20 #include <i2c.h> 21 #include <initcall.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <sysreset.h> 30 #include <timer.h> 31 #include <trace.h> 32 #include <video.h> 33 #include <watchdog.h> 34 #ifdef CONFIG_MACH_TYPE 35 #include <asm/mach-types.h> 36 #endif 37 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 38 #include <asm/mp.h> 39 #endif 40 #include <asm/io.h> 41 #include <asm/sections.h> 42 #include <dm/root.h> 43 #include <linux/errno.h> 44 45 /* 46 * Pointer to initial global data area 47 * 48 * Here we initialize it if needed. 49 */ 50 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 51 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 53 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 54 #else 55 DECLARE_GLOBAL_DATA_PTR; 56 #endif 57 58 /* 59 * TODO(sjg@chromium.org): IMO this code should be 60 * refactored to a single function, something like: 61 * 62 * void led_set_state(enum led_colour_t colour, int on); 63 */ 64 /************************************************************************ 65 * Coloured LED functionality 66 ************************************************************************ 67 * May be supplied by boards if desired 68 */ 69 __weak void coloured_LED_init(void) {} 70 __weak void red_led_on(void) {} 71 __weak void red_led_off(void) {} 72 __weak void green_led_on(void) {} 73 __weak void green_led_off(void) {} 74 __weak void yellow_led_on(void) {} 75 __weak void yellow_led_off(void) {} 76 __weak void blue_led_on(void) {} 77 __weak void blue_led_off(void) {} 78 79 /* 80 * Why is gd allocated a register? Prior to reloc it might be better to 81 * just pass it around to each function in this file? 82 * 83 * After reloc one could argue that it is hardly used and doesn't need 84 * to be in a register. Or if it is it should perhaps hold pointers to all 85 * global data for all modules, so that post-reloc we can avoid the massive 86 * literal pool we get on ARM. Or perhaps just encourage each module to use 87 * a structure... 88 */ 89 90 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 91 static int init_func_watchdog_init(void) 92 { 93 # if defined(CONFIG_HW_WATCHDOG) && \ 94 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 95 defined(CONFIG_SH) || \ 96 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 97 defined(CONFIG_IMX_WATCHDOG)) 98 hw_watchdog_init(); 99 puts(" Watchdog enabled\n"); 100 # endif 101 WATCHDOG_RESET(); 102 103 return 0; 104 } 105 106 int init_func_watchdog_reset(void) 107 { 108 WATCHDOG_RESET(); 109 110 return 0; 111 } 112 #endif /* CONFIG_WATCHDOG */ 113 114 __weak void board_add_ram_info(int use_default) 115 { 116 /* please define platform specific board_add_ram_info() */ 117 } 118 119 static int init_baud_rate(void) 120 { 121 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 122 return 0; 123 } 124 125 static int display_text_info(void) 126 { 127 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 128 ulong bss_start, bss_end, text_base; 129 130 bss_start = (ulong)&__bss_start; 131 bss_end = (ulong)&__bss_end; 132 133 #ifdef CONFIG_SYS_TEXT_BASE 134 text_base = CONFIG_SYS_TEXT_BASE; 135 #else 136 text_base = CONFIG_SYS_MONITOR_BASE; 137 #endif 138 139 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 140 text_base, bss_start, bss_end); 141 #endif 142 143 return 0; 144 } 145 146 #ifdef CONFIG_SYSRESET 147 static int print_resetinfo(void) 148 { 149 struct udevice *dev; 150 char status[256]; 151 int ret; 152 153 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); 154 if (ret) { 155 debug("%s: No sysreset device found (error: %d)\n", 156 __func__, ret); 157 /* Not all boards have sysreset drivers available during early 158 * boot, so don't fail if one can't be found. 159 */ 160 return 0; 161 } 162 163 if (!sysreset_get_status(dev, status, sizeof(status))) 164 printf("%s", status); 165 166 return 0; 167 } 168 #endif 169 170 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) 171 static int print_cpuinfo(void) 172 { 173 struct udevice *dev; 174 char desc[512]; 175 int ret; 176 177 ret = uclass_first_device_err(UCLASS_CPU, &dev); 178 if (ret) { 179 debug("%s: Could not get CPU device (err = %d)\n", 180 __func__, ret); 181 return ret; 182 } 183 184 ret = cpu_get_desc(dev, desc, sizeof(desc)); 185 if (ret) { 186 debug("%s: Could not get CPU description (err = %d)\n", 187 dev->name, ret); 188 return ret; 189 } 190 191 printf("CPU: %s\n", desc); 192 193 return 0; 194 } 195 #endif 196 197 static int announce_dram_init(void) 198 { 199 puts("DRAM: "); 200 return 0; 201 } 202 203 static int show_dram_config(void) 204 { 205 unsigned long long size; 206 207 #ifdef CONFIG_NR_DRAM_BANKS 208 int i; 209 210 debug("\nRAM Configuration:\n"); 211 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 212 size += gd->bd->bi_dram[i].size; 213 debug("Bank #%d: %llx ", i, 214 (unsigned long long)(gd->bd->bi_dram[i].start)); 215 #ifdef DEBUG 216 print_size(gd->bd->bi_dram[i].size, "\n"); 217 #endif 218 } 219 debug("\nDRAM: "); 220 #else 221 size = gd->ram_size; 222 #endif 223 224 print_size(size, ""); 225 board_add_ram_info(0); 226 putc('\n'); 227 228 return 0; 229 } 230 231 __weak int dram_init_banksize(void) 232 { 233 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 234 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 235 gd->bd->bi_dram[0].size = get_effective_memsize(); 236 #endif 237 238 return 0; 239 } 240 241 #if defined(CONFIG_SYS_I2C) 242 static int init_func_i2c(void) 243 { 244 puts("I2C: "); 245 #ifdef CONFIG_SYS_I2C 246 i2c_init_all(); 247 #else 248 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 249 #endif 250 puts("ready\n"); 251 return 0; 252 } 253 #endif 254 255 #if defined(CONFIG_VID) 256 __weak int init_func_vid(void) 257 { 258 return 0; 259 } 260 #endif 261 262 #if defined(CONFIG_HARD_SPI) 263 static int init_func_spi(void) 264 { 265 puts("SPI: "); 266 spi_init(); 267 puts("ready\n"); 268 return 0; 269 } 270 #endif 271 272 static int setup_mon_len(void) 273 { 274 #if defined(__ARM__) || defined(__MICROBLAZE__) 275 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 276 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 277 gd->mon_len = (ulong)&_end - (ulong)_init; 278 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 279 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 280 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 281 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 282 #elif defined(CONFIG_SYS_MONITOR_BASE) 283 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 284 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 285 #endif 286 return 0; 287 } 288 289 __weak int arch_cpu_init(void) 290 { 291 return 0; 292 } 293 294 __weak int mach_cpu_init(void) 295 { 296 return 0; 297 } 298 299 /* Get the top of usable RAM */ 300 __weak ulong board_get_usable_ram_top(ulong total_size) 301 { 302 #ifdef CONFIG_SYS_SDRAM_BASE 303 /* 304 * Detect whether we have so much RAM that it goes past the end of our 305 * 32-bit address space. If so, clip the usable RAM so it doesn't. 306 */ 307 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 308 /* 309 * Will wrap back to top of 32-bit space when reservations 310 * are made. 311 */ 312 return 0; 313 #endif 314 return gd->ram_top; 315 } 316 317 static int setup_dest_addr(void) 318 { 319 debug("Monitor len: %08lX\n", gd->mon_len); 320 /* 321 * Ram is setup, size stored in gd !! 322 */ 323 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 324 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 325 /* 326 * Subtract specified amount of memory to hide so that it won't 327 * get "touched" at all by U-Boot. By fixing up gd->ram_size 328 * the Linux kernel should now get passed the now "corrected" 329 * memory size and won't touch it either. This should work 330 * for arch/ppc and arch/powerpc. Only Linux board ports in 331 * arch/powerpc with bootwrapper support, that recalculate the 332 * memory size from the SDRAM controller setup will have to 333 * get fixed. 334 */ 335 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 336 #endif 337 #ifdef CONFIG_SYS_SDRAM_BASE 338 gd->ram_base = CONFIG_SYS_SDRAM_BASE; 339 #endif 340 gd->ram_top = gd->ram_base + get_effective_memsize(); 341 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 342 gd->relocaddr = gd->ram_top; 343 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 344 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 345 /* 346 * We need to make sure the location we intend to put secondary core 347 * boot code is reserved and not used by any part of u-boot 348 */ 349 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 350 gd->relocaddr = determine_mp_bootpg(NULL); 351 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 352 } 353 #endif 354 return 0; 355 } 356 357 #ifdef CONFIG_PRAM 358 /* reserve protected RAM */ 359 static int reserve_pram(void) 360 { 361 ulong reg; 362 363 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 364 gd->relocaddr -= (reg << 10); /* size is in kB */ 365 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 366 gd->relocaddr); 367 return 0; 368 } 369 #endif /* CONFIG_PRAM */ 370 371 /* Round memory pointer down to next 4 kB limit */ 372 static int reserve_round_4k(void) 373 { 374 gd->relocaddr &= ~(4096 - 1); 375 return 0; 376 } 377 378 #ifdef CONFIG_ARM 379 __weak int reserve_mmu(void) 380 { 381 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 382 /* reserve TLB table */ 383 gd->arch.tlb_size = PGTABLE_SIZE; 384 gd->relocaddr -= gd->arch.tlb_size; 385 386 /* round down to next 64 kB limit */ 387 gd->relocaddr &= ~(0x10000 - 1); 388 389 gd->arch.tlb_addr = gd->relocaddr; 390 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 391 gd->arch.tlb_addr + gd->arch.tlb_size); 392 393 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 394 /* 395 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 396 * with location within secure ram. 397 */ 398 gd->arch.tlb_allocated = gd->arch.tlb_addr; 399 #endif 400 #endif 401 402 return 0; 403 } 404 #endif 405 406 static int reserve_video(void) 407 { 408 #ifdef CONFIG_DM_VIDEO 409 ulong addr; 410 int ret; 411 412 addr = gd->relocaddr; 413 ret = video_reserve(&addr); 414 if (ret) 415 return ret; 416 gd->relocaddr = addr; 417 #elif defined(CONFIG_LCD) 418 # ifdef CONFIG_FB_ADDR 419 gd->fb_base = CONFIG_FB_ADDR; 420 # else 421 /* reserve memory for LCD display (always full pages) */ 422 gd->relocaddr = lcd_setmem(gd->relocaddr); 423 gd->fb_base = gd->relocaddr; 424 # endif /* CONFIG_FB_ADDR */ 425 #elif defined(CONFIG_VIDEO) && \ 426 (!defined(CONFIG_PPC)) && \ 427 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 428 !defined(CONFIG_M68K) 429 /* reserve memory for video display (always full pages) */ 430 gd->relocaddr = video_setmem(gd->relocaddr); 431 gd->fb_base = gd->relocaddr; 432 #endif 433 434 return 0; 435 } 436 437 static int reserve_trace(void) 438 { 439 #ifdef CONFIG_TRACE 440 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 441 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 442 debug("Reserving %dk for trace data at: %08lx\n", 443 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 444 #endif 445 446 return 0; 447 } 448 449 static int reserve_uboot(void) 450 { 451 if (!(gd->flags & GD_FLG_SKIP_RELOC)) { 452 /* 453 * reserve memory for U-Boot code, data & bss 454 * round down to next 4 kB limit 455 */ 456 gd->relocaddr -= gd->mon_len; 457 gd->relocaddr &= ~(4096 - 1); 458 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 459 /* round down to next 64 kB limit so that IVPR stays aligned */ 460 gd->relocaddr &= ~(65536 - 1); 461 #endif 462 463 debug("Reserving %ldk for U-Boot at: %08lx\n", 464 gd->mon_len >> 10, gd->relocaddr); 465 } 466 467 gd->start_addr_sp = gd->relocaddr; 468 469 return 0; 470 } 471 472 /* reserve memory for malloc() area */ 473 static int reserve_malloc(void) 474 { 475 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 476 debug("Reserving %dk for malloc() at: %08lx\n", 477 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 478 return 0; 479 } 480 481 /* (permanently) allocate a Board Info struct */ 482 static int reserve_board(void) 483 { 484 if (!gd->bd) { 485 gd->start_addr_sp -= sizeof(bd_t); 486 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 487 memset(gd->bd, '\0', sizeof(bd_t)); 488 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 489 sizeof(bd_t), gd->start_addr_sp); 490 } 491 return 0; 492 } 493 494 static int setup_machine(void) 495 { 496 #ifdef CONFIG_MACH_TYPE 497 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 498 #endif 499 return 0; 500 } 501 502 static int reserve_global_data(void) 503 { 504 gd->start_addr_sp -= sizeof(gd_t); 505 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 506 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 507 sizeof(gd_t), gd->start_addr_sp); 508 return 0; 509 } 510 511 static int reserve_fdt(void) 512 { 513 #ifndef CONFIG_OF_EMBED 514 /* 515 * If the device tree is sitting immediately above our image then we 516 * must relocate it. If it is embedded in the data section, then it 517 * will be relocated with other data. 518 */ 519 if (gd->fdt_blob) { 520 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 521 522 gd->start_addr_sp -= gd->fdt_size; 523 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 524 debug("Reserving %lu Bytes for FDT at: %08lx\n", 525 gd->fdt_size, gd->start_addr_sp); 526 } 527 #endif 528 529 return 0; 530 } 531 532 static int reserve_bootstage(void) 533 { 534 #ifdef CONFIG_BOOTSTAGE 535 int size = bootstage_get_size(); 536 537 gd->start_addr_sp -= size; 538 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 539 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 540 gd->start_addr_sp); 541 #endif 542 543 return 0; 544 } 545 546 __weak int arch_reserve_stacks(void) 547 { 548 return 0; 549 } 550 551 static int reserve_stacks(void) 552 { 553 /* make stack pointer 16-byte aligned */ 554 gd->start_addr_sp -= 16; 555 gd->start_addr_sp &= ~0xf; 556 557 /* 558 * let the architecture-specific code tailor gd->start_addr_sp and 559 * gd->irq_sp 560 */ 561 return arch_reserve_stacks(); 562 } 563 564 static int reserve_bloblist(void) 565 { 566 #ifdef CONFIG_BLOBLIST 567 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE; 568 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE); 569 #endif 570 571 return 0; 572 } 573 574 static int display_new_sp(void) 575 { 576 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 577 578 return 0; 579 } 580 581 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 582 defined(CONFIG_SH) 583 static int setup_board_part1(void) 584 { 585 bd_t *bd = gd->bd; 586 587 /* 588 * Save local variables to board info struct 589 */ 590 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 591 bd->bi_memsize = gd->ram_size; /* size in bytes */ 592 593 #ifdef CONFIG_SYS_SRAM_BASE 594 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 595 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 596 #endif 597 598 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 599 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 600 #endif 601 #if defined(CONFIG_M68K) 602 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 603 #endif 604 #if defined(CONFIG_MPC83xx) 605 bd->bi_immrbar = CONFIG_SYS_IMMR; 606 #endif 607 608 return 0; 609 } 610 #endif 611 612 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 613 static int setup_board_part2(void) 614 { 615 bd_t *bd = gd->bd; 616 617 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 618 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 619 #if defined(CONFIG_CPM2) 620 bd->bi_cpmfreq = gd->arch.cpm_clk; 621 bd->bi_brgfreq = gd->arch.brg_clk; 622 bd->bi_sccfreq = gd->arch.scc_clk; 623 bd->bi_vco = gd->arch.vco_out; 624 #endif /* CONFIG_CPM2 */ 625 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 626 bd->bi_pcifreq = gd->pci_clk; 627 #endif 628 #if defined(CONFIG_EXTRA_CLOCK) 629 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 630 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 631 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 632 #endif 633 634 return 0; 635 } 636 #endif 637 638 #ifdef CONFIG_POST 639 static int init_post(void) 640 { 641 post_bootmode_init(); 642 post_run(NULL, POST_ROM | post_bootmode_get(0)); 643 644 return 0; 645 } 646 #endif 647 648 static int reloc_fdt(void) 649 { 650 #ifndef CONFIG_OF_EMBED 651 if (gd->flags & GD_FLG_SKIP_RELOC) 652 return 0; 653 if (gd->new_fdt) { 654 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 655 gd->fdt_blob = gd->new_fdt; 656 } 657 #endif 658 659 return 0; 660 } 661 662 static int reloc_bootstage(void) 663 { 664 #ifdef CONFIG_BOOTSTAGE 665 if (gd->flags & GD_FLG_SKIP_RELOC) 666 return 0; 667 if (gd->new_bootstage) { 668 int size = bootstage_get_size(); 669 670 debug("Copying bootstage from %p to %p, size %x\n", 671 gd->bootstage, gd->new_bootstage, size); 672 memcpy(gd->new_bootstage, gd->bootstage, size); 673 gd->bootstage = gd->new_bootstage; 674 } 675 #endif 676 677 return 0; 678 } 679 680 static int reloc_bloblist(void) 681 { 682 #ifdef CONFIG_BLOBLIST 683 if (gd->flags & GD_FLG_SKIP_RELOC) 684 return 0; 685 if (gd->new_bloblist) { 686 int size = CONFIG_BLOBLIST_SIZE; 687 688 debug("Copying bloblist from %p to %p, size %x\n", 689 gd->bloblist, gd->new_bloblist, size); 690 memcpy(gd->new_bloblist, gd->bloblist, size); 691 gd->bloblist = gd->new_bloblist; 692 } 693 #endif 694 695 return 0; 696 } 697 698 static int setup_reloc(void) 699 { 700 if (gd->flags & GD_FLG_SKIP_RELOC) { 701 debug("Skipping relocation due to flag\n"); 702 return 0; 703 } 704 705 #ifdef CONFIG_SYS_TEXT_BASE 706 #ifdef ARM 707 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 708 #elif defined(CONFIG_M68K) 709 /* 710 * On all ColdFire arch cpu, monitor code starts always 711 * just after the default vector table location, so at 0x400 712 */ 713 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 714 #else 715 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 716 #endif 717 #endif 718 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 719 720 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 721 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 722 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 723 gd->start_addr_sp); 724 725 return 0; 726 } 727 728 #ifdef CONFIG_OF_BOARD_FIXUP 729 static int fix_fdt(void) 730 { 731 return board_fix_fdt((void *)gd->fdt_blob); 732 } 733 #endif 734 735 /* ARM calls relocate_code from its crt0.S */ 736 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 737 !CONFIG_IS_ENABLED(X86_64) 738 739 static int jump_to_copy(void) 740 { 741 if (gd->flags & GD_FLG_SKIP_RELOC) 742 return 0; 743 /* 744 * x86 is special, but in a nice way. It uses a trampoline which 745 * enables the dcache if possible. 746 * 747 * For now, other archs use relocate_code(), which is implemented 748 * similarly for all archs. When we do generic relocation, hopefully 749 * we can make all archs enable the dcache prior to relocation. 750 */ 751 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 752 /* 753 * SDRAM and console are now initialised. The final stack can now 754 * be setup in SDRAM. Code execution will continue in Flash, but 755 * with the stack in SDRAM and Global Data in temporary memory 756 * (CPU cache) 757 */ 758 arch_setup_gd(gd->new_gd); 759 board_init_f_r_trampoline(gd->start_addr_sp); 760 #else 761 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 762 #endif 763 764 return 0; 765 } 766 #endif 767 768 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 769 static int initf_bootstage(void) 770 { 771 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 772 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 773 int ret; 774 775 ret = bootstage_init(!from_spl); 776 if (ret) 777 return ret; 778 if (from_spl) { 779 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 780 CONFIG_BOOTSTAGE_STASH_SIZE); 781 782 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 783 if (ret && ret != -ENOENT) { 784 debug("Failed to unstash bootstage: err=%d\n", ret); 785 return ret; 786 } 787 } 788 789 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 790 791 return 0; 792 } 793 794 static int initf_console_record(void) 795 { 796 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 797 return console_record_init(); 798 #else 799 return 0; 800 #endif 801 } 802 803 static int initf_dm(void) 804 { 805 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 806 int ret; 807 808 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 809 ret = dm_init_and_scan(true); 810 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 811 if (ret) 812 return ret; 813 #endif 814 #ifdef CONFIG_TIMER_EARLY 815 ret = dm_timer_init(); 816 if (ret) 817 return ret; 818 #endif 819 820 return 0; 821 } 822 823 /* Architecture-specific memory reservation */ 824 __weak int reserve_arch(void) 825 { 826 return 0; 827 } 828 829 __weak int arch_cpu_init_dm(void) 830 { 831 return 0; 832 } 833 834 static const init_fnc_t init_sequence_f[] = { 835 setup_mon_len, 836 #ifdef CONFIG_OF_CONTROL 837 fdtdec_setup, 838 #endif 839 #ifdef CONFIG_TRACE 840 trace_early_init, 841 #endif 842 initf_malloc, 843 log_init, 844 initf_bootstage, /* uses its own timer, so does not need DM */ 845 #ifdef CONFIG_BLOBLIST 846 bloblist_init, 847 #endif 848 initf_console_record, 849 #if defined(CONFIG_HAVE_FSP) 850 arch_fsp_init, 851 #endif 852 arch_cpu_init, /* basic arch cpu dependent setup */ 853 mach_cpu_init, /* SoC/machine dependent CPU setup */ 854 initf_dm, 855 arch_cpu_init_dm, 856 #if defined(CONFIG_BOARD_EARLY_INIT_F) 857 board_early_init_f, 858 #endif 859 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 860 /* get CPU and bus clocks according to the environment variable */ 861 get_clocks, /* get CPU and bus clocks (etc.) */ 862 #endif 863 #if !defined(CONFIG_M68K) 864 timer_init, /* initialize timer */ 865 #endif 866 #if defined(CONFIG_BOARD_POSTCLK_INIT) 867 board_postclk_init, 868 #endif 869 env_init, /* initialize environment */ 870 init_baud_rate, /* initialze baudrate settings */ 871 serial_init, /* serial communications setup */ 872 console_init_f, /* stage 1 init of console */ 873 display_options, /* say that we are here */ 874 display_text_info, /* show debugging info if required */ 875 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 876 checkcpu, 877 #endif 878 #if defined(CONFIG_SYSRESET) 879 print_resetinfo, 880 #endif 881 #if defined(CONFIG_DISPLAY_CPUINFO) 882 print_cpuinfo, /* display cpu info (and speed) */ 883 #endif 884 #if defined(CONFIG_DTB_RESELECT) 885 embedded_dtb_select, 886 #endif 887 #if defined(CONFIG_DISPLAY_BOARDINFO) 888 show_board_info, 889 #endif 890 INIT_FUNC_WATCHDOG_INIT 891 #if defined(CONFIG_MISC_INIT_F) 892 misc_init_f, 893 #endif 894 INIT_FUNC_WATCHDOG_RESET 895 #if defined(CONFIG_SYS_I2C) 896 init_func_i2c, 897 #endif 898 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 899 init_func_vid, 900 #endif 901 #if defined(CONFIG_HARD_SPI) 902 init_func_spi, 903 #endif 904 announce_dram_init, 905 dram_init, /* configure available RAM banks */ 906 #ifdef CONFIG_POST 907 post_init_f, 908 #endif 909 INIT_FUNC_WATCHDOG_RESET 910 #if defined(CONFIG_SYS_DRAM_TEST) 911 testdram, 912 #endif /* CONFIG_SYS_DRAM_TEST */ 913 INIT_FUNC_WATCHDOG_RESET 914 915 #ifdef CONFIG_POST 916 init_post, 917 #endif 918 INIT_FUNC_WATCHDOG_RESET 919 /* 920 * Now that we have DRAM mapped and working, we can 921 * relocate the code and continue running from DRAM. 922 * 923 * Reserve memory at end of RAM for (top down in that order): 924 * - area that won't get touched by U-Boot and Linux (optional) 925 * - kernel log buffer 926 * - protected RAM 927 * - LCD framebuffer 928 * - monitor code 929 * - board info struct 930 */ 931 setup_dest_addr, 932 #ifdef CONFIG_PRAM 933 reserve_pram, 934 #endif 935 reserve_round_4k, 936 #ifdef CONFIG_ARM 937 reserve_mmu, 938 #endif 939 reserve_video, 940 reserve_trace, 941 reserve_uboot, 942 reserve_malloc, 943 reserve_board, 944 setup_machine, 945 reserve_global_data, 946 reserve_fdt, 947 reserve_bootstage, 948 reserve_bloblist, 949 reserve_arch, 950 reserve_stacks, 951 dram_init_banksize, 952 show_dram_config, 953 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 954 defined(CONFIG_SH) 955 setup_board_part1, 956 #endif 957 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 958 INIT_FUNC_WATCHDOG_RESET 959 setup_board_part2, 960 #endif 961 display_new_sp, 962 #ifdef CONFIG_OF_BOARD_FIXUP 963 fix_fdt, 964 #endif 965 INIT_FUNC_WATCHDOG_RESET 966 reloc_fdt, 967 reloc_bootstage, 968 reloc_bloblist, 969 setup_reloc, 970 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 971 copy_uboot_to_ram, 972 do_elf_reloc_fixups, 973 clear_bss, 974 #endif 975 #if defined(CONFIG_XTENSA) 976 clear_bss, 977 #endif 978 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 979 !CONFIG_IS_ENABLED(X86_64) 980 jump_to_copy, 981 #endif 982 NULL, 983 }; 984 985 void board_init_f(ulong boot_flags) 986 { 987 gd->flags = boot_flags; 988 gd->have_console = 0; 989 990 if (initcall_run_list(init_sequence_f)) 991 hang(); 992 993 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 994 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ 995 !defined(CONFIG_ARC) 996 /* NOTREACHED - jump_to_copy() does not return */ 997 hang(); 998 #endif 999 } 1000 1001 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 1002 /* 1003 * For now this code is only used on x86. 1004 * 1005 * init_sequence_f_r is the list of init functions which are run when 1006 * U-Boot is executing from Flash with a semi-limited 'C' environment. 1007 * The following limitations must be considered when implementing an 1008 * '_f_r' function: 1009 * - 'static' variables are read-only 1010 * - Global Data (gd->xxx) is read/write 1011 * 1012 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 1013 * supported). It _should_, if possible, copy global data to RAM and 1014 * initialise the CPU caches (to speed up the relocation process) 1015 * 1016 * NOTE: At present only x86 uses this route, but it is intended that 1017 * all archs will move to this when generic relocation is implemented. 1018 */ 1019 static const init_fnc_t init_sequence_f_r[] = { 1020 #if !CONFIG_IS_ENABLED(X86_64) 1021 init_cache_f_r, 1022 #endif 1023 1024 NULL, 1025 }; 1026 1027 void board_init_f_r(void) 1028 { 1029 if (initcall_run_list(init_sequence_f_r)) 1030 hang(); 1031 1032 /* 1033 * The pre-relocation drivers may be using memory that has now gone 1034 * away. Mark serial as unavailable - this will fall back to the debug 1035 * UART if available. 1036 * 1037 * Do the same with log drivers since the memory may not be available. 1038 */ 1039 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1040 #ifdef CONFIG_TIMER 1041 gd->timer = NULL; 1042 #endif 1043 1044 /* 1045 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1046 * Transfer execution from Flash to RAM by calculating the address 1047 * of the in-RAM copy of board_init_r() and calling it 1048 */ 1049 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1050 1051 /* NOTREACHED - board_init_r() does not return */ 1052 hang(); 1053 } 1054 #endif /* CONFIG_X86 */ 1055