1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <malloc.h> 22 #include <mapmem.h> 23 #include <os.h> 24 #include <post.h> 25 #include <relocate.h> 26 #include <spi.h> 27 #include <status_led.h> 28 #include <timer.h> 29 #include <trace.h> 30 #include <video.h> 31 #include <watchdog.h> 32 #ifdef CONFIG_MACH_TYPE 33 #include <asm/mach-types.h> 34 #endif 35 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 36 #include <asm/mp.h> 37 #endif 38 #include <asm/io.h> 39 #include <asm/sections.h> 40 #include <dm/root.h> 41 #include <linux/errno.h> 42 43 /* 44 * Pointer to initial global data area 45 * 46 * Here we initialize it if needed. 47 */ 48 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 49 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 50 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 51 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 52 #else 53 DECLARE_GLOBAL_DATA_PTR; 54 #endif 55 56 /* 57 * TODO(sjg@chromium.org): IMO this code should be 58 * refactored to a single function, something like: 59 * 60 * void led_set_state(enum led_colour_t colour, int on); 61 */ 62 /************************************************************************ 63 * Coloured LED functionality 64 ************************************************************************ 65 * May be supplied by boards if desired 66 */ 67 __weak void coloured_LED_init(void) {} 68 __weak void red_led_on(void) {} 69 __weak void red_led_off(void) {} 70 __weak void green_led_on(void) {} 71 __weak void green_led_off(void) {} 72 __weak void yellow_led_on(void) {} 73 __weak void yellow_led_off(void) {} 74 __weak void blue_led_on(void) {} 75 __weak void blue_led_off(void) {} 76 77 /* 78 * Why is gd allocated a register? Prior to reloc it might be better to 79 * just pass it around to each function in this file? 80 * 81 * After reloc one could argue that it is hardly used and doesn't need 82 * to be in a register. Or if it is it should perhaps hold pointers to all 83 * global data for all modules, so that post-reloc we can avoid the massive 84 * literal pool we get on ARM. Or perhaps just encourage each module to use 85 * a structure... 86 */ 87 88 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 89 static int init_func_watchdog_init(void) 90 { 91 # if defined(CONFIG_HW_WATCHDOG) && \ 92 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 93 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 94 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 95 defined(CONFIG_IMX_WATCHDOG)) 96 hw_watchdog_init(); 97 puts(" Watchdog enabled\n"); 98 # endif 99 WATCHDOG_RESET(); 100 101 return 0; 102 } 103 104 int init_func_watchdog_reset(void) 105 { 106 WATCHDOG_RESET(); 107 108 return 0; 109 } 110 #endif /* CONFIG_WATCHDOG */ 111 112 __weak void board_add_ram_info(int use_default) 113 { 114 /* please define platform specific board_add_ram_info() */ 115 } 116 117 static int init_baud_rate(void) 118 { 119 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 120 return 0; 121 } 122 123 static int display_text_info(void) 124 { 125 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 126 ulong bss_start, bss_end, text_base; 127 128 bss_start = (ulong)&__bss_start; 129 bss_end = (ulong)&__bss_end; 130 131 #ifdef CONFIG_SYS_TEXT_BASE 132 text_base = CONFIG_SYS_TEXT_BASE; 133 #else 134 text_base = CONFIG_SYS_MONITOR_BASE; 135 #endif 136 137 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 138 text_base, bss_start, bss_end); 139 #endif 140 141 return 0; 142 } 143 144 static int announce_dram_init(void) 145 { 146 puts("DRAM: "); 147 return 0; 148 } 149 150 static int show_dram_config(void) 151 { 152 unsigned long long size; 153 154 #ifdef CONFIG_NR_DRAM_BANKS 155 int i; 156 157 debug("\nRAM Configuration:\n"); 158 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 159 size += gd->bd->bi_dram[i].size; 160 debug("Bank #%d: %llx ", i, 161 (unsigned long long)(gd->bd->bi_dram[i].start)); 162 #ifdef DEBUG 163 print_size(gd->bd->bi_dram[i].size, "\n"); 164 #endif 165 } 166 debug("\nDRAM: "); 167 #else 168 size = gd->ram_size; 169 #endif 170 171 print_size(size, ""); 172 board_add_ram_info(0); 173 putc('\n'); 174 175 return 0; 176 } 177 178 __weak int dram_init_banksize(void) 179 { 180 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 181 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 182 gd->bd->bi_dram[0].size = get_effective_memsize(); 183 #endif 184 185 return 0; 186 } 187 188 #if defined(CONFIG_SYS_I2C) 189 static int init_func_i2c(void) 190 { 191 puts("I2C: "); 192 #ifdef CONFIG_SYS_I2C 193 i2c_init_all(); 194 #else 195 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 196 #endif 197 puts("ready\n"); 198 return 0; 199 } 200 #endif 201 202 #if defined(CONFIG_VID) 203 __weak int init_func_vid(void) 204 { 205 return 0; 206 } 207 #endif 208 209 #if defined(CONFIG_HARD_SPI) 210 static int init_func_spi(void) 211 { 212 puts("SPI: "); 213 spi_init(); 214 puts("ready\n"); 215 return 0; 216 } 217 #endif 218 219 static int setup_mon_len(void) 220 { 221 #if defined(__ARM__) || defined(__MICROBLAZE__) 222 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 223 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 224 gd->mon_len = (ulong)&_end - (ulong)_init; 225 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 226 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 227 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 228 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 229 #elif defined(CONFIG_SYS_MONITOR_BASE) 230 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 231 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 232 #endif 233 return 0; 234 } 235 236 __weak int arch_cpu_init(void) 237 { 238 return 0; 239 } 240 241 __weak int mach_cpu_init(void) 242 { 243 return 0; 244 } 245 246 /* Get the top of usable RAM */ 247 __weak ulong board_get_usable_ram_top(ulong total_size) 248 { 249 #ifdef CONFIG_SYS_SDRAM_BASE 250 /* 251 * Detect whether we have so much RAM that it goes past the end of our 252 * 32-bit address space. If so, clip the usable RAM so it doesn't. 253 */ 254 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 255 /* 256 * Will wrap back to top of 32-bit space when reservations 257 * are made. 258 */ 259 return 0; 260 #endif 261 return gd->ram_top; 262 } 263 264 static int setup_dest_addr(void) 265 { 266 debug("Monitor len: %08lX\n", gd->mon_len); 267 /* 268 * Ram is setup, size stored in gd !! 269 */ 270 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 271 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 272 /* 273 * Subtract specified amount of memory to hide so that it won't 274 * get "touched" at all by U-Boot. By fixing up gd->ram_size 275 * the Linux kernel should now get passed the now "corrected" 276 * memory size and won't touch it either. This should work 277 * for arch/ppc and arch/powerpc. Only Linux board ports in 278 * arch/powerpc with bootwrapper support, that recalculate the 279 * memory size from the SDRAM controller setup will have to 280 * get fixed. 281 */ 282 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 283 #endif 284 #ifdef CONFIG_SYS_SDRAM_BASE 285 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 286 #endif 287 gd->ram_top += get_effective_memsize(); 288 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 289 gd->relocaddr = gd->ram_top; 290 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 291 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 292 /* 293 * We need to make sure the location we intend to put secondary core 294 * boot code is reserved and not used by any part of u-boot 295 */ 296 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 297 gd->relocaddr = determine_mp_bootpg(NULL); 298 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 299 } 300 #endif 301 return 0; 302 } 303 304 #ifdef CONFIG_PRAM 305 /* reserve protected RAM */ 306 static int reserve_pram(void) 307 { 308 ulong reg; 309 310 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 311 gd->relocaddr -= (reg << 10); /* size is in kB */ 312 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 313 gd->relocaddr); 314 return 0; 315 } 316 #endif /* CONFIG_PRAM */ 317 318 /* Round memory pointer down to next 4 kB limit */ 319 static int reserve_round_4k(void) 320 { 321 gd->relocaddr &= ~(4096 - 1); 322 return 0; 323 } 324 325 #ifdef CONFIG_ARM 326 __weak int reserve_mmu(void) 327 { 328 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 329 /* reserve TLB table */ 330 gd->arch.tlb_size = PGTABLE_SIZE; 331 gd->relocaddr -= gd->arch.tlb_size; 332 333 /* round down to next 64 kB limit */ 334 gd->relocaddr &= ~(0x10000 - 1); 335 336 gd->arch.tlb_addr = gd->relocaddr; 337 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 338 gd->arch.tlb_addr + gd->arch.tlb_size); 339 340 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 341 /* 342 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 343 * with location within secure ram. 344 */ 345 gd->arch.tlb_allocated = gd->arch.tlb_addr; 346 #endif 347 #endif 348 349 return 0; 350 } 351 #endif 352 353 static int reserve_video(void) 354 { 355 #ifdef CONFIG_DM_VIDEO 356 ulong addr; 357 int ret; 358 359 addr = gd->relocaddr; 360 ret = video_reserve(&addr); 361 if (ret) 362 return ret; 363 gd->relocaddr = addr; 364 #elif defined(CONFIG_LCD) 365 # ifdef CONFIG_FB_ADDR 366 gd->fb_base = CONFIG_FB_ADDR; 367 # else 368 /* reserve memory for LCD display (always full pages) */ 369 gd->relocaddr = lcd_setmem(gd->relocaddr); 370 gd->fb_base = gd->relocaddr; 371 # endif /* CONFIG_FB_ADDR */ 372 #elif defined(CONFIG_VIDEO) && \ 373 (!defined(CONFIG_PPC)) && \ 374 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 375 !defined(CONFIG_M68K) 376 /* reserve memory for video display (always full pages) */ 377 gd->relocaddr = video_setmem(gd->relocaddr); 378 gd->fb_base = gd->relocaddr; 379 #endif 380 381 return 0; 382 } 383 384 static int reserve_trace(void) 385 { 386 #ifdef CONFIG_TRACE 387 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 388 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 389 debug("Reserving %dk for trace data at: %08lx\n", 390 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 391 #endif 392 393 return 0; 394 } 395 396 static int reserve_uboot(void) 397 { 398 /* 399 * reserve memory for U-Boot code, data & bss 400 * round down to next 4 kB limit 401 */ 402 gd->relocaddr -= gd->mon_len; 403 gd->relocaddr &= ~(4096 - 1); 404 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 405 /* round down to next 64 kB limit so that IVPR stays aligned */ 406 gd->relocaddr &= ~(65536 - 1); 407 #endif 408 409 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 410 gd->relocaddr); 411 412 gd->start_addr_sp = gd->relocaddr; 413 414 return 0; 415 } 416 417 /* reserve memory for malloc() area */ 418 static int reserve_malloc(void) 419 { 420 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 421 debug("Reserving %dk for malloc() at: %08lx\n", 422 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 423 return 0; 424 } 425 426 /* (permanently) allocate a Board Info struct */ 427 static int reserve_board(void) 428 { 429 if (!gd->bd) { 430 gd->start_addr_sp -= sizeof(bd_t); 431 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 432 memset(gd->bd, '\0', sizeof(bd_t)); 433 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 434 sizeof(bd_t), gd->start_addr_sp); 435 } 436 return 0; 437 } 438 439 static int setup_machine(void) 440 { 441 #ifdef CONFIG_MACH_TYPE 442 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 443 #endif 444 return 0; 445 } 446 447 static int reserve_global_data(void) 448 { 449 gd->start_addr_sp -= sizeof(gd_t); 450 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 451 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 452 sizeof(gd_t), gd->start_addr_sp); 453 return 0; 454 } 455 456 static int reserve_fdt(void) 457 { 458 #ifndef CONFIG_OF_EMBED 459 /* 460 * If the device tree is sitting immediately above our image then we 461 * must relocate it. If it is embedded in the data section, then it 462 * will be relocated with other data. 463 */ 464 if (gd->fdt_blob) { 465 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 466 467 gd->start_addr_sp -= gd->fdt_size; 468 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 469 debug("Reserving %lu Bytes for FDT at: %08lx\n", 470 gd->fdt_size, gd->start_addr_sp); 471 } 472 #endif 473 474 return 0; 475 } 476 477 static int reserve_bootstage(void) 478 { 479 #ifdef CONFIG_BOOTSTAGE 480 int size = bootstage_get_size(); 481 482 gd->start_addr_sp -= size; 483 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 484 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 485 gd->start_addr_sp); 486 #endif 487 488 return 0; 489 } 490 491 __weak int arch_reserve_stacks(void) 492 { 493 return 0; 494 } 495 496 static int reserve_stacks(void) 497 { 498 /* make stack pointer 16-byte aligned */ 499 gd->start_addr_sp -= 16; 500 gd->start_addr_sp &= ~0xf; 501 502 /* 503 * let the architecture-specific code tailor gd->start_addr_sp and 504 * gd->irq_sp 505 */ 506 return arch_reserve_stacks(); 507 } 508 509 static int display_new_sp(void) 510 { 511 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 512 513 return 0; 514 } 515 516 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 517 defined(CONFIG_SH) 518 static int setup_board_part1(void) 519 { 520 bd_t *bd = gd->bd; 521 522 /* 523 * Save local variables to board info struct 524 */ 525 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 526 bd->bi_memsize = gd->ram_size; /* size in bytes */ 527 528 #ifdef CONFIG_SYS_SRAM_BASE 529 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 530 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 531 #endif 532 533 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 534 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 535 #endif 536 #if defined(CONFIG_M68K) 537 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 538 #endif 539 #if defined(CONFIG_MPC83xx) 540 bd->bi_immrbar = CONFIG_SYS_IMMR; 541 #endif 542 543 return 0; 544 } 545 #endif 546 547 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 548 static int setup_board_part2(void) 549 { 550 bd_t *bd = gd->bd; 551 552 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 553 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 554 #if defined(CONFIG_CPM2) 555 bd->bi_cpmfreq = gd->arch.cpm_clk; 556 bd->bi_brgfreq = gd->arch.brg_clk; 557 bd->bi_sccfreq = gd->arch.scc_clk; 558 bd->bi_vco = gd->arch.vco_out; 559 #endif /* CONFIG_CPM2 */ 560 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 561 bd->bi_pcifreq = gd->pci_clk; 562 #endif 563 #if defined(CONFIG_EXTRA_CLOCK) 564 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 565 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 566 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 567 #endif 568 569 return 0; 570 } 571 #endif 572 573 #ifdef CONFIG_POST 574 static int init_post(void) 575 { 576 post_bootmode_init(); 577 post_run(NULL, POST_ROM | post_bootmode_get(0)); 578 579 return 0; 580 } 581 #endif 582 583 static int reloc_fdt(void) 584 { 585 #ifndef CONFIG_OF_EMBED 586 if (gd->flags & GD_FLG_SKIP_RELOC) 587 return 0; 588 if (gd->new_fdt) { 589 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 590 gd->fdt_blob = gd->new_fdt; 591 } 592 #endif 593 594 return 0; 595 } 596 597 static int reloc_bootstage(void) 598 { 599 #ifdef CONFIG_BOOTSTAGE 600 if (gd->flags & GD_FLG_SKIP_RELOC) 601 return 0; 602 if (gd->new_bootstage) { 603 int size = bootstage_get_size(); 604 605 debug("Copying bootstage from %p to %p, size %x\n", 606 gd->bootstage, gd->new_bootstage, size); 607 memcpy(gd->new_bootstage, gd->bootstage, size); 608 gd->bootstage = gd->new_bootstage; 609 } 610 #endif 611 612 return 0; 613 } 614 615 static int setup_reloc(void) 616 { 617 if (gd->flags & GD_FLG_SKIP_RELOC) { 618 debug("Skipping relocation due to flag\n"); 619 return 0; 620 } 621 622 #ifdef CONFIG_SYS_TEXT_BASE 623 #ifdef ARM 624 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 625 #elif defined(CONFIG_M68K) 626 /* 627 * On all ColdFire arch cpu, monitor code starts always 628 * just after the default vector table location, so at 0x400 629 */ 630 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 631 #else 632 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 633 #endif 634 #endif 635 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 636 637 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 638 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 639 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 640 gd->start_addr_sp); 641 642 return 0; 643 } 644 645 #ifdef CONFIG_OF_BOARD_FIXUP 646 static int fix_fdt(void) 647 { 648 return board_fix_fdt((void *)gd->fdt_blob); 649 } 650 #endif 651 652 /* ARM calls relocate_code from its crt0.S */ 653 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 654 !CONFIG_IS_ENABLED(X86_64) 655 656 static int jump_to_copy(void) 657 { 658 if (gd->flags & GD_FLG_SKIP_RELOC) 659 return 0; 660 /* 661 * x86 is special, but in a nice way. It uses a trampoline which 662 * enables the dcache if possible. 663 * 664 * For now, other archs use relocate_code(), which is implemented 665 * similarly for all archs. When we do generic relocation, hopefully 666 * we can make all archs enable the dcache prior to relocation. 667 */ 668 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 669 /* 670 * SDRAM and console are now initialised. The final stack can now 671 * be setup in SDRAM. Code execution will continue in Flash, but 672 * with the stack in SDRAM and Global Data in temporary memory 673 * (CPU cache) 674 */ 675 arch_setup_gd(gd->new_gd); 676 board_init_f_r_trampoline(gd->start_addr_sp); 677 #else 678 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 679 #endif 680 681 return 0; 682 } 683 #endif 684 685 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 686 static int initf_bootstage(void) 687 { 688 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 689 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 690 int ret; 691 692 ret = bootstage_init(!from_spl); 693 if (ret) 694 return ret; 695 if (from_spl) { 696 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 697 CONFIG_BOOTSTAGE_STASH_SIZE); 698 699 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 700 if (ret && ret != -ENOENT) { 701 debug("Failed to unstash bootstage: err=%d\n", ret); 702 return ret; 703 } 704 } 705 706 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 707 708 return 0; 709 } 710 711 static int initf_console_record(void) 712 { 713 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 714 return console_record_init(); 715 #else 716 return 0; 717 #endif 718 } 719 720 static int initf_dm(void) 721 { 722 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 723 int ret; 724 725 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 726 ret = dm_init_and_scan(true); 727 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 728 if (ret) 729 return ret; 730 #endif 731 #ifdef CONFIG_TIMER_EARLY 732 ret = dm_timer_init(); 733 if (ret) 734 return ret; 735 #endif 736 737 return 0; 738 } 739 740 /* Architecture-specific memory reservation */ 741 __weak int reserve_arch(void) 742 { 743 return 0; 744 } 745 746 __weak int arch_cpu_init_dm(void) 747 { 748 return 0; 749 } 750 751 static const init_fnc_t init_sequence_f[] = { 752 setup_mon_len, 753 #ifdef CONFIG_OF_CONTROL 754 fdtdec_setup, 755 #endif 756 #ifdef CONFIG_TRACE 757 trace_early_init, 758 #endif 759 initf_malloc, 760 log_init, 761 initf_bootstage, /* uses its own timer, so does not need DM */ 762 initf_console_record, 763 #if defined(CONFIG_HAVE_FSP) 764 arch_fsp_init, 765 #endif 766 arch_cpu_init, /* basic arch cpu dependent setup */ 767 mach_cpu_init, /* SoC/machine dependent CPU setup */ 768 initf_dm, 769 arch_cpu_init_dm, 770 #if defined(CONFIG_BOARD_EARLY_INIT_F) 771 board_early_init_f, 772 #endif 773 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 774 /* get CPU and bus clocks according to the environment variable */ 775 get_clocks, /* get CPU and bus clocks (etc.) */ 776 #endif 777 #if !defined(CONFIG_M68K) 778 timer_init, /* initialize timer */ 779 #endif 780 #if defined(CONFIG_BOARD_POSTCLK_INIT) 781 board_postclk_init, 782 #endif 783 env_init, /* initialize environment */ 784 init_baud_rate, /* initialze baudrate settings */ 785 serial_init, /* serial communications setup */ 786 console_init_f, /* stage 1 init of console */ 787 display_options, /* say that we are here */ 788 display_text_info, /* show debugging info if required */ 789 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 790 checkcpu, 791 #endif 792 #if defined(CONFIG_DISPLAY_CPUINFO) 793 print_cpuinfo, /* display cpu info (and speed) */ 794 #endif 795 #if defined(CONFIG_DTB_RESELECT) 796 embedded_dtb_select, 797 #endif 798 #if defined(CONFIG_DISPLAY_BOARDINFO) 799 show_board_info, 800 #endif 801 INIT_FUNC_WATCHDOG_INIT 802 #if defined(CONFIG_MISC_INIT_F) 803 misc_init_f, 804 #endif 805 INIT_FUNC_WATCHDOG_RESET 806 #if defined(CONFIG_SYS_I2C) 807 init_func_i2c, 808 #endif 809 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 810 init_func_vid, 811 #endif 812 #if defined(CONFIG_HARD_SPI) 813 init_func_spi, 814 #endif 815 announce_dram_init, 816 dram_init, /* configure available RAM banks */ 817 #ifdef CONFIG_POST 818 post_init_f, 819 #endif 820 INIT_FUNC_WATCHDOG_RESET 821 #if defined(CONFIG_SYS_DRAM_TEST) 822 testdram, 823 #endif /* CONFIG_SYS_DRAM_TEST */ 824 INIT_FUNC_WATCHDOG_RESET 825 826 #ifdef CONFIG_POST 827 init_post, 828 #endif 829 INIT_FUNC_WATCHDOG_RESET 830 /* 831 * Now that we have DRAM mapped and working, we can 832 * relocate the code and continue running from DRAM. 833 * 834 * Reserve memory at end of RAM for (top down in that order): 835 * - area that won't get touched by U-Boot and Linux (optional) 836 * - kernel log buffer 837 * - protected RAM 838 * - LCD framebuffer 839 * - monitor code 840 * - board info struct 841 */ 842 setup_dest_addr, 843 #ifdef CONFIG_PRAM 844 reserve_pram, 845 #endif 846 reserve_round_4k, 847 #ifdef CONFIG_ARM 848 reserve_mmu, 849 #endif 850 reserve_video, 851 reserve_trace, 852 reserve_uboot, 853 reserve_malloc, 854 reserve_board, 855 setup_machine, 856 reserve_global_data, 857 reserve_fdt, 858 reserve_bootstage, 859 reserve_arch, 860 reserve_stacks, 861 dram_init_banksize, 862 show_dram_config, 863 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 864 defined(CONFIG_SH) 865 setup_board_part1, 866 #endif 867 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 868 INIT_FUNC_WATCHDOG_RESET 869 setup_board_part2, 870 #endif 871 display_new_sp, 872 #ifdef CONFIG_OF_BOARD_FIXUP 873 fix_fdt, 874 #endif 875 INIT_FUNC_WATCHDOG_RESET 876 reloc_fdt, 877 reloc_bootstage, 878 setup_reloc, 879 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 880 copy_uboot_to_ram, 881 do_elf_reloc_fixups, 882 clear_bss, 883 #endif 884 #if defined(CONFIG_XTENSA) 885 clear_bss, 886 #endif 887 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 888 !CONFIG_IS_ENABLED(X86_64) 889 jump_to_copy, 890 #endif 891 NULL, 892 }; 893 894 void board_init_f(ulong boot_flags) 895 { 896 gd->flags = boot_flags; 897 gd->have_console = 0; 898 899 if (initcall_run_list(init_sequence_f)) 900 hang(); 901 902 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 903 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 904 /* NOTREACHED - jump_to_copy() does not return */ 905 hang(); 906 #endif 907 } 908 909 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 910 /* 911 * For now this code is only used on x86. 912 * 913 * init_sequence_f_r is the list of init functions which are run when 914 * U-Boot is executing from Flash with a semi-limited 'C' environment. 915 * The following limitations must be considered when implementing an 916 * '_f_r' function: 917 * - 'static' variables are read-only 918 * - Global Data (gd->xxx) is read/write 919 * 920 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 921 * supported). It _should_, if possible, copy global data to RAM and 922 * initialise the CPU caches (to speed up the relocation process) 923 * 924 * NOTE: At present only x86 uses this route, but it is intended that 925 * all archs will move to this when generic relocation is implemented. 926 */ 927 static const init_fnc_t init_sequence_f_r[] = { 928 #if !CONFIG_IS_ENABLED(X86_64) 929 init_cache_f_r, 930 #endif 931 932 NULL, 933 }; 934 935 void board_init_f_r(void) 936 { 937 if (initcall_run_list(init_sequence_f_r)) 938 hang(); 939 940 /* 941 * The pre-relocation drivers may be using memory that has now gone 942 * away. Mark serial as unavailable - this will fall back to the debug 943 * UART if available. 944 * 945 * Do the same with log drivers since the memory may not be available. 946 */ 947 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 948 #ifdef CONFIG_TIMER 949 gd->timer = NULL; 950 #endif 951 952 /* 953 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 954 * Transfer execution from Flash to RAM by calculating the address 955 * of the in-RAM copy of board_init_r() and calling it 956 */ 957 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 958 959 /* NOTREACHED - board_init_r() does not return */ 960 hang(); 961 } 962 #endif /* CONFIG_X86 */ 963