1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2002-2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2002 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 9 * Marius Groeger <mgroeger@sysgo.de> 10 */ 11 12 #include <common.h> 13 #include <console.h> 14 #include <cpu.h> 15 #include <dm.h> 16 #include <environment.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <malloc.h> 22 #include <mapmem.h> 23 #include <os.h> 24 #include <post.h> 25 #include <relocate.h> 26 #include <status_led.h> 27 #include <sysreset.h> 28 #include <timer.h> 29 #include <trace.h> 30 #include <video.h> 31 #include <watchdog.h> 32 #ifdef CONFIG_MACH_TYPE 33 #include <asm/mach-types.h> 34 #endif 35 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 36 #include <asm/mp.h> 37 #endif 38 #include <asm/io.h> 39 #include <asm/sections.h> 40 #include <dm/root.h> 41 #include <linux/errno.h> 42 43 /* 44 * Pointer to initial global data area 45 * 46 * Here we initialize it if needed. 47 */ 48 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 49 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 50 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 51 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 52 #else 53 DECLARE_GLOBAL_DATA_PTR; 54 #endif 55 56 /* 57 * TODO(sjg@chromium.org): IMO this code should be 58 * refactored to a single function, something like: 59 * 60 * void led_set_state(enum led_colour_t colour, int on); 61 */ 62 /************************************************************************ 63 * Coloured LED functionality 64 ************************************************************************ 65 * May be supplied by boards if desired 66 */ 67 __weak void coloured_LED_init(void) {} 68 __weak void red_led_on(void) {} 69 __weak void red_led_off(void) {} 70 __weak void green_led_on(void) {} 71 __weak void green_led_off(void) {} 72 __weak void yellow_led_on(void) {} 73 __weak void yellow_led_off(void) {} 74 __weak void blue_led_on(void) {} 75 __weak void blue_led_off(void) {} 76 77 /* 78 * Why is gd allocated a register? Prior to reloc it might be better to 79 * just pass it around to each function in this file? 80 * 81 * After reloc one could argue that it is hardly used and doesn't need 82 * to be in a register. Or if it is it should perhaps hold pointers to all 83 * global data for all modules, so that post-reloc we can avoid the massive 84 * literal pool we get on ARM. Or perhaps just encourage each module to use 85 * a structure... 86 */ 87 88 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 89 static int init_func_watchdog_init(void) 90 { 91 # if defined(CONFIG_HW_WATCHDOG) && \ 92 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 93 defined(CONFIG_SH) || \ 94 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 95 defined(CONFIG_IMX_WATCHDOG)) 96 hw_watchdog_init(); 97 puts(" Watchdog enabled\n"); 98 # endif 99 WATCHDOG_RESET(); 100 101 return 0; 102 } 103 104 int init_func_watchdog_reset(void) 105 { 106 WATCHDOG_RESET(); 107 108 return 0; 109 } 110 #endif /* CONFIG_WATCHDOG */ 111 112 __weak void board_add_ram_info(int use_default) 113 { 114 /* please define platform specific board_add_ram_info() */ 115 } 116 117 static int init_baud_rate(void) 118 { 119 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 120 return 0; 121 } 122 123 static int display_text_info(void) 124 { 125 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 126 ulong bss_start, bss_end, text_base; 127 128 bss_start = (ulong)&__bss_start; 129 bss_end = (ulong)&__bss_end; 130 131 #ifdef CONFIG_SYS_TEXT_BASE 132 text_base = CONFIG_SYS_TEXT_BASE; 133 #else 134 text_base = CONFIG_SYS_MONITOR_BASE; 135 #endif 136 137 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 138 text_base, bss_start, bss_end); 139 #endif 140 141 return 0; 142 } 143 144 #ifdef CONFIG_SYSRESET 145 static int print_resetinfo(void) 146 { 147 struct udevice *dev; 148 char status[256]; 149 int ret; 150 151 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); 152 if (ret) { 153 debug("%s: No sysreset device found (error: %d)\n", 154 __func__, ret); 155 /* Not all boards have sysreset drivers available during early 156 * boot, so don't fail if one can't be found. 157 */ 158 return 0; 159 } 160 161 if (!sysreset_get_status(dev, status, sizeof(status))) 162 printf("%s", status); 163 164 return 0; 165 } 166 #endif 167 168 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) 169 static int print_cpuinfo(void) 170 { 171 struct udevice *dev; 172 char desc[512]; 173 int ret; 174 175 ret = uclass_first_device_err(UCLASS_CPU, &dev); 176 if (ret) { 177 debug("%s: Could not get CPU device (err = %d)\n", 178 __func__, ret); 179 return ret; 180 } 181 182 ret = cpu_get_desc(dev, desc, sizeof(desc)); 183 if (ret) { 184 debug("%s: Could not get CPU description (err = %d)\n", 185 dev->name, ret); 186 return ret; 187 } 188 189 printf("CPU: %s\n", desc); 190 191 return 0; 192 } 193 #endif 194 195 static int announce_dram_init(void) 196 { 197 puts("DRAM: "); 198 return 0; 199 } 200 201 static int show_dram_config(void) 202 { 203 unsigned long long size; 204 205 #ifdef CONFIG_NR_DRAM_BANKS 206 int i; 207 208 debug("\nRAM Configuration:\n"); 209 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 210 size += gd->bd->bi_dram[i].size; 211 debug("Bank #%d: %llx ", i, 212 (unsigned long long)(gd->bd->bi_dram[i].start)); 213 #ifdef DEBUG 214 print_size(gd->bd->bi_dram[i].size, "\n"); 215 #endif 216 } 217 debug("\nDRAM: "); 218 #else 219 size = gd->ram_size; 220 #endif 221 222 print_size(size, ""); 223 board_add_ram_info(0); 224 putc('\n'); 225 226 return 0; 227 } 228 229 __weak int dram_init_banksize(void) 230 { 231 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 232 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 233 gd->bd->bi_dram[0].size = get_effective_memsize(); 234 #endif 235 236 return 0; 237 } 238 239 #if defined(CONFIG_SYS_I2C) 240 static int init_func_i2c(void) 241 { 242 puts("I2C: "); 243 #ifdef CONFIG_SYS_I2C 244 i2c_init_all(); 245 #else 246 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 247 #endif 248 puts("ready\n"); 249 return 0; 250 } 251 #endif 252 253 #if defined(CONFIG_VID) 254 __weak int init_func_vid(void) 255 { 256 return 0; 257 } 258 #endif 259 260 static int setup_mon_len(void) 261 { 262 #if defined(__ARM__) || defined(__MICROBLAZE__) 263 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 264 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 265 gd->mon_len = (ulong)&_end - (ulong)_init; 266 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 267 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 268 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 269 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 270 #elif defined(CONFIG_SYS_MONITOR_BASE) 271 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 272 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 273 #endif 274 return 0; 275 } 276 277 __weak int arch_cpu_init(void) 278 { 279 return 0; 280 } 281 282 __weak int mach_cpu_init(void) 283 { 284 return 0; 285 } 286 287 /* Get the top of usable RAM */ 288 __weak ulong board_get_usable_ram_top(ulong total_size) 289 { 290 #ifdef CONFIG_SYS_SDRAM_BASE 291 /* 292 * Detect whether we have so much RAM that it goes past the end of our 293 * 32-bit address space. If so, clip the usable RAM so it doesn't. 294 */ 295 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 296 /* 297 * Will wrap back to top of 32-bit space when reservations 298 * are made. 299 */ 300 return 0; 301 #endif 302 return gd->ram_top; 303 } 304 305 static int setup_dest_addr(void) 306 { 307 debug("Monitor len: %08lX\n", gd->mon_len); 308 /* 309 * Ram is setup, size stored in gd !! 310 */ 311 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 312 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 313 /* 314 * Subtract specified amount of memory to hide so that it won't 315 * get "touched" at all by U-Boot. By fixing up gd->ram_size 316 * the Linux kernel should now get passed the now "corrected" 317 * memory size and won't touch it either. This should work 318 * for arch/ppc and arch/powerpc. Only Linux board ports in 319 * arch/powerpc with bootwrapper support, that recalculate the 320 * memory size from the SDRAM controller setup will have to 321 * get fixed. 322 */ 323 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 324 #endif 325 #ifdef CONFIG_SYS_SDRAM_BASE 326 gd->ram_base = CONFIG_SYS_SDRAM_BASE; 327 #endif 328 gd->ram_top = gd->ram_base + get_effective_memsize(); 329 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 330 gd->relocaddr = gd->ram_top; 331 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 332 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 333 /* 334 * We need to make sure the location we intend to put secondary core 335 * boot code is reserved and not used by any part of u-boot 336 */ 337 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 338 gd->relocaddr = determine_mp_bootpg(NULL); 339 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 340 } 341 #endif 342 return 0; 343 } 344 345 #ifdef CONFIG_PRAM 346 /* reserve protected RAM */ 347 static int reserve_pram(void) 348 { 349 ulong reg; 350 351 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 352 gd->relocaddr -= (reg << 10); /* size is in kB */ 353 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 354 gd->relocaddr); 355 return 0; 356 } 357 #endif /* CONFIG_PRAM */ 358 359 /* Round memory pointer down to next 4 kB limit */ 360 static int reserve_round_4k(void) 361 { 362 gd->relocaddr &= ~(4096 - 1); 363 return 0; 364 } 365 366 #ifdef CONFIG_ARM 367 __weak int reserve_mmu(void) 368 { 369 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 370 /* reserve TLB table */ 371 gd->arch.tlb_size = PGTABLE_SIZE; 372 gd->relocaddr -= gd->arch.tlb_size; 373 374 /* round down to next 64 kB limit */ 375 gd->relocaddr &= ~(0x10000 - 1); 376 377 gd->arch.tlb_addr = gd->relocaddr; 378 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 379 gd->arch.tlb_addr + gd->arch.tlb_size); 380 381 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 382 /* 383 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 384 * with location within secure ram. 385 */ 386 gd->arch.tlb_allocated = gd->arch.tlb_addr; 387 #endif 388 #endif 389 390 return 0; 391 } 392 #endif 393 394 static int reserve_video(void) 395 { 396 #ifdef CONFIG_DM_VIDEO 397 ulong addr; 398 int ret; 399 400 addr = gd->relocaddr; 401 ret = video_reserve(&addr); 402 if (ret) 403 return ret; 404 gd->relocaddr = addr; 405 #elif defined(CONFIG_LCD) 406 # ifdef CONFIG_FB_ADDR 407 gd->fb_base = CONFIG_FB_ADDR; 408 # else 409 /* reserve memory for LCD display (always full pages) */ 410 gd->relocaddr = lcd_setmem(gd->relocaddr); 411 gd->fb_base = gd->relocaddr; 412 # endif /* CONFIG_FB_ADDR */ 413 #elif defined(CONFIG_VIDEO) && \ 414 (!defined(CONFIG_PPC)) && \ 415 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 416 !defined(CONFIG_M68K) 417 /* reserve memory for video display (always full pages) */ 418 gd->relocaddr = video_setmem(gd->relocaddr); 419 gd->fb_base = gd->relocaddr; 420 #endif 421 422 return 0; 423 } 424 425 static int reserve_trace(void) 426 { 427 #ifdef CONFIG_TRACE 428 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 429 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 430 debug("Reserving %dk for trace data at: %08lx\n", 431 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 432 #endif 433 434 return 0; 435 } 436 437 static int reserve_uboot(void) 438 { 439 if (!(gd->flags & GD_FLG_SKIP_RELOC)) { 440 /* 441 * reserve memory for U-Boot code, data & bss 442 * round down to next 4 kB limit 443 */ 444 gd->relocaddr -= gd->mon_len; 445 gd->relocaddr &= ~(4096 - 1); 446 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 447 /* round down to next 64 kB limit so that IVPR stays aligned */ 448 gd->relocaddr &= ~(65536 - 1); 449 #endif 450 451 debug("Reserving %ldk for U-Boot at: %08lx\n", 452 gd->mon_len >> 10, gd->relocaddr); 453 } 454 455 gd->start_addr_sp = gd->relocaddr; 456 457 return 0; 458 } 459 460 /* reserve memory for malloc() area */ 461 static int reserve_malloc(void) 462 { 463 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 464 debug("Reserving %dk for malloc() at: %08lx\n", 465 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 466 return 0; 467 } 468 469 /* (permanently) allocate a Board Info struct */ 470 static int reserve_board(void) 471 { 472 if (!gd->bd) { 473 gd->start_addr_sp -= sizeof(bd_t); 474 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 475 memset(gd->bd, '\0', sizeof(bd_t)); 476 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 477 sizeof(bd_t), gd->start_addr_sp); 478 } 479 return 0; 480 } 481 482 static int setup_machine(void) 483 { 484 #ifdef CONFIG_MACH_TYPE 485 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 486 #endif 487 return 0; 488 } 489 490 static int reserve_global_data(void) 491 { 492 gd->start_addr_sp -= sizeof(gd_t); 493 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 494 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 495 sizeof(gd_t), gd->start_addr_sp); 496 return 0; 497 } 498 499 static int reserve_fdt(void) 500 { 501 #ifndef CONFIG_OF_EMBED 502 /* 503 * If the device tree is sitting immediately above our image then we 504 * must relocate it. If it is embedded in the data section, then it 505 * will be relocated with other data. 506 */ 507 if (gd->fdt_blob) { 508 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 509 510 gd->start_addr_sp -= gd->fdt_size; 511 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 512 debug("Reserving %lu Bytes for FDT at: %08lx\n", 513 gd->fdt_size, gd->start_addr_sp); 514 } 515 #endif 516 517 return 0; 518 } 519 520 static int reserve_bootstage(void) 521 { 522 #ifdef CONFIG_BOOTSTAGE 523 int size = bootstage_get_size(); 524 525 gd->start_addr_sp -= size; 526 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 527 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 528 gd->start_addr_sp); 529 #endif 530 531 return 0; 532 } 533 534 __weak int arch_reserve_stacks(void) 535 { 536 return 0; 537 } 538 539 static int reserve_stacks(void) 540 { 541 /* make stack pointer 16-byte aligned */ 542 gd->start_addr_sp -= 16; 543 gd->start_addr_sp &= ~0xf; 544 545 /* 546 * let the architecture-specific code tailor gd->start_addr_sp and 547 * gd->irq_sp 548 */ 549 return arch_reserve_stacks(); 550 } 551 552 static int display_new_sp(void) 553 { 554 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 555 556 return 0; 557 } 558 559 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 560 defined(CONFIG_SH) 561 static int setup_board_part1(void) 562 { 563 bd_t *bd = gd->bd; 564 565 /* 566 * Save local variables to board info struct 567 */ 568 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 569 bd->bi_memsize = gd->ram_size; /* size in bytes */ 570 571 #ifdef CONFIG_SYS_SRAM_BASE 572 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 573 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 574 #endif 575 576 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 577 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 578 #endif 579 #if defined(CONFIG_M68K) 580 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 581 #endif 582 #if defined(CONFIG_MPC83xx) 583 bd->bi_immrbar = CONFIG_SYS_IMMR; 584 #endif 585 586 return 0; 587 } 588 #endif 589 590 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 591 static int setup_board_part2(void) 592 { 593 bd_t *bd = gd->bd; 594 595 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 596 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 597 #if defined(CONFIG_CPM2) 598 bd->bi_cpmfreq = gd->arch.cpm_clk; 599 bd->bi_brgfreq = gd->arch.brg_clk; 600 bd->bi_sccfreq = gd->arch.scc_clk; 601 bd->bi_vco = gd->arch.vco_out; 602 #endif /* CONFIG_CPM2 */ 603 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 604 bd->bi_pcifreq = gd->pci_clk; 605 #endif 606 #if defined(CONFIG_EXTRA_CLOCK) 607 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 608 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 609 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 610 #endif 611 612 return 0; 613 } 614 #endif 615 616 #ifdef CONFIG_POST 617 static int init_post(void) 618 { 619 post_bootmode_init(); 620 post_run(NULL, POST_ROM | post_bootmode_get(0)); 621 622 return 0; 623 } 624 #endif 625 626 static int reloc_fdt(void) 627 { 628 #ifndef CONFIG_OF_EMBED 629 if (gd->flags & GD_FLG_SKIP_RELOC) 630 return 0; 631 if (gd->new_fdt) { 632 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 633 gd->fdt_blob = gd->new_fdt; 634 } 635 #endif 636 637 return 0; 638 } 639 640 static int reloc_bootstage(void) 641 { 642 #ifdef CONFIG_BOOTSTAGE 643 if (gd->flags & GD_FLG_SKIP_RELOC) 644 return 0; 645 if (gd->new_bootstage) { 646 int size = bootstage_get_size(); 647 648 debug("Copying bootstage from %p to %p, size %x\n", 649 gd->bootstage, gd->new_bootstage, size); 650 memcpy(gd->new_bootstage, gd->bootstage, size); 651 gd->bootstage = gd->new_bootstage; 652 } 653 #endif 654 655 return 0; 656 } 657 658 static int setup_reloc(void) 659 { 660 if (gd->flags & GD_FLG_SKIP_RELOC) { 661 debug("Skipping relocation due to flag\n"); 662 return 0; 663 } 664 665 #ifdef CONFIG_SYS_TEXT_BASE 666 #ifdef ARM 667 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 668 #elif defined(CONFIG_M68K) 669 /* 670 * On all ColdFire arch cpu, monitor code starts always 671 * just after the default vector table location, so at 0x400 672 */ 673 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 674 #else 675 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 676 #endif 677 #endif 678 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 679 680 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 681 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 682 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 683 gd->start_addr_sp); 684 685 return 0; 686 } 687 688 #ifdef CONFIG_OF_BOARD_FIXUP 689 static int fix_fdt(void) 690 { 691 return board_fix_fdt((void *)gd->fdt_blob); 692 } 693 #endif 694 695 /* ARM calls relocate_code from its crt0.S */ 696 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 697 !CONFIG_IS_ENABLED(X86_64) 698 699 static int jump_to_copy(void) 700 { 701 if (gd->flags & GD_FLG_SKIP_RELOC) 702 return 0; 703 /* 704 * x86 is special, but in a nice way. It uses a trampoline which 705 * enables the dcache if possible. 706 * 707 * For now, other archs use relocate_code(), which is implemented 708 * similarly for all archs. When we do generic relocation, hopefully 709 * we can make all archs enable the dcache prior to relocation. 710 */ 711 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 712 /* 713 * SDRAM and console are now initialised. The final stack can now 714 * be setup in SDRAM. Code execution will continue in Flash, but 715 * with the stack in SDRAM and Global Data in temporary memory 716 * (CPU cache) 717 */ 718 arch_setup_gd(gd->new_gd); 719 board_init_f_r_trampoline(gd->start_addr_sp); 720 #else 721 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 722 #endif 723 724 return 0; 725 } 726 #endif 727 728 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 729 static int initf_bootstage(void) 730 { 731 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 732 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 733 int ret; 734 735 ret = bootstage_init(!from_spl); 736 if (ret) 737 return ret; 738 if (from_spl) { 739 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 740 CONFIG_BOOTSTAGE_STASH_SIZE); 741 742 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 743 if (ret && ret != -ENOENT) { 744 debug("Failed to unstash bootstage: err=%d\n", ret); 745 return ret; 746 } 747 } 748 749 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 750 751 return 0; 752 } 753 754 static int initf_console_record(void) 755 { 756 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 757 return console_record_init(); 758 #else 759 return 0; 760 #endif 761 } 762 763 static int initf_dm(void) 764 { 765 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 766 int ret; 767 768 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 769 ret = dm_init_and_scan(true); 770 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 771 if (ret) 772 return ret; 773 #endif 774 #ifdef CONFIG_TIMER_EARLY 775 ret = dm_timer_init(); 776 if (ret) 777 return ret; 778 #endif 779 780 return 0; 781 } 782 783 /* Architecture-specific memory reservation */ 784 __weak int reserve_arch(void) 785 { 786 return 0; 787 } 788 789 __weak int arch_cpu_init_dm(void) 790 { 791 return 0; 792 } 793 794 static const init_fnc_t init_sequence_f[] = { 795 setup_mon_len, 796 #ifdef CONFIG_OF_CONTROL 797 fdtdec_setup, 798 #endif 799 #ifdef CONFIG_TRACE 800 trace_early_init, 801 #endif 802 initf_malloc, 803 log_init, 804 initf_bootstage, /* uses its own timer, so does not need DM */ 805 initf_console_record, 806 #if defined(CONFIG_HAVE_FSP) 807 arch_fsp_init, 808 #endif 809 arch_cpu_init, /* basic arch cpu dependent setup */ 810 mach_cpu_init, /* SoC/machine dependent CPU setup */ 811 initf_dm, 812 arch_cpu_init_dm, 813 #if defined(CONFIG_BOARD_EARLY_INIT_F) 814 board_early_init_f, 815 #endif 816 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 817 /* get CPU and bus clocks according to the environment variable */ 818 get_clocks, /* get CPU and bus clocks (etc.) */ 819 #endif 820 #if !defined(CONFIG_M68K) 821 timer_init, /* initialize timer */ 822 #endif 823 #if defined(CONFIG_BOARD_POSTCLK_INIT) 824 board_postclk_init, 825 #endif 826 env_init, /* initialize environment */ 827 init_baud_rate, /* initialze baudrate settings */ 828 serial_init, /* serial communications setup */ 829 console_init_f, /* stage 1 init of console */ 830 display_options, /* say that we are here */ 831 display_text_info, /* show debugging info if required */ 832 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 833 checkcpu, 834 #endif 835 #if defined(CONFIG_SYSRESET) 836 print_resetinfo, 837 #endif 838 #if defined(CONFIG_DISPLAY_CPUINFO) 839 print_cpuinfo, /* display cpu info (and speed) */ 840 #endif 841 #if defined(CONFIG_DTB_RESELECT) 842 embedded_dtb_select, 843 #endif 844 #if defined(CONFIG_DISPLAY_BOARDINFO) 845 show_board_info, 846 #endif 847 INIT_FUNC_WATCHDOG_INIT 848 #if defined(CONFIG_MISC_INIT_F) 849 misc_init_f, 850 #endif 851 INIT_FUNC_WATCHDOG_RESET 852 #if defined(CONFIG_SYS_I2C) 853 init_func_i2c, 854 #endif 855 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 856 init_func_vid, 857 #endif 858 announce_dram_init, 859 dram_init, /* configure available RAM banks */ 860 #ifdef CONFIG_POST 861 post_init_f, 862 #endif 863 INIT_FUNC_WATCHDOG_RESET 864 #if defined(CONFIG_SYS_DRAM_TEST) 865 testdram, 866 #endif /* CONFIG_SYS_DRAM_TEST */ 867 INIT_FUNC_WATCHDOG_RESET 868 869 #ifdef CONFIG_POST 870 init_post, 871 #endif 872 INIT_FUNC_WATCHDOG_RESET 873 /* 874 * Now that we have DRAM mapped and working, we can 875 * relocate the code and continue running from DRAM. 876 * 877 * Reserve memory at end of RAM for (top down in that order): 878 * - area that won't get touched by U-Boot and Linux (optional) 879 * - kernel log buffer 880 * - protected RAM 881 * - LCD framebuffer 882 * - monitor code 883 * - board info struct 884 */ 885 setup_dest_addr, 886 #ifdef CONFIG_PRAM 887 reserve_pram, 888 #endif 889 reserve_round_4k, 890 #ifdef CONFIG_ARM 891 reserve_mmu, 892 #endif 893 reserve_video, 894 reserve_trace, 895 reserve_uboot, 896 reserve_malloc, 897 reserve_board, 898 setup_machine, 899 reserve_global_data, 900 reserve_fdt, 901 reserve_bootstage, 902 reserve_arch, 903 reserve_stacks, 904 dram_init_banksize, 905 show_dram_config, 906 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 907 defined(CONFIG_SH) 908 setup_board_part1, 909 #endif 910 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 911 INIT_FUNC_WATCHDOG_RESET 912 setup_board_part2, 913 #endif 914 display_new_sp, 915 #ifdef CONFIG_OF_BOARD_FIXUP 916 fix_fdt, 917 #endif 918 INIT_FUNC_WATCHDOG_RESET 919 reloc_fdt, 920 reloc_bootstage, 921 setup_reloc, 922 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 923 copy_uboot_to_ram, 924 do_elf_reloc_fixups, 925 clear_bss, 926 #endif 927 #if defined(CONFIG_XTENSA) 928 clear_bss, 929 #endif 930 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 931 !CONFIG_IS_ENABLED(X86_64) 932 jump_to_copy, 933 #endif 934 NULL, 935 }; 936 937 void board_init_f(ulong boot_flags) 938 { 939 gd->flags = boot_flags; 940 gd->have_console = 0; 941 942 if (initcall_run_list(init_sequence_f)) 943 hang(); 944 945 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 946 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ 947 !defined(CONFIG_ARC) 948 /* NOTREACHED - jump_to_copy() does not return */ 949 hang(); 950 #endif 951 } 952 953 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 954 /* 955 * For now this code is only used on x86. 956 * 957 * init_sequence_f_r is the list of init functions which are run when 958 * U-Boot is executing from Flash with a semi-limited 'C' environment. 959 * The following limitations must be considered when implementing an 960 * '_f_r' function: 961 * - 'static' variables are read-only 962 * - Global Data (gd->xxx) is read/write 963 * 964 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 965 * supported). It _should_, if possible, copy global data to RAM and 966 * initialise the CPU caches (to speed up the relocation process) 967 * 968 * NOTE: At present only x86 uses this route, but it is intended that 969 * all archs will move to this when generic relocation is implemented. 970 */ 971 static const init_fnc_t init_sequence_f_r[] = { 972 #if !CONFIG_IS_ENABLED(X86_64) 973 init_cache_f_r, 974 #endif 975 976 NULL, 977 }; 978 979 void board_init_f_r(void) 980 { 981 if (initcall_run_list(init_sequence_f_r)) 982 hang(); 983 984 /* 985 * The pre-relocation drivers may be using memory that has now gone 986 * away. Mark serial as unavailable - this will fall back to the debug 987 * UART if available. 988 * 989 * Do the same with log drivers since the memory may not be available. 990 */ 991 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 992 #ifdef CONFIG_TIMER 993 gd->timer = NULL; 994 #endif 995 996 /* 997 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 998 * Transfer execution from Flash to RAM by calculating the address 999 * of the in-RAM copy of board_init_r() and calling it 1000 */ 1001 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1002 1003 /* NOTREACHED - board_init_r() does not return */ 1004 hang(); 1005 } 1006 #endif /* CONFIG_X86 */ 1007