1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2002-2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2002 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 9 * Marius Groeger <mgroeger@sysgo.de> 10 */ 11 12 #include <common.h> 13 #include <console.h> 14 #include <cpu.h> 15 #include <dm.h> 16 #include <environment.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <malloc.h> 22 #include <mapmem.h> 23 #include <os.h> 24 #include <post.h> 25 #include <relocate.h> 26 #include <spi.h> 27 #include <status_led.h> 28 #include <sysreset.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 44 /* 45 * Pointer to initial global data area 46 * 47 * Here we initialize it if needed. 48 */ 49 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 50 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 51 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 52 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 53 #else 54 DECLARE_GLOBAL_DATA_PTR; 55 #endif 56 57 /* 58 * TODO(sjg@chromium.org): IMO this code should be 59 * refactored to a single function, something like: 60 * 61 * void led_set_state(enum led_colour_t colour, int on); 62 */ 63 /************************************************************************ 64 * Coloured LED functionality 65 ************************************************************************ 66 * May be supplied by boards if desired 67 */ 68 __weak void coloured_LED_init(void) {} 69 __weak void red_led_on(void) {} 70 __weak void red_led_off(void) {} 71 __weak void green_led_on(void) {} 72 __weak void green_led_off(void) {} 73 __weak void yellow_led_on(void) {} 74 __weak void yellow_led_off(void) {} 75 __weak void blue_led_on(void) {} 76 __weak void blue_led_off(void) {} 77 78 /* 79 * Why is gd allocated a register? Prior to reloc it might be better to 80 * just pass it around to each function in this file? 81 * 82 * After reloc one could argue that it is hardly used and doesn't need 83 * to be in a register. Or if it is it should perhaps hold pointers to all 84 * global data for all modules, so that post-reloc we can avoid the massive 85 * literal pool we get on ARM. Or perhaps just encourage each module to use 86 * a structure... 87 */ 88 89 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 90 static int init_func_watchdog_init(void) 91 { 92 # if defined(CONFIG_HW_WATCHDOG) && \ 93 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 94 defined(CONFIG_SH) || \ 95 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 96 defined(CONFIG_IMX_WATCHDOG)) 97 hw_watchdog_init(); 98 puts(" Watchdog enabled\n"); 99 # endif 100 WATCHDOG_RESET(); 101 102 return 0; 103 } 104 105 int init_func_watchdog_reset(void) 106 { 107 WATCHDOG_RESET(); 108 109 return 0; 110 } 111 #endif /* CONFIG_WATCHDOG */ 112 113 __weak void board_add_ram_info(int use_default) 114 { 115 /* please define platform specific board_add_ram_info() */ 116 } 117 118 static int init_baud_rate(void) 119 { 120 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 121 return 0; 122 } 123 124 static int display_text_info(void) 125 { 126 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 127 ulong bss_start, bss_end, text_base; 128 129 bss_start = (ulong)&__bss_start; 130 bss_end = (ulong)&__bss_end; 131 132 #ifdef CONFIG_SYS_TEXT_BASE 133 text_base = CONFIG_SYS_TEXT_BASE; 134 #else 135 text_base = CONFIG_SYS_MONITOR_BASE; 136 #endif 137 138 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 139 text_base, bss_start, bss_end); 140 #endif 141 142 return 0; 143 } 144 145 #ifdef CONFIG_SYSRESET 146 static int print_resetinfo(void) 147 { 148 struct udevice *dev; 149 char status[256]; 150 int ret; 151 152 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); 153 if (ret) { 154 debug("%s: No sysreset device found (error: %d)\n", 155 __func__, ret); 156 /* Not all boards have sysreset drivers available during early 157 * boot, so don't fail if one can't be found. 158 */ 159 return 0; 160 } 161 162 if (!sysreset_get_status(dev, status, sizeof(status))) 163 printf("%s", status); 164 165 return 0; 166 } 167 #endif 168 169 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) 170 static int print_cpuinfo(void) 171 { 172 struct udevice *dev; 173 char desc[512]; 174 int ret; 175 176 ret = uclass_first_device_err(UCLASS_CPU, &dev); 177 if (ret) { 178 debug("%s: Could not get CPU device (err = %d)\n", 179 __func__, ret); 180 return ret; 181 } 182 183 ret = cpu_get_desc(dev, desc, sizeof(desc)); 184 if (ret) { 185 debug("%s: Could not get CPU description (err = %d)\n", 186 dev->name, ret); 187 return ret; 188 } 189 190 printf("CPU: %s\n", desc); 191 192 return 0; 193 } 194 #endif 195 196 static int announce_dram_init(void) 197 { 198 puts("DRAM: "); 199 return 0; 200 } 201 202 static int show_dram_config(void) 203 { 204 unsigned long long size; 205 206 #ifdef CONFIG_NR_DRAM_BANKS 207 int i; 208 209 debug("\nRAM Configuration:\n"); 210 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 211 size += gd->bd->bi_dram[i].size; 212 debug("Bank #%d: %llx ", i, 213 (unsigned long long)(gd->bd->bi_dram[i].start)); 214 #ifdef DEBUG 215 print_size(gd->bd->bi_dram[i].size, "\n"); 216 #endif 217 } 218 debug("\nDRAM: "); 219 #else 220 size = gd->ram_size; 221 #endif 222 223 print_size(size, ""); 224 board_add_ram_info(0); 225 putc('\n'); 226 227 return 0; 228 } 229 230 __weak int dram_init_banksize(void) 231 { 232 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 233 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 234 gd->bd->bi_dram[0].size = get_effective_memsize(); 235 #endif 236 237 return 0; 238 } 239 240 #if defined(CONFIG_SYS_I2C) 241 static int init_func_i2c(void) 242 { 243 puts("I2C: "); 244 #ifdef CONFIG_SYS_I2C 245 i2c_init_all(); 246 #else 247 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 248 #endif 249 puts("ready\n"); 250 return 0; 251 } 252 #endif 253 254 #if defined(CONFIG_VID) 255 __weak int init_func_vid(void) 256 { 257 return 0; 258 } 259 #endif 260 261 #if defined(CONFIG_HARD_SPI) 262 static int init_func_spi(void) 263 { 264 puts("SPI: "); 265 spi_init(); 266 puts("ready\n"); 267 return 0; 268 } 269 #endif 270 271 static int setup_mon_len(void) 272 { 273 #if defined(__ARM__) || defined(__MICROBLAZE__) 274 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 275 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 276 gd->mon_len = (ulong)&_end - (ulong)_init; 277 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 278 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 279 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 280 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 281 #elif defined(CONFIG_SYS_MONITOR_BASE) 282 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 283 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 284 #endif 285 return 0; 286 } 287 288 __weak int arch_cpu_init(void) 289 { 290 return 0; 291 } 292 293 __weak int mach_cpu_init(void) 294 { 295 return 0; 296 } 297 298 /* Get the top of usable RAM */ 299 __weak ulong board_get_usable_ram_top(ulong total_size) 300 { 301 #ifdef CONFIG_SYS_SDRAM_BASE 302 /* 303 * Detect whether we have so much RAM that it goes past the end of our 304 * 32-bit address space. If so, clip the usable RAM so it doesn't. 305 */ 306 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 307 /* 308 * Will wrap back to top of 32-bit space when reservations 309 * are made. 310 */ 311 return 0; 312 #endif 313 return gd->ram_top; 314 } 315 316 static int setup_dest_addr(void) 317 { 318 debug("Monitor len: %08lX\n", gd->mon_len); 319 /* 320 * Ram is setup, size stored in gd !! 321 */ 322 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 323 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 324 /* 325 * Subtract specified amount of memory to hide so that it won't 326 * get "touched" at all by U-Boot. By fixing up gd->ram_size 327 * the Linux kernel should now get passed the now "corrected" 328 * memory size and won't touch it either. This should work 329 * for arch/ppc and arch/powerpc. Only Linux board ports in 330 * arch/powerpc with bootwrapper support, that recalculate the 331 * memory size from the SDRAM controller setup will have to 332 * get fixed. 333 */ 334 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 335 #endif 336 #ifdef CONFIG_SYS_SDRAM_BASE 337 gd->ram_base = CONFIG_SYS_SDRAM_BASE; 338 #endif 339 gd->ram_top = gd->ram_base + get_effective_memsize(); 340 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 341 gd->relocaddr = gd->ram_top; 342 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 343 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 344 /* 345 * We need to make sure the location we intend to put secondary core 346 * boot code is reserved and not used by any part of u-boot 347 */ 348 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 349 gd->relocaddr = determine_mp_bootpg(NULL); 350 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 351 } 352 #endif 353 return 0; 354 } 355 356 #ifdef CONFIG_PRAM 357 /* reserve protected RAM */ 358 static int reserve_pram(void) 359 { 360 ulong reg; 361 362 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 363 gd->relocaddr -= (reg << 10); /* size is in kB */ 364 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 365 gd->relocaddr); 366 return 0; 367 } 368 #endif /* CONFIG_PRAM */ 369 370 /* Round memory pointer down to next 4 kB limit */ 371 static int reserve_round_4k(void) 372 { 373 gd->relocaddr &= ~(4096 - 1); 374 return 0; 375 } 376 377 #ifdef CONFIG_ARM 378 __weak int reserve_mmu(void) 379 { 380 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 381 /* reserve TLB table */ 382 gd->arch.tlb_size = PGTABLE_SIZE; 383 gd->relocaddr -= gd->arch.tlb_size; 384 385 /* round down to next 64 kB limit */ 386 gd->relocaddr &= ~(0x10000 - 1); 387 388 gd->arch.tlb_addr = gd->relocaddr; 389 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 390 gd->arch.tlb_addr + gd->arch.tlb_size); 391 392 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 393 /* 394 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 395 * with location within secure ram. 396 */ 397 gd->arch.tlb_allocated = gd->arch.tlb_addr; 398 #endif 399 #endif 400 401 return 0; 402 } 403 #endif 404 405 static int reserve_video(void) 406 { 407 #ifdef CONFIG_DM_VIDEO 408 ulong addr; 409 int ret; 410 411 addr = gd->relocaddr; 412 ret = video_reserve(&addr); 413 if (ret) 414 return ret; 415 gd->relocaddr = addr; 416 #elif defined(CONFIG_LCD) 417 # ifdef CONFIG_FB_ADDR 418 gd->fb_base = CONFIG_FB_ADDR; 419 # else 420 /* reserve memory for LCD display (always full pages) */ 421 gd->relocaddr = lcd_setmem(gd->relocaddr); 422 gd->fb_base = gd->relocaddr; 423 # endif /* CONFIG_FB_ADDR */ 424 #elif defined(CONFIG_VIDEO) && \ 425 (!defined(CONFIG_PPC)) && \ 426 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 427 !defined(CONFIG_M68K) 428 /* reserve memory for video display (always full pages) */ 429 gd->relocaddr = video_setmem(gd->relocaddr); 430 gd->fb_base = gd->relocaddr; 431 #endif 432 433 return 0; 434 } 435 436 static int reserve_trace(void) 437 { 438 #ifdef CONFIG_TRACE 439 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 440 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 441 debug("Reserving %dk for trace data at: %08lx\n", 442 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 443 #endif 444 445 return 0; 446 } 447 448 static int reserve_uboot(void) 449 { 450 if (!(gd->flags & GD_FLG_SKIP_RELOC)) { 451 /* 452 * reserve memory for U-Boot code, data & bss 453 * round down to next 4 kB limit 454 */ 455 gd->relocaddr -= gd->mon_len; 456 gd->relocaddr &= ~(4096 - 1); 457 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 458 /* round down to next 64 kB limit so that IVPR stays aligned */ 459 gd->relocaddr &= ~(65536 - 1); 460 #endif 461 462 debug("Reserving %ldk for U-Boot at: %08lx\n", 463 gd->mon_len >> 10, gd->relocaddr); 464 } 465 466 gd->start_addr_sp = gd->relocaddr; 467 468 return 0; 469 } 470 471 /* reserve memory for malloc() area */ 472 static int reserve_malloc(void) 473 { 474 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 475 debug("Reserving %dk for malloc() at: %08lx\n", 476 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 477 return 0; 478 } 479 480 /* (permanently) allocate a Board Info struct */ 481 static int reserve_board(void) 482 { 483 if (!gd->bd) { 484 gd->start_addr_sp -= sizeof(bd_t); 485 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 486 memset(gd->bd, '\0', sizeof(bd_t)); 487 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 488 sizeof(bd_t), gd->start_addr_sp); 489 } 490 return 0; 491 } 492 493 static int setup_machine(void) 494 { 495 #ifdef CONFIG_MACH_TYPE 496 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 497 #endif 498 return 0; 499 } 500 501 static int reserve_global_data(void) 502 { 503 gd->start_addr_sp -= sizeof(gd_t); 504 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 505 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 506 sizeof(gd_t), gd->start_addr_sp); 507 return 0; 508 } 509 510 static int reserve_fdt(void) 511 { 512 #ifndef CONFIG_OF_EMBED 513 /* 514 * If the device tree is sitting immediately above our image then we 515 * must relocate it. If it is embedded in the data section, then it 516 * will be relocated with other data. 517 */ 518 if (gd->fdt_blob) { 519 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 520 521 gd->start_addr_sp -= gd->fdt_size; 522 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 523 debug("Reserving %lu Bytes for FDT at: %08lx\n", 524 gd->fdt_size, gd->start_addr_sp); 525 } 526 #endif 527 528 return 0; 529 } 530 531 static int reserve_bootstage(void) 532 { 533 #ifdef CONFIG_BOOTSTAGE 534 int size = bootstage_get_size(); 535 536 gd->start_addr_sp -= size; 537 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 538 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 539 gd->start_addr_sp); 540 #endif 541 542 return 0; 543 } 544 545 __weak int arch_reserve_stacks(void) 546 { 547 return 0; 548 } 549 550 static int reserve_stacks(void) 551 { 552 /* make stack pointer 16-byte aligned */ 553 gd->start_addr_sp -= 16; 554 gd->start_addr_sp &= ~0xf; 555 556 /* 557 * let the architecture-specific code tailor gd->start_addr_sp and 558 * gd->irq_sp 559 */ 560 return arch_reserve_stacks(); 561 } 562 563 static int display_new_sp(void) 564 { 565 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 566 567 return 0; 568 } 569 570 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 571 defined(CONFIG_SH) 572 static int setup_board_part1(void) 573 { 574 bd_t *bd = gd->bd; 575 576 /* 577 * Save local variables to board info struct 578 */ 579 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 580 bd->bi_memsize = gd->ram_size; /* size in bytes */ 581 582 #ifdef CONFIG_SYS_SRAM_BASE 583 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 584 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 585 #endif 586 587 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 588 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 589 #endif 590 #if defined(CONFIG_M68K) 591 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 592 #endif 593 #if defined(CONFIG_MPC83xx) 594 bd->bi_immrbar = CONFIG_SYS_IMMR; 595 #endif 596 597 return 0; 598 } 599 #endif 600 601 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 602 static int setup_board_part2(void) 603 { 604 bd_t *bd = gd->bd; 605 606 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 607 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 608 #if defined(CONFIG_CPM2) 609 bd->bi_cpmfreq = gd->arch.cpm_clk; 610 bd->bi_brgfreq = gd->arch.brg_clk; 611 bd->bi_sccfreq = gd->arch.scc_clk; 612 bd->bi_vco = gd->arch.vco_out; 613 #endif /* CONFIG_CPM2 */ 614 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 615 bd->bi_pcifreq = gd->pci_clk; 616 #endif 617 #if defined(CONFIG_EXTRA_CLOCK) 618 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 619 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 620 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 621 #endif 622 623 return 0; 624 } 625 #endif 626 627 #ifdef CONFIG_POST 628 static int init_post(void) 629 { 630 post_bootmode_init(); 631 post_run(NULL, POST_ROM | post_bootmode_get(0)); 632 633 return 0; 634 } 635 #endif 636 637 static int reloc_fdt(void) 638 { 639 #ifndef CONFIG_OF_EMBED 640 if (gd->flags & GD_FLG_SKIP_RELOC) 641 return 0; 642 if (gd->new_fdt) { 643 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 644 gd->fdt_blob = gd->new_fdt; 645 } 646 #endif 647 648 return 0; 649 } 650 651 static int reloc_bootstage(void) 652 { 653 #ifdef CONFIG_BOOTSTAGE 654 if (gd->flags & GD_FLG_SKIP_RELOC) 655 return 0; 656 if (gd->new_bootstage) { 657 int size = bootstage_get_size(); 658 659 debug("Copying bootstage from %p to %p, size %x\n", 660 gd->bootstage, gd->new_bootstage, size); 661 memcpy(gd->new_bootstage, gd->bootstage, size); 662 gd->bootstage = gd->new_bootstage; 663 } 664 #endif 665 666 return 0; 667 } 668 669 static int setup_reloc(void) 670 { 671 if (gd->flags & GD_FLG_SKIP_RELOC) { 672 debug("Skipping relocation due to flag\n"); 673 return 0; 674 } 675 676 #ifdef CONFIG_SYS_TEXT_BASE 677 #ifdef ARM 678 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 679 #elif defined(CONFIG_M68K) 680 /* 681 * On all ColdFire arch cpu, monitor code starts always 682 * just after the default vector table location, so at 0x400 683 */ 684 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 685 #else 686 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 687 #endif 688 #endif 689 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 690 691 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 692 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 693 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 694 gd->start_addr_sp); 695 696 return 0; 697 } 698 699 #ifdef CONFIG_OF_BOARD_FIXUP 700 static int fix_fdt(void) 701 { 702 return board_fix_fdt((void *)gd->fdt_blob); 703 } 704 #endif 705 706 /* ARM calls relocate_code from its crt0.S */ 707 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 708 !CONFIG_IS_ENABLED(X86_64) 709 710 static int jump_to_copy(void) 711 { 712 if (gd->flags & GD_FLG_SKIP_RELOC) 713 return 0; 714 /* 715 * x86 is special, but in a nice way. It uses a trampoline which 716 * enables the dcache if possible. 717 * 718 * For now, other archs use relocate_code(), which is implemented 719 * similarly for all archs. When we do generic relocation, hopefully 720 * we can make all archs enable the dcache prior to relocation. 721 */ 722 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 723 /* 724 * SDRAM and console are now initialised. The final stack can now 725 * be setup in SDRAM. Code execution will continue in Flash, but 726 * with the stack in SDRAM and Global Data in temporary memory 727 * (CPU cache) 728 */ 729 arch_setup_gd(gd->new_gd); 730 board_init_f_r_trampoline(gd->start_addr_sp); 731 #else 732 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 733 #endif 734 735 return 0; 736 } 737 #endif 738 739 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 740 static int initf_bootstage(void) 741 { 742 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 743 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 744 int ret; 745 746 ret = bootstage_init(!from_spl); 747 if (ret) 748 return ret; 749 if (from_spl) { 750 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 751 CONFIG_BOOTSTAGE_STASH_SIZE); 752 753 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 754 if (ret && ret != -ENOENT) { 755 debug("Failed to unstash bootstage: err=%d\n", ret); 756 return ret; 757 } 758 } 759 760 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 761 762 return 0; 763 } 764 765 static int initf_console_record(void) 766 { 767 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 768 return console_record_init(); 769 #else 770 return 0; 771 #endif 772 } 773 774 static int initf_dm(void) 775 { 776 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 777 int ret; 778 779 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 780 ret = dm_init_and_scan(true); 781 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 782 if (ret) 783 return ret; 784 #endif 785 #ifdef CONFIG_TIMER_EARLY 786 ret = dm_timer_init(); 787 if (ret) 788 return ret; 789 #endif 790 791 return 0; 792 } 793 794 /* Architecture-specific memory reservation */ 795 __weak int reserve_arch(void) 796 { 797 return 0; 798 } 799 800 __weak int arch_cpu_init_dm(void) 801 { 802 return 0; 803 } 804 805 static const init_fnc_t init_sequence_f[] = { 806 setup_mon_len, 807 #ifdef CONFIG_OF_CONTROL 808 fdtdec_setup, 809 #endif 810 #ifdef CONFIG_TRACE 811 trace_early_init, 812 #endif 813 initf_malloc, 814 log_init, 815 initf_bootstage, /* uses its own timer, so does not need DM */ 816 initf_console_record, 817 #if defined(CONFIG_HAVE_FSP) 818 arch_fsp_init, 819 #endif 820 arch_cpu_init, /* basic arch cpu dependent setup */ 821 mach_cpu_init, /* SoC/machine dependent CPU setup */ 822 initf_dm, 823 arch_cpu_init_dm, 824 #if defined(CONFIG_BOARD_EARLY_INIT_F) 825 board_early_init_f, 826 #endif 827 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 828 /* get CPU and bus clocks according to the environment variable */ 829 get_clocks, /* get CPU and bus clocks (etc.) */ 830 #endif 831 #if !defined(CONFIG_M68K) 832 timer_init, /* initialize timer */ 833 #endif 834 #if defined(CONFIG_BOARD_POSTCLK_INIT) 835 board_postclk_init, 836 #endif 837 env_init, /* initialize environment */ 838 init_baud_rate, /* initialze baudrate settings */ 839 serial_init, /* serial communications setup */ 840 console_init_f, /* stage 1 init of console */ 841 display_options, /* say that we are here */ 842 display_text_info, /* show debugging info if required */ 843 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 844 checkcpu, 845 #endif 846 #if defined(CONFIG_SYSRESET) 847 print_resetinfo, 848 #endif 849 #if defined(CONFIG_DISPLAY_CPUINFO) 850 print_cpuinfo, /* display cpu info (and speed) */ 851 #endif 852 #if defined(CONFIG_DTB_RESELECT) 853 embedded_dtb_select, 854 #endif 855 #if defined(CONFIG_DISPLAY_BOARDINFO) 856 show_board_info, 857 #endif 858 INIT_FUNC_WATCHDOG_INIT 859 #if defined(CONFIG_MISC_INIT_F) 860 misc_init_f, 861 #endif 862 INIT_FUNC_WATCHDOG_RESET 863 #if defined(CONFIG_SYS_I2C) 864 init_func_i2c, 865 #endif 866 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 867 init_func_vid, 868 #endif 869 #if defined(CONFIG_HARD_SPI) 870 init_func_spi, 871 #endif 872 announce_dram_init, 873 dram_init, /* configure available RAM banks */ 874 #ifdef CONFIG_POST 875 post_init_f, 876 #endif 877 INIT_FUNC_WATCHDOG_RESET 878 #if defined(CONFIG_SYS_DRAM_TEST) 879 testdram, 880 #endif /* CONFIG_SYS_DRAM_TEST */ 881 INIT_FUNC_WATCHDOG_RESET 882 883 #ifdef CONFIG_POST 884 init_post, 885 #endif 886 INIT_FUNC_WATCHDOG_RESET 887 /* 888 * Now that we have DRAM mapped and working, we can 889 * relocate the code and continue running from DRAM. 890 * 891 * Reserve memory at end of RAM for (top down in that order): 892 * - area that won't get touched by U-Boot and Linux (optional) 893 * - kernel log buffer 894 * - protected RAM 895 * - LCD framebuffer 896 * - monitor code 897 * - board info struct 898 */ 899 setup_dest_addr, 900 #ifdef CONFIG_PRAM 901 reserve_pram, 902 #endif 903 reserve_round_4k, 904 #ifdef CONFIG_ARM 905 reserve_mmu, 906 #endif 907 reserve_video, 908 reserve_trace, 909 reserve_uboot, 910 reserve_malloc, 911 reserve_board, 912 setup_machine, 913 reserve_global_data, 914 reserve_fdt, 915 reserve_bootstage, 916 reserve_arch, 917 reserve_stacks, 918 dram_init_banksize, 919 show_dram_config, 920 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 921 defined(CONFIG_SH) 922 setup_board_part1, 923 #endif 924 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 925 INIT_FUNC_WATCHDOG_RESET 926 setup_board_part2, 927 #endif 928 display_new_sp, 929 #ifdef CONFIG_OF_BOARD_FIXUP 930 fix_fdt, 931 #endif 932 INIT_FUNC_WATCHDOG_RESET 933 reloc_fdt, 934 reloc_bootstage, 935 setup_reloc, 936 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 937 copy_uboot_to_ram, 938 do_elf_reloc_fixups, 939 clear_bss, 940 #endif 941 #if defined(CONFIG_XTENSA) 942 clear_bss, 943 #endif 944 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 945 !CONFIG_IS_ENABLED(X86_64) 946 jump_to_copy, 947 #endif 948 NULL, 949 }; 950 951 void board_init_f(ulong boot_flags) 952 { 953 gd->flags = boot_flags; 954 gd->have_console = 0; 955 956 if (initcall_run_list(init_sequence_f)) 957 hang(); 958 959 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 960 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ 961 !defined(CONFIG_ARC) 962 /* NOTREACHED - jump_to_copy() does not return */ 963 hang(); 964 #endif 965 } 966 967 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 968 /* 969 * For now this code is only used on x86. 970 * 971 * init_sequence_f_r is the list of init functions which are run when 972 * U-Boot is executing from Flash with a semi-limited 'C' environment. 973 * The following limitations must be considered when implementing an 974 * '_f_r' function: 975 * - 'static' variables are read-only 976 * - Global Data (gd->xxx) is read/write 977 * 978 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 979 * supported). It _should_, if possible, copy global data to RAM and 980 * initialise the CPU caches (to speed up the relocation process) 981 * 982 * NOTE: At present only x86 uses this route, but it is intended that 983 * all archs will move to this when generic relocation is implemented. 984 */ 985 static const init_fnc_t init_sequence_f_r[] = { 986 #if !CONFIG_IS_ENABLED(X86_64) 987 init_cache_f_r, 988 #endif 989 990 NULL, 991 }; 992 993 void board_init_f_r(void) 994 { 995 if (initcall_run_list(init_sequence_f_r)) 996 hang(); 997 998 /* 999 * The pre-relocation drivers may be using memory that has now gone 1000 * away. Mark serial as unavailable - this will fall back to the debug 1001 * UART if available. 1002 * 1003 * Do the same with log drivers since the memory may not be available. 1004 */ 1005 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1006 #ifdef CONFIG_TIMER 1007 gd->timer = NULL; 1008 #endif 1009 1010 /* 1011 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1012 * Transfer execution from Flash to RAM by calculating the address 1013 * of the in-RAM copy of board_init_r() and calling it 1014 */ 1015 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1016 1017 /* NOTREACHED - board_init_r() does not return */ 1018 hang(); 1019 } 1020 #endif /* CONFIG_X86 */ 1021