1 //#include "io.h" 2 #include <asm/io.h> 3 4 #define MAC1_BASE 0x1e660000 5 #define MAC2_BASE 0x1e680000 6 #define MDIO0_BASE (MAC1_BASE + 0x60) 7 #define MDIO1_BASE (MAC2_BASE + 0x60) 8 #define SCU_BASE 0x1e6e2000 9 10 11 #ifdef CONFIG_ASPEED_AST2600 12 #define MAC3_BASE 0x1e670000 13 #define MAC4_BASE 0x1e690000 14 15 #define PMI_BASE 0x1e650000 16 #undef MDIO0_BASE 17 #undef MDIO1_BASE 18 #define MDIO0_BASE (PMI_BASE + 0x00) 19 #define MDIO1_BASE (PMI_BASE + 0x08) 20 #define MDIO2_BASE (PMI_BASE + 0x10) 21 #define MDIO3_BASE (PMI_BASE + 0x18) 22 #endif 23 24 #define GPIO_BASE 0x1e780000 25 26 /* macros for register access */ 27 #define SCU_RD(offset) readl(SCU_BASE + offset) 28 #define SCU_WR(value, offset) writel(value, SCU_BASE + offset) 29 30 #define MAC1_RD(offset) readl(MAC1_BASE + offset) 31 #define MAC1_WR(value, offset) writel(value, MAC1_BASE + offset) 32 #define MAC2_RD(offset) readl(MAC2_BASE + offset) 33 #define MAC2_WR(value, offset) writel(value, MAC2_BASE + offset) 34 #ifdef CONFIG_ASPEED_AST2600 35 #define MAC3_RD(offset) readl(MAC3_BASE + offset) 36 #define MAC3_WR(value, offset) writel(value, MAC3_BASE + offset) 37 #define MAC4_RD(offset) readl(MAC4_BASE + offset) 38 #define MAC4_WR(value, offset) writel(value, MAC4_BASE + offset) 39 #endif 40 41 #define GPIO_RD(offset) readl(GPIO_BASE + offset) 42 #define GPIO_WR(value, offset) writel(value, GPIO_BASE + offset) 43 /* typedef for register access */ 44 typedef union { 45 uint32_t w; 46 struct { 47 uint32_t reserved_0 : 6; /* bit[5:0] */ 48 uint32_t mac1_interface : 1; /* bit[6] */ 49 uint32_t mac2_interface : 1; /* bit[7] */ 50 uint32_t reserved_1 : 24; /* bit[31:8] */ 51 }b; 52 } hw_strap1_t; 53 54 typedef union { 55 uint32_t w; 56 struct { 57 uint32_t mac3_interface : 1; /* bit[0] */ 58 uint32_t mac4_interface : 1; /* bit[1] */ 59 uint32_t reserved_0 : 30; /* bit[31:2] */ 60 }b; 61 } hw_strap2_t; 62 63 uint32_t SRAM_RD(uint32_t addr);