1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #define MACTEST_C 7 8 #include "swfunc.h" 9 #include "comminf.h" 10 #include <command.h> 11 #include <common.h> 12 #include <malloc.h> 13 #include <net.h> 14 #include <post.h> 15 #include "mem_io.h" 16 17 #include "phy_api.h" 18 #include "mac_api.h" 19 20 #define ARGV_MAC_IDX 1 21 #define ARGV_MDIO_IDX 2 22 #define ARGV_SPEED 3 23 #define ARGV_CTRL 4 24 #define ARGV_LOOP 5 25 #define ARGV_TEST_MODE 6 26 #define ARGV_PHY_ADDR 7 27 #define ARGV_TIMING_MARGIN 8 28 29 30 uint8_t __attribute__ ((aligned (1024*1024))) tdes_buf[TDES_SIZE]; 31 uint8_t __attribute__ ((aligned (1024*1024))) rdes_buf[RDES_SIZE]; 32 uint8_t __attribute__ ((aligned (1024*1024))) dma_buf[DMA_BUF_SIZE]; 33 34 struct mac_ctrl_desc { 35 uint32_t base_reset_assert; 36 uint32_t bit_reset_assert; 37 uint32_t base_reset_deassert; 38 uint32_t bit_reset_deassert; 39 40 uint32_t base_clk_stop; 41 uint32_t bit_clk_stop; 42 uint32_t base_clk_start; 43 uint32_t bit_clk_start; 44 }; 45 46 static const uint32_t timeout_th_tbl[3] = { 47 TIME_OUT_Des_1G, TIME_OUT_Des_100M, TIME_OUT_Des_10M}; 48 #if defined(CONFIG_ASPEED_AST2600) 49 const uint32_t mac_base_lookup_tbl[4] = {MAC1_BASE, MAC2_BASE, MAC3_BASE, 50 MAC4_BASE}; 51 const uint32_t mdio_base_lookup_tbl[4] = {MDIO0_BASE, MDIO1_BASE, MDIO2_BASE, 52 MDIO3_BASE}; 53 const struct mac_ctrl_desc mac_ctrl_lookup_tbl[4] = { 54 { 55 .base_reset_assert = 0x40, .bit_reset_assert = BIT(11), 56 .base_reset_deassert = 0x44,.bit_reset_deassert = BIT(11), 57 .base_clk_stop = 0x80, .bit_clk_stop = BIT(20), 58 .base_clk_start = 0x84, .bit_clk_start = BIT(20), 59 }, 60 { 61 .base_reset_assert = 0x40, .bit_reset_assert = BIT(12), 62 .base_reset_deassert = 0x44,.bit_reset_deassert = BIT(12), 63 .base_clk_stop = 0x80, .bit_clk_stop = BIT(21), 64 .base_clk_start = 0x84,.bit_clk_start = BIT(21), 65 }, 66 { 67 .base_reset_assert = 0x50, .bit_reset_assert = BIT(20), 68 .base_reset_deassert = 0x54,.bit_reset_deassert = BIT(20), 69 .base_clk_stop = 0x90, .bit_clk_stop = BIT(20), 70 .base_clk_start = 0x94, .bit_clk_start = BIT(20), 71 }, 72 { 73 .base_reset_assert = 0x50, .bit_reset_assert = BIT(21), 74 .base_reset_deassert = 0x54,.bit_reset_deassert = BIT(21), 75 .base_clk_stop = 0x90, .bit_clk_stop = BIT(21), 76 .base_clk_start = 0x94,.bit_clk_start = BIT(21), 77 } 78 }; 79 #else 80 const uint32_t mac_base_lookup_tbl[2] = {MAC1_BASE, MAC2_BASE}; 81 const uint32_t mdio_base_lookup_tbl[2] = {MDIO0_BASE, MDIO1_BASE}; 82 const struct mac_ctrl_desc mac_ctrl_lookup_tbl[2] = { 83 { 84 .base_reset_assert = 0x04, .bit_reset_assert = BIT(11), 85 .base_reset_deassert = 0x04, .bit_reset_deassert = BIT(11), 86 .base_clk_stop = 0x0c, .bit_clk_stop = BIT(20), 87 .base_clk_start = 0x0c, .bit_clk_start = BIT(20), 88 }, 89 { 90 .base_reset_assert = 0x04, .bit_reset_assert = BIT(12), 91 .base_reset_deassert = 0x04, .bit_reset_deassert = BIT(12), 92 .base_clk_stop = 0x0c, .bit_clk_stop = BIT(21), 93 .base_clk_start = 0x0c, .bit_clk_start = BIT(21), 94 } 95 }; 96 #endif 97 98 void Print_Header(MAC_ENGINE *p_eng, uint8_t option) 99 { 100 if (p_eng->run.speed_sel[0]) { 101 PRINTF(option, " 1G "); 102 } else if (p_eng->run.speed_sel[1]) { 103 PRINTF(option, " 100M "); 104 } else { 105 PRINTF(option, " 10M "); 106 } 107 108 switch (p_eng->arg.test_mode) { 109 case 0: 110 PRINTF(option, "TX/RX delay margin check\n"); 111 break; 112 case 1: 113 PRINTF(option, "TX/RX delay scan\n"); 114 break; 115 case 2: 116 PRINTF(option, "TX/RX delay and IO driving scan\n"); 117 break; 118 case 3: 119 PRINTF(option, "TX frame - ARP\n"); 120 break; 121 case 4: 122 PRINTF(option, "TX frame - random\n"); 123 break; 124 case 5: 125 PRINTF(option, "TX frame - 0x%08x\n", p_eng->arg.user_def_val); 126 break; 127 } 128 } 129 130 static void print_arg_test_mode(MAC_ENGINE *p_eng) 131 { 132 uint8_t item[32] = "test_mode[dec]"; 133 134 if (p_eng->arg.run_mode == MODE_NCSI) { 135 printf("%20s| 0: NCSI configuration with " 136 "Disable_Channel request\n", item); 137 printf("%20s| (default:%3d)\n", "", DEF_GTESTMODE); 138 printf("%20s| 1: TX/RX delay scan\n", ""); 139 printf("%20s| 2: TX/RX delay and IO driving scan\n", ""); 140 printf("%20s| 3: NCSI configuration without " 141 "Disable_Channel request\n", ""); 142 } else { 143 printf("%20s| (default:%3d)\n", item, DEF_GTESTMODE); 144 printf("%20s| 0: TX/RX delay margin check\n", ""); 145 printf("%20s| 1: TX/RX delay scan\n", ""); 146 printf("%20s| 2: TX/RX delay and IO driving scan\n", ""); 147 printf("%20s| 3: TX frame - ARP\n", ""); 148 printf("%20s| 4: TX frame - random\n", ""); 149 printf("%20s| 5: TX frame - user defined (default:0x%8x)\n", "", 150 DEF_GUSER_DEF_PACKET_VAL); 151 } 152 } 153 154 static void print_arg_phy_addr(MAC_ENGINE *p_eng) 155 { 156 uint8_t item[32] = "phy_addr[dec]"; 157 158 printf("%20s| 0~31: PHY Address (default:%d)\n", item, DEF_GPHY_ADR); 159 } 160 161 static void print_arg_ieee_select(MAC_ENGINE *p_eng) 162 { 163 uint8_t item[32] = "IEEE packet select"; 164 165 printf("%20s| 0/1/2 (default:0) only for test_mode 3,4,5)\n", item); 166 } 167 168 static void print_arg_delay_scan_range(MAC_ENGINE *p_eng) 169 { 170 uint8_t item[32] = "TX/RX delay margin"; 171 172 printf("%20s| 1/2/3/... (default:%d) only for test_mode 0\n", item, 173 DEF_GIOTIMINGBUND); 174 printf("%20s| check range = (orig - margin) ~ (orig + margin)\n", ""); 175 } 176 177 static void print_arg_channel_num(MAC_ENGINE *p_eng) 178 { 179 uint8_t item[32] = "channel_num[dec]"; 180 181 printf("%20s| 1~32: Total Number of NCSI Channel (default:%d)\n", item, 182 DEF_GCHANNEL2NUM); 183 } 184 185 static void print_arg_package_num(MAC_ENGINE *p_eng) 186 { 187 uint8_t item[32] = "package_num[dec]"; 188 189 printf("%20s| 1~ 8: Total Number of NCSI Package (default:%d)\n", item, 190 DEF_GPACKAGE2NUM); 191 } 192 193 static void print_arg_loop(MAC_ENGINE *p_eng) 194 { 195 uint8_t item[32] = "loop_max[dec]"; 196 197 printf("%20s| 1G : (default:%3d)\n", item, DEF_GLOOP_MAX * 20); 198 printf("%20s| 100M: (default:%3d)\n", "", DEF_GLOOP_MAX * 2); 199 printf("%20s| 10M : (default:%3d)\n", "", DEF_GLOOP_MAX); 200 } 201 202 static void print_arg_ctrl(MAC_ENGINE *p_eng) 203 { 204 uint8_t item[32] = "ctrl[hex]"; 205 206 printf("%20s| default : 0x%03x\n", item, DEF_GCTRL); 207 printf("%20s| bit0 : skip PHY init/deinit\n", ""); 208 printf("%20s| bit1 : skip PHY deinit\n", ""); 209 printf("%20s| bit2 : skip PHY ID check\n", ""); 210 printf("%20s| bit3 : reserved\n", ""); 211 printf("%20s| bit4 : PHY internal loopback\n", ""); 212 printf("%20s| bit5 : MAC internal loopback\n", ""); 213 printf("%20s| bit6 : Enable PHY RX delay\n", ""); 214 printf("%20s| bit7 : Enable PHY TX delay\n", ""); 215 printf("%20s| bit8 : RMII 50MHz Output enable\n", ""); 216 printf("%20s| bit9 : RMII REFCLK pin input enable\n", ""); 217 printf("%20s| bit10 : inverse RGMII RXCLK\n", ""); 218 printf("%20s| bit11 : reserved\n", ""); 219 printf("%20s| bit12 : TX single packet for each test point\n", ""); 220 printf("%20s| bit13 : full range scan\n", ""); 221 printf("%20s| bit15~14 : reserved\n", ""); 222 printf("%20s| bit16 : NCSI verbose log\n", ""); 223 printf("%20s| bit17 : NCSI skip RX error\n", ""); 224 printf("%20s| bit31~18 : reserved\n", ""); 225 } 226 227 static void print_arg_speed(MAC_ENGINE *p_eng) 228 { 229 uint8_t item[32] = "speed[hex]"; 230 231 printf("%20s| bit[0]->1G bit[1]->100M bit[2]->10M " 232 "(default:0x%02lx)\n", 233 item, DEF_GSPEED); 234 } 235 236 static void print_arg_mdio_idx(MAC_ENGINE *p_eng) 237 { 238 uint8_t item[32] = "mdio_idx[dec]"; 239 240 printf("%20s| 0->MDIO1 1->MDIO2", item); 241 242 if (p_eng->env.mac_num > 2) { 243 printf(" 2->MDIO3 3->MDIO4"); 244 } 245 printf("\n"); 246 } 247 248 static void print_arg_mac_idx(MAC_ENGINE *p_eng) 249 { 250 uint8_t item[32] = "mac_idx[dec]"; 251 252 printf("%20s| 0->MAC1 1->MAC2", item); 253 254 if (p_eng->env.mac_num > 2) { 255 printf(" 2->MAC3 3->MAC4"); 256 } 257 printf("\n"); 258 } 259 static void print_legend(void) 260 { 261 printf("Legend:\n"); 262 printf(" o : OK\n"); 263 printf(" x : CRC error\n"); 264 printf(" . : packet not found\n"); 265 printf(" System default setting\n"); 266 printf(" O : OK\n"); 267 printf(" X : CRC error\n"); 268 printf(" * : packet not found\n"); 269 } 270 static void print_usage(MAC_ENGINE *p_eng) 271 { 272 if (MODE_DEDICATED == p_eng->arg.run_mode) { 273 printf("mactest <mac_idx> <mdio_idx> <speed> <ctrl> <loop_max> <test " 274 "mode> <phy addr> <margin / IEEE select> <user data>\n"); 275 print_arg_mac_idx(p_eng); 276 print_arg_mdio_idx(p_eng); 277 print_arg_speed(p_eng); 278 print_arg_ctrl(p_eng); 279 print_arg_loop(p_eng); 280 print_arg_test_mode(p_eng); 281 print_arg_phy_addr(p_eng); 282 print_arg_delay_scan_range(p_eng); 283 print_arg_ieee_select(p_eng); 284 } else if (MODE_NCSI == p_eng->arg.run_mode) { 285 printf("ncsitest <idx> <packet num> <channel num> <test mode> " 286 "<margin> <ctrl>\n"); 287 print_arg_mac_idx(p_eng); 288 print_arg_package_num(p_eng); 289 print_arg_channel_num(p_eng); 290 print_arg_test_mode(p_eng); 291 print_arg_delay_scan_range(p_eng); 292 print_arg_ctrl(p_eng); 293 } else { 294 printf("unknown run mode\n"); 295 } 296 } 297 298 static void push_reg(MAC_ENGINE *p_eng) 299 { 300 /* SCU delay settings */ 301 p_eng->io.mac12_1g_delay.value.w = readl(p_eng->io.mac12_1g_delay.addr); 302 p_eng->io.mac12_100m_delay.value.w = readl(p_eng->io.mac12_100m_delay.addr); 303 p_eng->io.mac12_10m_delay.value.w = readl(p_eng->io.mac12_10m_delay.addr); 304 305 #ifdef CONFIG_ASPEED_AST2600 306 p_eng->io.mac34_1g_delay.value.w = readl(p_eng->io.mac34_1g_delay.addr); 307 p_eng->io.mac34_100m_delay.value.w = readl(p_eng->io.mac34_100m_delay.addr); 308 p_eng->io.mac34_10m_delay.value.w = readl(p_eng->io.mac34_10m_delay.addr); 309 310 p_eng->io.mac34_drv_reg.value.w = readl(p_eng->io.mac34_drv_reg.addr); 311 #else 312 p_eng->io.mac12_drv_reg.value.w = readl(p_eng->io.mac12_drv_reg.addr); 313 #endif 314 315 /* MAC registers */ 316 p_eng->reg.maccr.w = mac_reg_read(p_eng, 0x50); 317 318 p_eng->reg.mac_madr = mac_reg_read(p_eng, 0x08); 319 p_eng->reg.mac_ladr = mac_reg_read(p_eng, 0x0c); 320 p_eng->reg.mac_fear = mac_reg_read(p_eng, 0x40); 321 } 322 323 static void pop_reg(MAC_ENGINE *p_eng) 324 { 325 /* SCU delay settings */ 326 writel(p_eng->io.mac12_1g_delay.value.w, p_eng->io.mac12_1g_delay.addr); 327 writel(p_eng->io.mac12_100m_delay.value.w, p_eng->io.mac12_100m_delay.addr); 328 writel(p_eng->io.mac12_10m_delay.value.w, p_eng->io.mac12_10m_delay.addr); 329 330 #ifdef CONFIG_ASPEED_AST2600 331 writel(p_eng->io.mac34_1g_delay.value.w, p_eng->io.mac34_1g_delay.addr); 332 writel(p_eng->io.mac34_100m_delay.value.w, p_eng->io.mac34_100m_delay.addr); 333 writel(p_eng->io.mac34_10m_delay.value.w, p_eng->io.mac34_10m_delay.addr); 334 335 writel(p_eng->io.mac34_drv_reg.value.w, p_eng->io.mac34_drv_reg.addr); 336 #else 337 writel(p_eng->io.mac12_drv_reg.value.w, p_eng->io.mac12_drv_reg.addr); 338 #endif 339 340 /* MAC registers */ 341 mac_reg_write(p_eng, 0x50, p_eng->reg.maccr.w); 342 mac_reg_write(p_eng, 0x08, p_eng->reg.mac_madr); 343 mac_reg_write(p_eng, 0x0c, p_eng->reg.mac_ladr); 344 mac_reg_write(p_eng, 0x40, p_eng->reg.mac_fear); 345 } 346 347 static void finish_close(MAC_ENGINE *p_eng) 348 { 349 nt_log_func_name(); 350 pop_reg(p_eng); 351 } 352 353 char finish_check(MAC_ENGINE *p_eng, int value) 354 { 355 nt_log_func_name(); 356 357 if (p_eng->arg.run_mode == MODE_DEDICATED) { 358 if (p_eng->dat.FRAME_LEN) 359 free(p_eng->dat.FRAME_LEN); 360 361 if (p_eng->dat.wp_lst) 362 free(p_eng->dat.wp_lst); 363 } 364 365 p_eng->flg.error = p_eng->flg.error | value; 366 367 if (DBG_PRINT_ERR_FLAG) 368 printf("flags: error = %08x\n", p_eng->flg.error); 369 370 if (!p_eng->run.tm_tx_only) 371 FPri_ErrFlag(p_eng, FP_LOG); 372 373 if (p_eng->run.TM_IOTiming) 374 FPri_ErrFlag(p_eng, FP_IO); 375 376 FPri_ErrFlag(p_eng, STD_OUT); 377 378 if (!p_eng->run.tm_tx_only) 379 FPri_End(p_eng, FP_LOG); 380 381 if (p_eng->run.TM_IOTiming) 382 FPri_End(p_eng, FP_IO); 383 384 FPri_End(p_eng, STD_OUT); 385 386 if (!p_eng->run.tm_tx_only) 387 FPri_RegValue(p_eng, FP_LOG); 388 if (p_eng->run.TM_IOTiming) 389 FPri_RegValue(p_eng, FP_IO); 390 391 finish_close(p_eng); 392 393 if (p_eng->flg.error) { 394 return (1); 395 } else { 396 return (0); 397 } 398 } 399 400 static uint32_t check_test_mode(MAC_ENGINE *p_eng) 401 { 402 if (p_eng->arg.run_mode == MODE_NCSI ) { 403 switch (p_eng->arg.test_mode) { 404 case 0: 405 break; 406 case 1: 407 p_eng->run.TM_IOTiming = 1; 408 break; 409 case 2: 410 p_eng->run.TM_IOTiming = 1; 411 p_eng->run.TM_IOStrength = 1; 412 break; 413 case 3: 414 p_eng->run.TM_NCSI_DiSChannel = 0; 415 break; 416 default: 417 printf("Error test_mode!!!\n"); 418 print_arg_test_mode(p_eng); 419 return (1); 420 } 421 } else { 422 switch (p_eng->arg.test_mode) { 423 case 0: 424 break; 425 case 1: 426 p_eng->run.TM_IOTiming = 1; 427 break; 428 case 2: 429 p_eng->run.TM_IOTiming = 1; 430 p_eng->run.TM_IOStrength = 1; 431 break; 432 case 3: 433 /* TX ARP frame */ 434 p_eng->run.TM_RxDataEn = 0; 435 p_eng->run.tm_tx_only = 1; 436 p_eng->run.TM_IEEE = 0; 437 break; 438 case 4: 439 case 5: 440 p_eng->run.TM_RxDataEn = 0; 441 p_eng->run.tm_tx_only = 1; 442 p_eng->run.TM_IEEE = 1; 443 break; 444 default: 445 printf("Error test_mode!!!\n"); 446 print_arg_test_mode(p_eng); 447 return (1); 448 } 449 } 450 451 if (0 == p_eng->run.TM_IOStrength) { 452 p_eng->io.drv_upper_bond = 0; 453 } 454 return 0; 455 } 456 457 /** 458 * @brief enable/disable MAC 459 * @param[in] p_eng - MAC_ENGINE 460 * 461 * AST2600 uses synchronous reset scheme, so the bits for reset assert and 462 * deassert are the same 463 * e.g. MAC#1: SCU04[11] = 1 --> MAC#1 reset assert 464 * = 0 --> MAC#1 reset de-assert 465 * 466 * AST2600 uses asynchronous reset scheme, so the bits for reset assert and 467 * deassert are different 468 * e.g. MAC#1: SCU40[11] = 1 --> MAC#1 reset assert 469 * SCU44[11] = 1 --> MAC#1 reset de-assert 470 * 471 * The same design concept is also adopted on clock stop/start. 472 */ 473 void scu_disable_mac(MAC_ENGINE *p_eng) 474 { 475 uint32_t mac_idx = p_eng->run.mac_idx; 476 const struct mac_ctrl_desc *p_mac = &mac_ctrl_lookup_tbl[mac_idx]; 477 uint32_t reg; 478 479 debug("MAC%d:reset assert=0x%02x[%08x] deassert=0x%02x[%08x]\n", 480 mac_idx, p_mac->base_reset_assert, p_mac->bit_reset_assert, 481 p_mac->base_reset_deassert, p_mac->bit_reset_deassert); 482 debug("MAC%d:clock stop=0x%02x[%08x] start=0x%02x[%08x]\n", mac_idx, 483 p_mac->base_clk_stop, p_mac->bit_clk_stop, p_mac->base_clk_start, 484 p_mac->bit_clk_start); 485 486 reg = SCU_RD(p_mac->base_reset_assert); 487 debug("reset reg: 0x%08x\n", reg); 488 reg |= p_mac->bit_reset_assert; 489 debug("reset reg: 0x%08x\n", reg); 490 SCU_WR(reg, p_mac->base_reset_assert); 491 /* issue a dummy read to ensure command is in order */ 492 reg = SCU_RD(p_mac->base_reset_assert); 493 494 reg = SCU_RD(p_mac->base_clk_stop); 495 debug("clock reg: 0x%08x\n", reg); 496 reg |= p_mac->bit_clk_stop; 497 debug("clock reg: 0x%08x\n", reg); 498 SCU_WR(reg, p_mac->base_clk_stop); 499 /* issue a dummy read to ensure command is in order */ 500 reg = SCU_RD(p_mac->base_clk_stop); 501 } 502 503 void scu_enable_mac(MAC_ENGINE *p_eng) 504 { 505 uint32_t mac_idx = p_eng->run.mac_idx; 506 const struct mac_ctrl_desc *p_mac = &mac_ctrl_lookup_tbl[mac_idx]; 507 uint32_t reg; 508 509 debug("MAC%d:reset assert=0x%02x[%08x] deassert=0x%02x[%08x]\n", 510 mac_idx, p_mac->base_reset_assert, p_mac->bit_reset_assert, 511 p_mac->base_reset_deassert, p_mac->bit_reset_deassert); 512 debug("MAC%d:clock stop=0x%02x[%08x] start=0x%02x[%08x]\n", mac_idx, 513 p_mac->base_clk_stop, p_mac->bit_clk_stop, p_mac->base_clk_start, 514 p_mac->bit_clk_start); 515 516 #ifdef CONFIG_ASPEED_AST2600 517 reg = SCU_RD(p_mac->base_reset_deassert); 518 debug("reset reg: 0x%08x\n", reg); 519 reg |= p_mac->bit_reset_deassert; 520 debug("reset reg: 0x%08x\n", reg); 521 SCU_WR(reg, p_mac->base_reset_deassert); 522 /* issue a dummy read to ensure command is in order */ 523 reg = SCU_RD(p_mac->base_reset_deassert); 524 525 reg = SCU_RD(p_mac->base_clk_start); 526 debug("clock reg: 0x%08x\n", reg); 527 reg |= p_mac->bit_clk_start; 528 debug("clock reg: 0x%08x\n", reg); 529 SCU_WR(reg, p_mac->base_clk_start); 530 /* issue a dummy read to ensure command is in order */ 531 reg = SCU_RD(p_mac->base_clk_start); 532 533 /* deassert MDIO reset */ 534 SCU_WR(BIT(3), 0x54); 535 #else 536 reg = SCU_RD(p_mac->base_reset_assert); 537 debug("reset reg: 0x%08x\n", reg); 538 reg &= ~p_mac->bit_reset_assert; 539 debug("reset reg: 0x%08x\n", reg); 540 SCU_WR(reg, p_mac->base_reset_assert); 541 542 reg = SCU_RD(p_mac->base_clk_stop); 543 debug("clock reg: 0x%08x\n", reg); 544 reg &= ~p_mac->bit_clk_stop; 545 debug("clock reg: 0x%08x\n", reg); 546 SCU_WR(reg, p_mac->base_clk_stop); 547 #endif 548 } 549 550 /** 551 * @brief setup mdc/mdio pinmix 552 * @todo push/pop pinmux registers 553 */ 554 void scu_set_pinmux(MAC_ENGINE *p_eng) 555 { 556 uint32_t reg; 557 nt_log_func_name(); 558 559 #ifdef CONFIG_ASPEED_AST2600 560 /* MDC/MDIO pinmux */ 561 switch (p_eng->run.mdio_idx) { 562 case 0: 563 reg = SCU_RD(0x430) | GENMASK(17, 16); 564 SCU_WR(reg, 0x430); 565 break; 566 case 1: 567 reg = SCU_RD(0x470) & ~GENMASK(13, 12); 568 SCU_WR(reg, 0x470); 569 reg = SCU_RD(0x410) | GENMASK(13, 12); 570 SCU_WR(reg, 0x410); 571 break; 572 case 2: 573 reg = SCU_RD(0x470) & ~GENMASK(1, 0); 574 SCU_WR(reg, 0x470); 575 reg = SCU_RD(0x410) | GENMASK(1, 0); 576 SCU_WR(reg, 0x410); 577 break; 578 case 3: 579 reg = SCU_RD(0x470) & ~GENMASK(3, 2); 580 SCU_WR(reg, 0x470); 581 reg = SCU_RD(0x410) | GENMASK(3, 2); 582 SCU_WR(reg, 0x410); 583 break; 584 default: 585 printf("%s:undefined MDIO idx %d\n", __func__, 586 p_eng->run.mdio_idx); 587 } 588 589 switch (p_eng->run.mac_idx) { 590 case 0: 591 #ifdef CONFIG_FPGA_ASPEED 592 setbits_le32(SCU_BASE + 0x410, BIT(4)); 593 #else 594 setbits_le32(SCU_BASE + 0x400, GENMASK(11, 0)); 595 setbits_le32(SCU_BASE + 0x410, BIT(4)); 596 clrbits_le32(SCU_BASE + 0x470, BIT(4)); 597 #endif 598 break; 599 case 1: 600 setbits_le32(SCU_BASE + 0x400, GENMASK(23, 12)); 601 setbits_le32(SCU_BASE + 0x410, BIT(5)); 602 clrbits_le32(SCU_BASE + 0x470, BIT(5)); 603 break; 604 case 2: 605 setbits_le32(SCU_BASE + 0x410, GENMASK(27, 16)); 606 setbits_le32(SCU_BASE + 0x410, BIT(6)); 607 clrbits_le32(SCU_BASE + 0x470, BIT(6)); 608 break; 609 case 3: 610 clrbits_le32(SCU_BASE + 0x410, GENMASK(31, 28)); 611 setbits_le32(SCU_BASE + 0x4b0, GENMASK(31, 28)); 612 clrbits_le32(SCU_BASE + 0x474, GENMASK(7, 0)); 613 clrbits_le32(SCU_BASE + 0x414, GENMASK(7, 0)); 614 setbits_le32(SCU_BASE + 0x4b4, GENMASK(7, 0)); 615 setbits_le32(SCU_BASE + 0x410, BIT(7)); 616 clrbits_le32(SCU_BASE + 0x470, BIT(7)); 617 break; 618 619 } 620 621 debug("SCU410: %08x %08x %08x %08x\n", SCU_RD(0x410), SCU_RD(0x414), SCU_RD(0x418), SCU_RD(0x41c)); 622 debug("SCU430: %08x %08x %08x %08x\n", SCU_RD(0x430), SCU_RD(0x434), SCU_RD(0x438), SCU_RD(0x43c)); 623 debug("SCU470: %08x %08x %08x %08x\n", SCU_RD(0x470), SCU_RD(0x474), SCU_RD(0x478), SCU_RD(0x47c)); 624 debug("SCU4b0: %08x %08x %08x %08x\n", SCU_RD(0x4b0), SCU_RD(0x4b4), SCU_RD(0x4b8), SCU_RD(0x4bc)); 625 #else 626 /* MDC/MDIO pinmux */ 627 if (p_eng->run.mdio_idx == 0) { 628 setbits_le32(SCU_BASE + 88, GENMASK(31, 30)); 629 } else { 630 clrsetbits_le32(SCU_BASE + 90, BIT(6), BIT(2)); 631 } 632 633 /* enable MAC#nLINK pin */ 634 setbits_le32(SCU_BASE + 80, BIT(p_eng->run.mac_idx)); 635 #endif 636 } 637 638 static uint32_t check_mac_idx(MAC_ENGINE *p_eng) 639 { 640 /* check if legal run_idx */ 641 if (p_eng->arg.mac_idx > p_eng->env.mac_num - 1) { 642 printf("invalid run_idx = %d\n", p_eng->arg.mac_idx); 643 return 1; 644 } 645 646 return 0; 647 } 648 649 static void calc_loop_check_num(MAC_ENGINE *p_eng) 650 { 651 nt_log_func_name(); 652 653 if (p_eng->run.IO_MrgChk || 654 (p_eng->arg.run_speed == SET_1G_100M_10MBPS) || 655 (p_eng->arg.run_speed == SET_100M_10MBPS)) { 656 p_eng->run.LOOP_CheckNum = p_eng->run.loop_max; 657 } else { 658 switch (p_eng->arg.run_speed) { 659 case SET_1GBPS: 660 p_eng->run.CheckBuf_MBSize = MOVE_DATA_MB_SEC; 661 break; 662 case SET_100MBPS: 663 p_eng->run.CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 3); 664 break; 665 case SET_10MBPS: 666 p_eng->run.CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 6); 667 break; 668 } 669 p_eng->run.LOOP_CheckNum = 670 (p_eng->run.CheckBuf_MBSize / 671 (((p_eng->dat.Des_Num * DMA_PakSize) >> 20) + 1)); 672 } 673 } 674 static uint32_t setup_interface(MAC_ENGINE *p_eng); 675 static uint32_t setup_running(MAC_ENGINE *p_eng) 676 { 677 uint32_t n_desp_min; 678 int i; 679 680 if (0 != check_mac_idx(p_eng)) { 681 return 1; 682 } 683 p_eng->run.mac_idx = p_eng->arg.mac_idx; 684 p_eng->run.mac_base = mac_base_lookup_tbl[p_eng->run.mac_idx]; 685 686 p_eng->run.mdio_idx = p_eng->arg.mdio_idx; 687 p_eng->run.mdio_base = mdio_base_lookup_tbl[p_eng->run.mdio_idx]; 688 689 p_eng->run.is_rgmii = p_eng->env.is_1g_valid[p_eng->run.mac_idx]; 690 691 if (p_eng->arg.run_mode == MODE_NCSI) { 692 #ifdef CONFIG_ASPEED_AST2600 693 /** 694 * NCSI needs for 3.3V IO voltage but MAC#1 & MAC#2 only 695 * support 1.8V. So NCSI can only runs on MAC#3 or MAC#4 696 */ 697 if (p_eng->run.mac_idx < 2) { 698 printf("\nNCSI must runs on MAC#3 or MAC#4\n"); 699 return 1; 700 } 701 702 if (p_eng->run.is_rgmii) { 703 hw_strap2_t strap2; 704 705 printf("\nNCSI must be RMII interface, force the strap value:\n"); 706 printf("\nbefore: SCU510=%08x\n", SCU_RD(0x510)); 707 strap2.w = 0; 708 if (p_eng->run.mac_idx == 2) { 709 strap2.b.mac3_interface = 1; 710 } else if (p_eng->run.mac_idx == 3) { 711 strap2.b.mac4_interface = 1; 712 } 713 SCU_WR(strap2.w, 0x514); 714 while (SCU_RD(0x510) & strap2.w); 715 printf("\nafter: SCU510=%08x\n", SCU_RD(0x510)); 716 /* update interface setting */ 717 setup_interface(p_eng); 718 p_eng->run.is_rgmii = p_eng->env.is_1g_valid[p_eng->run.mac_idx]; 719 } 720 #else 721 if (p_eng->run.is_rgmii) { 722 printf("\nNCSI must be RMII interface\n"); 723 return 1; 724 } 725 #endif 726 } 727 728 for (i = 0; i < 3; i++) { 729 if (p_eng->arg.run_speed & (1 << i)) 730 p_eng->run.speed_cfg[i] = 1; 731 } 732 733 if (p_eng->arg.run_mode == MODE_NCSI) { 734 /* 735 * [Arg]check GPackageTolNum 736 * [Arg]check GChannelTolNum 737 */ 738 if ((p_eng->arg.GPackageTolNum < 1) || 739 (p_eng->arg.GPackageTolNum > 8)) { 740 print_arg_package_num(p_eng); 741 return (1); 742 } 743 if ((p_eng->arg.GChannelTolNum < 1) || 744 (p_eng->arg.GChannelTolNum > 32)) { 745 print_arg_channel_num(p_eng); 746 return (1); 747 } 748 } else { 749 /* [Arg]check ctrl */ 750 if (p_eng->arg.ctrl.w & 0xfffc0000) { 751 print_arg_ctrl(p_eng); 752 return (1); 753 } 754 755 if (p_eng->arg.phy_addr > 31) { 756 printf("Error phy_adr!!!\n"); 757 print_arg_phy_addr(p_eng); 758 return (1); 759 } 760 761 if (0 == p_eng->arg.loop_max) { 762 switch (p_eng->arg.run_speed) { 763 case SET_1GBPS: 764 p_eng->arg.loop_max = DEF_GLOOP_MAX * 20; 765 break; 766 case SET_100MBPS: 767 p_eng->arg.loop_max = DEF_GLOOP_MAX * 2; 768 break; 769 case SET_10MBPS: 770 p_eng->arg.loop_max = DEF_GLOOP_MAX; 771 break; 772 case SET_1G_100M_10MBPS: 773 p_eng->arg.loop_max = DEF_GLOOP_MAX * 20; 774 break; 775 case SET_100M_10MBPS: 776 p_eng->arg.loop_max = DEF_GLOOP_MAX * 2; 777 break; 778 } 779 } 780 } 781 782 if (0 != check_test_mode(p_eng)) { 783 return 1; 784 } 785 786 if (p_eng->run.tm_tx_only) { 787 p_eng->run.ieee_sel = p_eng->arg.ieee_sel; 788 p_eng->run.delay_margin = 0; 789 } else { 790 p_eng->run.ieee_sel = 0; 791 p_eng->run.delay_margin = p_eng->arg.delay_scan_range; 792 #if 0 793 if (p_eng->run.delay_margin == 0) { 794 printf("Error IO margin!!!\n"); 795 print_arg_delay_scan_range(p_eng); 796 return(1); 797 } 798 #endif 799 } 800 801 if (!p_eng->env.is_1g_valid[p_eng->run.mac_idx]) 802 p_eng->run.speed_cfg[ 0 ] = 0; 803 804 p_eng->run.tdes_base = (uint32_t)(&tdes_buf[0]); 805 p_eng->run.rdes_base = (uint32_t)(&rdes_buf[0]); 806 807 if (p_eng->run.TM_IOTiming || p_eng->run.delay_margin) 808 p_eng->run.IO_MrgChk = 1; 809 else 810 p_eng->run.IO_MrgChk = 0; 811 812 p_eng->phy.Adr = p_eng->arg.phy_addr; 813 p_eng->phy.loopback = p_eng->arg.ctrl.b.phy_int_loopback; 814 p_eng->phy.default_phy = p_eng->run.TM_DefaultPHY; 815 816 p_eng->run.loop_max = p_eng->arg.loop_max; 817 calc_loop_check_num(p_eng); 818 819 //------------------------------------------------------------ 820 // Descriptor Number 821 //------------------------------------------------------------ 822 //------------------------------ 823 // [Dat]setup Des_Num 824 // [Dat]setup DMABuf_Size 825 // [Dat]setup DMABuf_Num 826 //------------------------------ 827 if (p_eng->arg.run_mode == MODE_DEDICATED) { 828 n_desp_min = p_eng->run.TM_IOTiming; 829 830 if (p_eng->arg.ctrl.b.skip_phy_id_check && 831 (p_eng->arg.test_mode == 0)) 832 /* for SMSC's LAN9303 issue */ 833 p_eng->dat.Des_Num = 114; 834 else { 835 switch (p_eng->arg.run_speed) { 836 case SET_1GBPS: 837 p_eng->dat.Des_Num = 838 p_eng->run.delay_margin 839 ? 100 840 : (n_desp_min) ? 512 : 4096; 841 break; 842 case SET_100MBPS: 843 p_eng->dat.Des_Num = 844 p_eng->run.delay_margin 845 ? 100 846 : (n_desp_min) ? 512 : 4096; 847 break; 848 case SET_10MBPS: 849 p_eng->dat.Des_Num = 850 p_eng->run.delay_margin 851 ? 100 852 : (n_desp_min) ? 100 : 830; 853 break; 854 case SET_1G_100M_10MBPS: 855 p_eng->dat.Des_Num = 856 p_eng->run.delay_margin 857 ? 100 858 : (n_desp_min) ? 100 : 830; 859 break; 860 case SET_100M_10MBPS: 861 p_eng->dat.Des_Num = 862 p_eng->run.delay_margin 863 ? 100 864 : (n_desp_min) ? 100 : 830; 865 break; 866 } 867 } 868 869 if (p_eng->arg.ctrl.b.single_packet) 870 p_eng->dat.Des_Num = 1; 871 872 /* keep in order: Des_Num -> DMABuf_Size -> DMABuf_Num */ 873 p_eng->dat.Des_Num_Org = p_eng->dat.Des_Num; 874 p_eng->dat.DMABuf_Size = DMA_BufSize; 875 p_eng->dat.DMABuf_Num = DMA_BufNum; 876 877 if (DbgPrn_Info) { 878 printf("CheckBuf_MBSize : %d\n", 879 p_eng->run.CheckBuf_MBSize); 880 printf("LOOP_CheckNum : %d\n", 881 p_eng->run.LOOP_CheckNum); 882 printf("Des_Num : %d\n", p_eng->dat.Des_Num); 883 printf("DMA_BufSize : %d bytes\n", 884 p_eng->dat.DMABuf_Size); 885 printf("DMA_BufNum : %d\n", p_eng->dat.DMABuf_Num); 886 printf("DMA_PakSize : %d\n", DMA_PakSize); 887 printf("\n"); 888 } 889 if (2 > p_eng->dat.DMABuf_Num) 890 return (finish_check(p_eng, Err_Flag_DMABufNum)); 891 } 892 893 return 0; 894 } 895 896 /** 897 * @brief setup environment according to HW strap registers 898 */ 899 static uint32_t setup_interface(MAC_ENGINE *p_eng) 900 { 901 #ifdef CONFIG_ASPEED_AST2600 902 hw_strap1_t strap1; 903 hw_strap2_t strap2; 904 905 strap1.w = SCU_RD(0x500); 906 strap2.w = SCU_RD(0x510); 907 908 p_eng->env.is_1g_valid[0] = strap1.b.mac1_interface; 909 p_eng->env.is_1g_valid[1] = strap1.b.mac2_interface; 910 p_eng->env.is_1g_valid[2] = strap2.b.mac3_interface; 911 p_eng->env.is_1g_valid[3] = strap2.b.mac4_interface; 912 913 p_eng->env.at_least_1g_valid = 914 p_eng->env.is_1g_valid[0] | p_eng->env.is_1g_valid[1] | 915 p_eng->env.is_1g_valid[2] | p_eng->env.is_1g_valid[3]; 916 #else 917 hw_strap1_t strap1; 918 strap1.w = SCU_RD(0x70); 919 p_eng->env.is_1g_valid[0] = strap1.b.mac1_interface; 920 p_eng->env.is_1g_valid[1] = strap1.b.mac2_interface; 921 922 p_eng->env.at_least_1g_valid = 923 p_eng->env.is_1g_valid[0] | p_eng->env.is_1g_valid[1]; 924 #endif 925 return 0; 926 } 927 928 /** 929 * @brief setup chip compatibility accoriding to the chip ID register 930 */ 931 static uint32_t setup_chip_compatibility(MAC_ENGINE *p_eng) 932 { 933 uint32_t reg_addr; 934 uint32_t id, version; 935 uint32_t is_valid; 936 937 p_eng->env.ast2600 = 0; 938 p_eng->env.ast2500 = 0; 939 940 #if defined(CONFIG_ASPEED_AST2600) 941 reg_addr = 0x04; 942 #else 943 reg_addr = 0x7c; 944 #endif 945 is_valid = 0; 946 id = (SCU_RD(reg_addr) & GENMASK(31, 24)) >> 24; 947 version = (SCU_RD(reg_addr) & GENMASK(23, 16)) >> 16; 948 949 #if defined(CONFIG_FPGA_ASPEED) && defined(CONFIG_ASPEED_AST2600) 950 id = 0x5; 951 #endif 952 if (id == 0x5) { 953 printf("chip: AST2600 A%d\n", version); 954 p_eng->env.ast2600 = 1; 955 p_eng->env.ast2500 = 1; 956 p_eng->env.mac_num = 4; 957 p_eng->env.is_new_mdio_reg[0] = 1; 958 p_eng->env.is_new_mdio_reg[1] = 1; 959 p_eng->env.is_new_mdio_reg[2] = 1; 960 p_eng->env.is_new_mdio_reg[3] = 1; 961 is_valid = 1; 962 } else if (id == 0x4) { 963 printf("chip: AST2500 A%d\n", version); 964 p_eng->env.ast2500 = 1; 965 p_eng->env.mac_num = 2; 966 p_eng->env.is_new_mdio_reg[0] = MAC1_RD(0x40) >> 31; 967 p_eng->env.is_new_mdio_reg[1] = MAC2_RD(0x40) >> 31; 968 is_valid = 1; 969 } 970 971 if (0 == is_valid) { 972 printf("unknown chip\n"); 973 return 1; 974 } 975 976 return 0; 977 } 978 979 /** 980 * @brief setup environment accoriding to the HW strap and chip ID 981 */ 982 static uint32_t setup_env(MAC_ENGINE *p_eng) 983 { 984 if (0 != setup_chip_compatibility(p_eng)) { 985 return 1; 986 } 987 988 setup_interface(p_eng); 989 return 0; 990 } 991 992 static uint32_t init_mac_engine(MAC_ENGINE *p_eng, uint32_t mode) 993 { 994 memset(p_eng, 0, sizeof(MAC_ENGINE)); 995 996 if (0 != setup_env(p_eng)) { 997 return 1; 998 } 999 1000 p_eng->arg.run_mode = mode; 1001 p_eng->arg.delay_scan_range = DEF_GIOTIMINGBUND; 1002 p_eng->arg.test_mode = DEF_GTESTMODE; 1003 1004 if (p_eng->arg.run_mode == MODE_NCSI ) { 1005 p_eng->arg.GARPNumCnt = DEF_GARPNUMCNT; 1006 p_eng->arg.GChannelTolNum = DEF_GCHANNEL2NUM; 1007 p_eng->arg.GPackageTolNum = DEF_GPACKAGE2NUM; 1008 p_eng->arg.ctrl.w = 0; 1009 p_eng->arg.run_speed = SET_100MBPS; // In NCSI mode, we set to 100M bps 1010 } else { 1011 p_eng->arg.user_def_val = DEF_GUSER_DEF_PACKET_VAL; 1012 p_eng->arg.phy_addr = DEF_GPHY_ADR; 1013 p_eng->arg.loop_inf = 0; 1014 p_eng->arg.loop_max = 0; 1015 p_eng->arg.ctrl.w = DEF_GCTRL; 1016 p_eng->arg.run_speed = DEF_GSPEED; 1017 } 1018 1019 p_eng->flg.print_en = 1; 1020 1021 p_eng->run.TM_TxDataEn = 1; 1022 p_eng->run.TM_RxDataEn = 1; 1023 p_eng->run.TM_NCSI_DiSChannel = 1; 1024 1025 /* setup 1026 * 1. delay control register 1027 * 2. driving strength control register and upper/lower bond 1028 * 3. MAC control register 1029 */ 1030 #ifdef CONFIG_ASPEED_AST2600 1031 p_eng->io.mac12_1g_delay.addr = SCU_BASE + 0x340; 1032 p_eng->io.mac12_1g_delay.tx_min = 0; 1033 p_eng->io.mac12_1g_delay.tx_max = 63; 1034 p_eng->io.mac12_1g_delay.rx_min = -63; 1035 p_eng->io.mac12_1g_delay.rx_max = 63; 1036 p_eng->io.mac12_1g_delay.rmii_tx_min = 0; 1037 p_eng->io.mac12_1g_delay.rmii_tx_max = 1; 1038 p_eng->io.mac12_1g_delay.rmii_rx_min = 0; 1039 p_eng->io.mac12_1g_delay.rmii_rx_max = 63; 1040 1041 p_eng->io.mac12_100m_delay.addr = SCU_BASE + 0x348; 1042 p_eng->io.mac12_100m_delay.tx_min = 0; 1043 p_eng->io.mac12_100m_delay.tx_max = 63; 1044 p_eng->io.mac12_100m_delay.rx_min = -63; 1045 p_eng->io.mac12_100m_delay.rx_max = 63; 1046 p_eng->io.mac12_10m_delay.addr = SCU_BASE + 0x34c; 1047 p_eng->io.mac12_10m_delay.tx_min = 0; 1048 p_eng->io.mac12_10m_delay.tx_max = 63; 1049 p_eng->io.mac12_10m_delay.rx_min = -63; 1050 p_eng->io.mac12_10m_delay.rx_max = 63; 1051 1052 p_eng->io.mac34_1g_delay.addr = SCU_BASE + 0x350; 1053 p_eng->io.mac34_1g_delay.tx_min = 0; 1054 p_eng->io.mac34_1g_delay.tx_max = 63; 1055 p_eng->io.mac34_1g_delay.rx_min = -63; 1056 p_eng->io.mac34_1g_delay.rx_max = 63; 1057 p_eng->io.mac34_1g_delay.rmii_tx_min = 0; 1058 p_eng->io.mac34_1g_delay.rmii_tx_max = 1; 1059 p_eng->io.mac34_1g_delay.rmii_rx_min = 0; 1060 p_eng->io.mac34_1g_delay.rmii_rx_max = 63; 1061 p_eng->io.mac34_100m_delay.addr = SCU_BASE + 0x358; 1062 p_eng->io.mac34_100m_delay.tx_min = 0; 1063 p_eng->io.mac34_100m_delay.tx_max = 63; 1064 p_eng->io.mac34_100m_delay.rx_min = -63; 1065 p_eng->io.mac34_100m_delay.rx_max = 63; 1066 p_eng->io.mac34_10m_delay.addr = SCU_BASE + 0x35c; 1067 p_eng->io.mac34_10m_delay.tx_min = 0; 1068 p_eng->io.mac34_10m_delay.tx_max = 63; 1069 p_eng->io.mac34_10m_delay.rx_min = -63; 1070 p_eng->io.mac34_10m_delay.rx_max = 63; 1071 1072 p_eng->io.mac34_drv_reg.addr = SCU_BASE + 0x458; 1073 p_eng->io.mac34_drv_reg.drv_max = 0x3; 1074 p_eng->io.drv_upper_bond = 0x3; 1075 p_eng->io.drv_lower_bond = 0; 1076 #else 1077 p_eng->io.mac12_1g_delay.addr = SCU_BASE + 0x48; 1078 p_eng->io.mac12_1g_delay.tx_min = 0; 1079 p_eng->io.mac12_1g_delay.tx_max = 63; 1080 p_eng->io.mac12_1g_delay.rx_min = 0; 1081 p_eng->io.mac12_1g_delay.rx_max = 63; 1082 p_eng->io.mac12_1g_delay.rmii_tx_min = 0; 1083 p_eng->io.mac12_1g_delay.rmii_tx_max = 1; 1084 p_eng->io.mac12_1g_delay.rmii_rx_min = 0; 1085 p_eng->io.mac12_1g_delay.rmii_rx_max = 63; 1086 p_eng->io.mac12_100m_delay.addr = SCU_BASE + 0xb8; 1087 p_eng->io.mac12_100m_delay.tx_min = 0; 1088 p_eng->io.mac12_100m_delay.tx_max = 63; 1089 p_eng->io.mac12_100m_delay.rx_min = 0; 1090 p_eng->io.mac12_100m_delay.rx_max = 63; 1091 p_eng->io.mac12_10m_delay.addr = SCU_BASE + 0xbc; 1092 p_eng->io.mac12_10m_delay.tx_min = 0; 1093 p_eng->io.mac12_10m_delay.tx_max = 63; 1094 p_eng->io.mac12_10m_delay.rx_min = 0; 1095 p_eng->io.mac12_10m_delay.rx_max = 63; 1096 1097 p_eng->io.mac34_1g_delay.addr = 0; 1098 p_eng->io.mac34_100m_delay.addr = 0; 1099 p_eng->io.mac34_10m_delay.addr = 0; 1100 1101 p_eng->io.mac12_drv_reg.addr = SCU_BASE + 0x90; 1102 p_eng->io.mac12_drv_reg.drv_max = 0x1; 1103 p_eng->io.drv_upper_bond = 0x1; 1104 p_eng->io.drv_lower_bond = 0; 1105 #endif 1106 return 0; 1107 } 1108 1109 static uint32_t parse_arg_dedicated(int argc, char *const argv[], 1110 MAC_ENGINE *p_eng) 1111 { 1112 switch (argc) { 1113 case 10: 1114 p_eng->arg.user_def_val = simple_strtol(argv[9], NULL, 16); 1115 case 9: 1116 p_eng->arg.delay_scan_range = simple_strtol(argv[8], NULL, 10); 1117 p_eng->arg.ieee_sel = p_eng->arg.delay_scan_range; 1118 case 8: 1119 p_eng->arg.phy_addr = simple_strtol(argv[7], NULL, 10); 1120 case 7: 1121 p_eng->arg.test_mode = simple_strtol(argv[6], NULL, 16); 1122 printf("test mode = %d\n", p_eng->arg.test_mode); 1123 case 6: 1124 p_eng->arg.loop_max = simple_strtol(argv[5], NULL, 10); 1125 if (p_eng->arg.loop_max == -1) { 1126 p_eng->arg.loop_inf = 1; 1127 } 1128 printf("loop max=%d, loop_inf=%d\n", p_eng->arg.loop_max, p_eng->arg.loop_inf); 1129 case 5: 1130 p_eng->arg.ctrl.w = simple_strtol(argv[4], NULL, 16); 1131 printf("ctrl=0x%05x\n", p_eng->arg.ctrl.w); 1132 case 4: 1133 p_eng->arg.run_speed = simple_strtol(argv[3], NULL, 16); 1134 printf("speed=0x%1x\n", p_eng->arg.run_speed); 1135 case 3: 1136 p_eng->arg.mdio_idx = simple_strtol(argv[2], NULL, 10); 1137 printf("mdio_idx=%d\n", p_eng->arg.mdio_idx); 1138 } 1139 1140 return 0; 1141 } 1142 1143 static uint32_t parse_arg_ncsi(int argc, char *const argv[], MAC_ENGINE *p_eng) 1144 { 1145 switch (argc) { 1146 case 8: 1147 p_eng->arg.GARPNumCnt = simple_strtol(argv[7], NULL, 10); 1148 case 7: 1149 p_eng->arg.ctrl.w = simple_strtol(argv[6], NULL, 16); 1150 case 6: 1151 p_eng->arg.delay_scan_range = simple_strtol(argv[5], NULL, 10); 1152 case 5: 1153 p_eng->arg.test_mode = simple_strtol(argv[4], NULL, 16); 1154 case 4: 1155 p_eng->arg.GChannelTolNum = simple_strtol(argv[3], NULL, 10); 1156 case 3: 1157 p_eng->arg.GPackageTolNum = simple_strtol(argv[2], NULL, 10); 1158 } 1159 return 0; 1160 } 1161 1162 1163 static void disable_wdt(MAC_ENGINE *p_eng) 1164 { 1165 #ifdef CONFIG_ASPEED_AST2600 1166 writel(0, 0x1e620064); 1167 #else 1168 writel(0, 0x1e78502c); 1169 #endif 1170 return; 1171 } 1172 1173 static uint32_t setup_data(MAC_ENGINE *p_eng) 1174 { 1175 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1176 if (p_eng->run.tm_tx_only) 1177 setup_arp(p_eng); 1178 1179 p_eng->dat.FRAME_LEN = 1180 (uint32_t *)malloc(p_eng->dat.Des_Num * sizeof(uint32_t)); 1181 p_eng->dat.wp_lst = 1182 (uint32_t *)malloc(p_eng->dat.Des_Num * sizeof(uint32_t)); 1183 1184 if (!p_eng->dat.FRAME_LEN) 1185 return (finish_check(p_eng, Err_Flag_MALLOC_FrmSize)); 1186 if (!p_eng->dat.wp_lst) 1187 return (finish_check(p_eng, Err_Flag_MALLOC_LastWP)); 1188 1189 TestingSetup(p_eng); 1190 } else { 1191 if (p_eng->arg.GARPNumCnt != 0) 1192 setup_arp(p_eng); 1193 } 1194 1195 p_eng->run.speed_idx = 0; 1196 p_eng->io.drv_curr = mac_get_driving_strength(p_eng); 1197 if (mac_set_scan_boundary(p_eng)) 1198 return (finish_check(p_eng, 0)); 1199 1200 return 0; 1201 } 1202 1203 static uint32_t get_time_out_th(MAC_ENGINE *p_eng) 1204 { 1205 uint32_t time_out; 1206 1207 time_out = timeout_th_tbl[p_eng->run.speed_idx]; 1208 if (p_eng->run.TM_WaitStart) 1209 time_out = time_out * 10000; 1210 1211 return time_out; 1212 } 1213 uint32_t test_start(MAC_ENGINE *p_eng, PHY_ENGINE *p_phy_eng) 1214 { 1215 uint32_t drv, speed; 1216 int td, rd, tbegin, rbegin, tend, rend; 1217 int tstep, rstep; 1218 1219 uint32_t wrn_flag_allspeed = 0; 1220 uint32_t err_flag_allspeed = 0; 1221 uint32_t des_flag_allspeed = 0; 1222 uint32_t ncsi_flag_allspeed = 0; 1223 1224 memset(&p_eng->io.result_history[0][0], 0, 1225 sizeof(p_eng->io.result_history)); 1226 1227 for (speed = 0; speed < 3; speed++) { 1228 p_eng->flg.print_en = 1; 1229 p_eng->run.speed_idx = speed; 1230 mac_set_scan_boundary(p_eng); 1231 if (0 == p_eng->run.speed_sel[speed]) { 1232 continue; 1233 } 1234 1235 p_eng->run.timeout_th = get_time_out_th(p_eng); 1236 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1237 if ((p_eng->arg.run_speed == SET_1G_100M_10MBPS) || 1238 (p_eng->arg.run_speed == SET_100M_10MBPS)) { 1239 if (p_eng->run.speed_sel[0]) 1240 p_eng->run.loop_max = 1241 p_eng->arg.loop_max; 1242 else if (p_eng->run.speed_sel[1]) 1243 p_eng->run.loop_max = 1244 p_eng->arg.loop_max / 100; 1245 else 1246 p_eng->run.loop_max = 1247 p_eng->arg.loop_max / 1000; 1248 1249 if (0 == p_eng->run.loop_max) 1250 p_eng->run.loop_max = 1; 1251 1252 calc_loop_check_num(p_eng); 1253 } 1254 //------------------------------ 1255 // PHY Initial 1256 //------------------------------ 1257 if (p_phy_eng->fp_set) { 1258 init_phy(p_eng, p_phy_eng); 1259 } 1260 1261 if (p_eng->flg.error) 1262 return (finish_check(p_eng, 0)); 1263 } 1264 1265 //------------------------------ 1266 // [Start] The loop of different IO strength 1267 //------------------------------ 1268 debug("drirving scan range: %d ~ %d\n", 1269 p_eng->io.drv_lower_bond, p_eng->io.drv_upper_bond); 1270 for (drv = p_eng->io.drv_lower_bond; 1271 drv <= p_eng->io.drv_upper_bond; drv++) { 1272 if (p_eng->run.IO_MrgChk) { 1273 if (p_eng->run.TM_IOStrength) { 1274 mac_set_driving_strength(p_eng, drv); 1275 p_eng->io.drv_curr = mac_get_driving_strength(p_eng); 1276 } 1277 1278 if (p_eng->run.delay_margin) 1279 PrintIO_Header(p_eng, FP_LOG); 1280 if (p_eng->run.TM_IOTiming) 1281 PrintIO_Header(p_eng, FP_IO); 1282 PrintIO_Header(p_eng, STD_OUT); 1283 } else { 1284 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1285 Print_Header(p_eng, STD_OUT); 1286 } 1287 } // End if (p_eng->run.IO_MrgChk) 1288 1289 //------------------------------ 1290 // [Start] The loop of different IO out delay 1291 //------------------------------ 1292 tbegin = p_eng->io.tx_delay_scan.begin; 1293 tend = p_eng->io.tx_delay_scan.end; 1294 tstep = p_eng->io.tx_delay_scan.step; 1295 1296 rbegin = p_eng->io.rx_delay_scan.begin; 1297 rend = p_eng->io.rx_delay_scan.end; 1298 rstep = p_eng->io.rx_delay_scan.step; 1299 1300 for (td = tbegin; td <= tend; td += tstep) { 1301 p_eng->io.Dly_out = td; 1302 p_eng->io.Dly_out_selval = td; 1303 if (p_eng->run.IO_MrgChk) { 1304 PrintIO_LineS(p_eng, STD_OUT); 1305 } // End if (p_eng->run.IO_MrgChk) 1306 1307 //------------------------------ 1308 // [Start] The loop of different IO in 1309 // delay 1310 //------------------------------ 1311 for (rd = rbegin; rd <= rend; rd += rstep) { 1312 p_eng->io.Dly_in = rd; 1313 if (p_eng->run.IO_MrgChk) { 1314 p_eng->io.Dly_in_selval = rd; 1315 scu_disable_mac(p_eng); 1316 mac_set_delay(p_eng, rd, td); 1317 scu_enable_mac(p_eng); 1318 } 1319 //------------------------------ 1320 // MAC Initial 1321 //------------------------------ 1322 init_mac(p_eng); 1323 if (p_eng->flg.error) 1324 return (finish_check(p_eng, 0)); 1325 1326 if (p_eng->arg.run_mode == MODE_NCSI) { 1327 p_eng->io.result = 1328 phy_ncsi(p_eng); 1329 } else { 1330 p_eng->io.result = TestingLoop( 1331 p_eng, 1332 p_eng->run.LOOP_CheckNum); 1333 } 1334 1335 p_eng->io.result_history[rd + 64][td] |= 1336 p_eng->io.result; 1337 1338 /* Display to Log file and monitor */ 1339 if (p_eng->run.IO_MrgChk) { 1340 PrintIO_Line(p_eng, STD_OUT); 1341 1342 FPri_ErrFlag(p_eng, FP_LOG); 1343 1344 p_eng->flg.warn = 0; 1345 p_eng->flg.error = 0; 1346 p_eng->flg.desc = 0; 1347 p_eng->flg.ncsi = 0; 1348 } 1349 } 1350 1351 if (p_eng->run.IO_MrgChk) { 1352 if (p_eng->run.TM_IOTiming) { 1353 PRINTF(FP_IO, "\n"); 1354 } 1355 printf("\n"); 1356 } 1357 } 1358 1359 if (!p_eng->run.tm_tx_only) 1360 FPri_ErrFlag(p_eng, FP_LOG); 1361 if (p_eng->run.TM_IOTiming) 1362 FPri_ErrFlag(p_eng, FP_IO); 1363 1364 FPri_ErrFlag(p_eng, STD_OUT); 1365 1366 wrn_flag_allspeed |= p_eng->flg.warn; 1367 err_flag_allspeed |= p_eng->flg.error; 1368 des_flag_allspeed |= p_eng->flg.error; 1369 ncsi_flag_allspeed |= p_eng->flg.error; 1370 p_eng->flg.warn = 0; 1371 p_eng->flg.error = 0; 1372 p_eng->flg.desc = 0; 1373 p_eng->flg.ncsi = 0; 1374 } 1375 1376 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1377 if (p_phy_eng->fp_clr != 0) 1378 recov_phy(p_eng, p_phy_eng); 1379 } 1380 1381 p_eng->run.speed_sel[speed] = 0; 1382 p_eng->flg.print_en = 0; 1383 } // End for (speed = 0; speed < 3; speed++) 1384 1385 p_eng->flg.warn = wrn_flag_allspeed; 1386 p_eng->flg.error = err_flag_allspeed; 1387 p_eng->flg.desc = des_flag_allspeed; 1388 p_eng->flg.ncsi = ncsi_flag_allspeed; 1389 1390 return (finish_check(p_eng, 0)); 1391 } 1392 static uint32_t ring_clk(uint32_t reg_offset, uint32_t clk_sel) 1393 { 1394 uint32_t freq; 1395 1396 SCU_WR(0, reg_offset); 1397 SCU_WR((0xf << 2) | BIT(0), reg_offset); 1398 udelay(1000); 1399 SCU_WR((clk_sel << 2) | BIT(1) | BIT(0), reg_offset); 1400 while ((SCU_RD(reg_offset) & BIT(6)) == 0); 1401 1402 freq = (SCU_RD(reg_offset) & GENMASK(29, 16)) >> 16; 1403 SCU_WR(0, reg_offset); 1404 return ((freq + 1) * 48828); 1405 } 1406 1407 void dump_setting(MAC_ENGINE *p_eng) 1408 { 1409 /* dump env */ 1410 printf("===================\n"); 1411 printf("ast2600 compatible = %d\n", p_eng->env.ast2600); 1412 printf("ast2500 compatible = %d\n", p_eng->env.ast2500); 1413 printf("valid MAC number = %d\n", p_eng->env.mac_num); 1414 printf("use new MDIO register = %d %d %d %d\n", 1415 p_eng->env.is_new_mdio_reg[0], 1416 p_eng->env.is_new_mdio_reg[1], 1417 p_eng->env.is_new_mdio_reg[2], 1418 p_eng->env.is_new_mdio_reg[3]); 1419 printf("1G compatible = %d %d %d %d\n", 1420 p_eng->env.is_1g_valid[0], 1421 p_eng->env.is_1g_valid[1], 1422 p_eng->env.is_1g_valid[2], 1423 p_eng->env.is_1g_valid[3]); 1424 printf("===================\n"); 1425 1426 1427 #if defined(CONFIG_ASPEED_AST2600) 1428 printf("RGMIICK of MAC1/2 = %d Hz\n", ring_clk(0x320, 0xf)); 1429 printf("RGMIICK of MAC3/4 = %d Hz\n", ring_clk(0x330, 0x9)); 1430 printf("EPLL = %d Hz\n", ring_clk(0x320, 0x5) * 4); 1431 printf("HCLK = %d Hz\n", ring_clk(0x330, 0x1)); 1432 #endif 1433 1434 } 1435 /** 1436 * @brief nettest main function 1437 */ 1438 int mac_test(int argc, char * const argv[], uint32_t mode) 1439 { 1440 MAC_ENGINE mac_eng; 1441 PHY_ENGINE phy_eng; 1442 uint32_t ret; 1443 1444 ret = init_mac_engine(&mac_eng, mode); 1445 if (ret) { 1446 printf("init MAC engine fail\n"); 1447 return ret; 1448 } 1449 1450 if (argc <= 1) { 1451 print_usage(&mac_eng); 1452 return 1; 1453 } 1454 1455 mac_eng.arg.mac_idx = simple_strtol(argv[1], NULL, 16); 1456 1457 /* default mdio_idx = mac_idx */ 1458 mac_eng.arg.mdio_idx = mac_eng.arg.mac_idx; 1459 if (MODE_DEDICATED == mode) 1460 parse_arg_dedicated(argc, argv, &mac_eng); 1461 else 1462 parse_arg_ncsi(argc, argv, &mac_eng); 1463 1464 ret = setup_running(&mac_eng); 1465 if (ret) 1466 return 1; 1467 1468 dump_setting(&mac_eng); 1469 1470 /* init PHY engine */ 1471 phy_eng.fp_set = NULL; 1472 phy_eng.fp_clr = NULL; 1473 1474 if (mac_eng.arg.ctrl.b.rmii_50m_out && 0 == mac_eng.run.is_rgmii) { 1475 mac_set_rmii_50m_output_enable(&mac_eng); 1476 } 1477 1478 push_reg(&mac_eng); 1479 disable_wdt(&mac_eng); 1480 1481 mac_set_addr(&mac_eng); 1482 if (mac_eng.arg.ctrl.b.mac_int_loopback) 1483 mac_set_interal_loopback(&mac_eng); 1484 1485 scu_set_pinmux(&mac_eng); 1486 1487 scu_disable_mac(&mac_eng); 1488 scu_enable_mac(&mac_eng); 1489 if (mac_eng.arg.run_mode == MODE_DEDICATED) { 1490 if (1 == phy_find_addr(&mac_eng)) { 1491 phy_select(&mac_eng, &phy_eng); 1492 } 1493 } 1494 1495 /* Data Initial */ 1496 setup_data(&mac_eng); 1497 1498 mac_eng.flg.all_fail = 1; 1499 mac_eng.io.init_done = 1; 1500 for(int i = 0; i < 3; i++) 1501 mac_eng.run.speed_sel[i] = mac_eng.run.speed_cfg[i]; 1502 1503 //------------------------------ 1504 // [Start] The loop of different speed 1505 //------------------------------ 1506 print_legend(); 1507 test_start(&mac_eng, &phy_eng); 1508 1509 return 0; 1510 } 1511