1 /* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11 //#define MAC_DEBUG_REGRW_MAC 12 //#define MAC_DEBUG_REGRW_PHY 13 //#define MAC_DEBUG_REGRW_SCU 14 //#define MAC_DEBUG_REGRW_WDT 15 //#define MAC_DEBUG_REGRW_SDR 16 //#define MAC_DEBUG_REGRW_SMB 17 //#define MAC_DEBUG_REGRW_TIMER 18 //#define MAC_DEBUG_REGRW_GPIO 19 //#define MAC_DEBUG_MEMRW_Dat 20 //#define MAC_DEBUG_MEMRW_Des 21 22 #define MAC_C 23 24 #include "swfunc.h" 25 26 #include "comminf.h" 27 #include <command.h> 28 #include <common.h> 29 #include <malloc.h> 30 #include "mem_io.h" 31 // ------------------------------------------------------------- 32 const uint32_t ARP_org_data[16] = { 33 0xffffffff, 34 0x0000ffff, // SA:00-00- 35 0x12345678, // SA:78-56-34-12 36 0x01000608, // ARP(0x0806) 37 0x04060008, 38 0x00000100, // sender MAC Address: 00 00 39 0x12345678, // sender MAC Address: 12 34 56 78 40 0xeb00a8c0, // sender IP Address: 192.168.0.235 (C0.A8.0.EB) 41 0x00000000, // target MAC Address: 00 00 00 00 42 0xa8c00000, // target MAC Address: 00 00, target IP Address:192.168 43 0x00005c00, // target IP Address: 0.92 (C0.A8.0.5C) 44 // 0x00000100, // target IP Address: 0.1 (C0.A8.0.1) 45 // 0x0000de00, // target IP Address: 0.222 (C0.A8.0.DE) 46 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc68e2bd5}; 47 48 //------------------------------------------------------------ 49 // Read Memory 50 //------------------------------------------------------------ 51 uint32_t Read_Mem_Dat_NCSI_DD(uint32_t addr) 52 { 53 #ifdef MAC_DEBUG_MEMRW_Dat 54 printf("[MEMRd-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( readl(addr) ) ); 55 #endif 56 return ( SWAP_4B_LEDN_MEM( readl(addr) ) ); 57 } 58 59 uint32_t Read_Mem_Des_NCSI_DD(uint32_t addr) 60 { 61 #ifdef MAC_DEBUG_MEMRW_Des 62 printf("[MEMRd-Des] %08x = %08x\n", addr, 63 SWAP_4B_LEDN_MEM(readl(addr))); 64 #endif 65 return (SWAP_4B_LEDN_MEM(readl(addr))); 66 } 67 68 uint32_t Read_Mem_Dat_DD(uint32_t addr) 69 { 70 #ifdef MAC_DEBUG_MEMRW_Dat 71 printf("[MEMRd-Dat] %08x = %08x\n", addr, 72 SWAP_4B_LEDN_MEM(readl(addr))); 73 #endif 74 return (SWAP_4B_LEDN_MEM(readl(addr))); 75 } 76 77 uint32_t Read_Mem_Des_DD(uint32_t addr) 78 { 79 #ifdef MAC_DEBUG_MEMRW_Des 80 printf("[MEMRd-Des] %08x = %08x\n", addr, 81 SWAP_4B_LEDN_MEM(readl(addr))); 82 #endif 83 return (SWAP_4B_LEDN_MEM(readl(addr))); 84 } 85 86 //------------------------------------------------------------ 87 // Read Register 88 //------------------------------------------------------------ 89 uint32_t mac_reg_read(MAC_ENGINE *p_eng, uint32_t addr) 90 { 91 return readl(p_eng->run.mac_base + addr); 92 } 93 94 //------------------------------------------------------------ 95 // Write Memory 96 //------------------------------------------------------------ 97 void Write_Mem_Dat_NCSI_DD (uint32_t addr, uint32_t data) { 98 #ifdef MAC_DEBUG_MEMRW_Dat 99 printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 100 #endif 101 writel(data, addr); 102 } 103 void Write_Mem_Des_NCSI_DD (uint32_t addr, uint32_t data) { 104 #ifdef MAC_DEBUG_MEMRW_Des 105 printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 106 #endif 107 writel(data, addr); 108 } 109 void Write_Mem_Dat_DD (uint32_t addr, uint32_t data) { 110 #ifdef MAC_DEBUG_MEMRW_Dat 111 printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 112 #endif 113 writel(data, addr); 114 } 115 void Write_Mem_Des_DD (uint32_t addr, uint32_t data) { 116 #ifdef MAC_DEBUG_MEMRW_Des 117 printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 118 #endif 119 writel(data, addr); 120 } 121 122 //------------------------------------------------------------ 123 // Write Register 124 //------------------------------------------------------------ 125 void mac_reg_write(MAC_ENGINE *p_eng, uint32_t addr, uint32_t data) 126 { 127 writel(data, p_eng->run.mac_base + addr); 128 } 129 130 131 //------------------------------------------------------------ 132 // Others 133 //------------------------------------------------------------ 134 void debug_pause (void) { 135 #ifdef DbgPrn_Enable_Debug_pause 136 GET_CAHR(); 137 #endif 138 } 139 140 //------------------------------------------------------------ 141 void dump_mac_ROreg(MAC_ENGINE *p_eng) 142 { 143 int i = 0xa0; 144 145 printf("\nMAC%d base 0x%08x", p_eng->run.mac_idx, p_eng->run.mac_base); 146 printf("\n%02x:", i); 147 for (i = 0xa0; i <= 0xc8; i += 4) { 148 printf("%08x ", mac_reg_read(p_eng, i)); 149 if ((i & 0xf) == 0xc) 150 printf("\n%02x:", i + 4); 151 } 152 printf("\n"); 153 } 154 155 //------------------------------------------------------------ 156 // IO delay 157 //------------------------------------------------------------ 158 static void get_mac_1g_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 159 { 160 int tx_d, rx_d; 161 mac_delay_1g_t reg; 162 163 reg.w = readl(addr); 164 tx_d = reg.b.tx_delay_1; 165 rx_d = reg.b.rx_delay_1; 166 #ifdef CONFIG_ASPEED_AST2600 167 if (reg.b.rx_clk_inv_1 == 1) { 168 rx_d = (-1) * rx_d; 169 } 170 #endif 171 *p_tx_d = tx_d; 172 *p_rx_d = rx_d; 173 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 174 rx_d, tx_d); 175 } 176 177 static void get_mac_1g_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 178 { 179 int tx_d, rx_d; 180 mac_delay_1g_t reg; 181 182 reg.w = readl(addr); 183 tx_d = reg.b.tx_delay_2; 184 rx_d = reg.b.rx_delay_2; 185 #ifdef CONFIG_ASPEED_AST2600 186 if (reg.b.rx_clk_inv_2 == 1) { 187 rx_d = (-1) * rx_d; 188 } 189 #endif 190 *p_tx_d = tx_d; 191 *p_rx_d = rx_d; 192 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 193 rx_d, tx_d); 194 } 195 196 static void get_mac_100_10_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 197 { 198 int tx_d, rx_d; 199 mac_delay_100_10_t reg; 200 201 reg.w = readl(addr); 202 tx_d = reg.b.tx_delay_1; 203 rx_d = reg.b.rx_delay_1; 204 #ifdef CONFIG_ASPEED_AST2600 205 if (reg.b.rx_clk_inv_1 == 1) { 206 rx_d = (-1) * rx_d; 207 } 208 #endif 209 *p_tx_d = tx_d; 210 *p_rx_d = rx_d; 211 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 212 rx_d, tx_d); 213 } 214 215 static void get_mac_100_10_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 216 { 217 int tx_d, rx_d; 218 mac_delay_100_10_t reg; 219 220 reg.w = readl(addr); 221 tx_d = reg.b.tx_delay_2; 222 rx_d = reg.b.rx_delay_2; 223 #ifdef CONFIG_ASPEED_AST2600 224 if (reg.b.rx_clk_inv_2 == 1) { 225 rx_d = (-1) * rx_d; 226 } 227 #endif 228 *p_tx_d = tx_d; 229 *p_rx_d = rx_d; 230 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 231 rx_d, tx_d); 232 } 233 234 static void get_mac_rmii_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 235 { 236 mac_delay_1g_t reg; 237 238 reg.w = readl(addr); 239 *p_rx_d = reg.b.rx_delay_1; 240 *p_tx_d = reg.b.rmii_tx_data_at_falling_1; 241 242 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 243 *p_rx_d, *p_tx_d); 244 } 245 static void get_mac_rmii_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 246 { 247 mac_delay_1g_t reg; 248 249 reg.w = readl(addr); 250 *p_rx_d = reg.b.rx_delay_2; 251 *p_tx_d = reg.b.rmii_tx_data_at_falling_2; 252 253 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 254 *p_rx_d, *p_tx_d); 255 } 256 257 static 258 void get_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 259 { 260 get_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 261 } 262 static 263 void get_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 264 { 265 get_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d); 266 } 267 static 268 void get_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 269 { 270 get_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d); 271 } 272 static 273 void get_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 274 { 275 get_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 276 } 277 static 278 void get_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 279 { 280 get_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d); 281 } 282 static 283 void get_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 284 { 285 get_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d); 286 } 287 static 288 void get_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 289 { 290 get_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 291 } 292 static 293 void get_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 294 { 295 get_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d); 296 } 297 static 298 void get_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 299 { 300 get_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d); 301 } 302 static 303 void get_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 304 { 305 get_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 306 } 307 static 308 void get_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 309 { 310 get_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d); 311 } 312 static 313 void get_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 314 { 315 get_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d); 316 } 317 static 318 void get_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 319 { 320 get_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 321 } 322 static 323 void get_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 324 { 325 get_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 326 } 327 static 328 void get_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 329 { 330 get_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 331 } 332 static 333 void get_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 334 { 335 get_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 336 } 337 static 338 void get_dummy_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 339 { 340 debug("%s\n", __func__); 341 } 342 343 /** 344 * @brief function pointer table to get current delay setting 345 * 346 * get_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m] 347 */ 348 typedef void (*pfn_get_delay) (MAC_ENGINE *, int32_t *, int32_t *); 349 pfn_get_delay get_delay_func_tbl[2][4][3] = { 350 { 351 {get_mac1_rmii_delay, get_mac1_rmii_delay, get_mac1_rmii_delay}, 352 {get_mac2_rmii_delay, get_mac2_rmii_delay, get_mac2_rmii_delay}, 353 #if defined(CONFIG_ASPEED_AST2600) 354 {get_mac3_rmii_delay, get_mac3_rmii_delay, get_mac3_rmii_delay}, 355 {get_mac4_rmii_delay, get_mac4_rmii_delay, get_mac4_rmii_delay}, 356 #else 357 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 358 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 359 #endif 360 }, 361 { 362 {get_mac1_1g_delay, get_mac1_100m_delay, get_mac1_10m_delay}, 363 {get_mac2_1g_delay, get_mac2_100m_delay, get_mac2_10m_delay}, 364 #if defined(CONFIG_ASPEED_AST2600) 365 {get_mac3_1g_delay, get_mac3_100m_delay, get_mac3_10m_delay}, 366 {get_mac4_1g_delay, get_mac4_100m_delay, get_mac4_10m_delay}, 367 #else 368 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 369 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 370 #endif 371 } 372 }; 373 void mac_get_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 374 { 375 #if 1 376 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 377 uint32_t mac_idx = p_eng->run.mac_idx; 378 uint32_t speed_idx = p_eng->run.speed_idx; 379 380 get_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, p_rx_d, p_tx_d); 381 #else 382 /* for test */ 383 uint32_t rgmii; 384 uint32_t mac_idx; 385 uint32_t speed_idx; 386 for (rgmii = 0; rgmii < 2; rgmii++) 387 for (mac_idx = 0; mac_idx < 4; mac_idx++) 388 for (speed_idx = 0; speed_idx < 3; speed_idx++) 389 get_delay_func_tbl[rgmii][mac_idx][speed_idx]( 390 p_eng, p_rx_d, p_tx_d); 391 #endif 392 } 393 394 void mac_get_max_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 395 { 396 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 397 uint32_t mac_idx = p_eng->run.mac_idx; 398 int32_t tx_max, rx_max; 399 400 if (rgmii) { 401 if (mac_idx > 1) { 402 tx_max = p_eng->io.mac34_1g_delay.tx_max; 403 rx_max = p_eng->io.mac34_1g_delay.rx_max; 404 } else { 405 tx_max = p_eng->io.mac12_1g_delay.tx_max; 406 rx_max = p_eng->io.mac12_1g_delay.rx_max; 407 } 408 } else { 409 if (mac_idx > 1) { 410 tx_max = p_eng->io.mac34_1g_delay.rmii_tx_max; 411 rx_max = p_eng->io.mac34_1g_delay.rmii_rx_max; 412 } else { 413 tx_max = p_eng->io.mac12_1g_delay.rmii_tx_max; 414 rx_max = p_eng->io.mac12_1g_delay.rmii_rx_max; 415 } 416 } 417 *p_tx_d = tx_max; 418 *p_rx_d = rx_max; 419 } 420 421 void mac_get_min_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 422 { 423 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 424 uint32_t mac_idx = p_eng->run.mac_idx; 425 int32_t tx_min, rx_min; 426 427 if (rgmii) { 428 if (mac_idx > 1) { 429 tx_min = p_eng->io.mac34_1g_delay.tx_min; 430 rx_min = p_eng->io.mac34_1g_delay.rx_min; 431 } else { 432 tx_min = p_eng->io.mac12_1g_delay.tx_min; 433 rx_min = p_eng->io.mac12_1g_delay.rx_min; 434 } 435 } else { 436 if (mac_idx > 1) { 437 tx_min = p_eng->io.mac34_1g_delay.rmii_tx_min; 438 rx_min = p_eng->io.mac34_1g_delay.rmii_rx_min; 439 } else { 440 tx_min = p_eng->io.mac12_1g_delay.rmii_tx_min; 441 rx_min = p_eng->io.mac12_1g_delay.rmii_rx_min; 442 } 443 } 444 *p_tx_d = tx_min; 445 *p_rx_d = rx_min; 446 } 447 448 static void set_mac_1g_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 449 { 450 mac_delay_1g_t reg; 451 452 reg.w = readl(addr); 453 #ifdef CONFIG_ASPEED_AST2600 454 if (rx_d < 0) { 455 reg.b.rx_clk_inv_1 = 1; 456 rx_d = abs(rx_d); 457 } 458 #endif 459 reg.b.rx_delay_1 = rx_d; 460 reg.b.tx_delay_1 = tx_d; 461 writel(reg.w, addr); 462 463 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 464 rx_d, tx_d); 465 } 466 467 static void set_mac_1g_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 468 { 469 mac_delay_1g_t reg; 470 471 reg.w = readl(addr); 472 #ifdef CONFIG_ASPEED_AST2600 473 if (rx_d < 0) { 474 reg.b.rx_clk_inv_2 = 1; 475 rx_d = abs(rx_d); 476 } 477 #endif 478 reg.b.rx_delay_2 = rx_d; 479 reg.b.tx_delay_2 = tx_d; 480 writel(reg.w, addr); 481 482 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 483 rx_d, tx_d); 484 } 485 486 static void set_mac_100_10_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 487 { 488 mac_delay_100_10_t reg; 489 490 reg.w = readl(addr); 491 #ifdef CONFIG_ASPEED_AST2600 492 if (rx_d < 0) { 493 reg.b.rx_clk_inv_1 = 1; 494 rx_d = abs(rx_d); 495 } 496 #endif 497 reg.b.rx_delay_1 = rx_d; 498 reg.b.tx_delay_1 = tx_d; 499 writel(reg.w, addr); 500 501 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 502 rx_d, tx_d); 503 } 504 505 static void set_mac_100_10_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 506 { 507 mac_delay_100_10_t reg; 508 509 reg.w = readl(addr); 510 #ifdef CONFIG_ASPEED_AST2600 511 if (rx_d < 0) { 512 reg.b.rx_clk_inv_2 = 1; 513 rx_d = abs(rx_d); 514 } 515 #endif 516 reg.b.rx_delay_2 = rx_d; 517 reg.b.tx_delay_2 = tx_d; 518 writel(reg.w, addr); 519 520 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 521 rx_d, tx_d); 522 } 523 524 static void set_mac_rmii_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 525 { 526 mac_delay_1g_t reg; 527 528 reg.w = readl(addr); 529 reg.b.rmii_tx_data_at_falling_1 = tx_d; 530 reg.b.rx_delay_1 = rx_d; 531 writel(reg.w, addr); 532 533 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 534 rx_d, tx_d); 535 } 536 537 static void set_mac_rmii_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 538 { 539 mac_delay_1g_t reg; 540 541 reg.w = readl(addr); 542 reg.b.rmii_tx_data_at_falling_2 = tx_d; 543 reg.b.rx_delay_2 = rx_d; 544 writel(reg.w, addr); 545 546 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 547 rx_d, tx_d); 548 } 549 550 551 static void set_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 552 { 553 set_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 554 } 555 static void set_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 556 { 557 set_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d); 558 } 559 static void set_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 560 { 561 set_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d); 562 } 563 static void set_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 564 { 565 set_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 566 } 567 static void set_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 568 { 569 set_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d); 570 } 571 static void set_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 572 { 573 set_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d); 574 } 575 static void set_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 576 { 577 set_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 578 } 579 static void set_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 580 { 581 set_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d); 582 } 583 static void set_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 584 { 585 set_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d); 586 } 587 static void set_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 588 { 589 set_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 590 } 591 static void set_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 592 { 593 set_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d); 594 } 595 static void set_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 596 { 597 set_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d); 598 } 599 static void set_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 600 { 601 set_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 602 } 603 static void set_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 604 { 605 set_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 606 } 607 608 static void set_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 609 { 610 set_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 611 } 612 613 static void set_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 614 { 615 set_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 616 } 617 618 void set_dummy_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 619 { 620 printf("%s: %d, %d\n", __func__, rx_d, tx_d); 621 } 622 623 /** 624 * @brief function pointer table for delay setting 625 * 626 * set_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m] 627 */ 628 typedef void (*pfn_set_delay) (MAC_ENGINE *, int32_t, int32_t); 629 pfn_set_delay set_delay_func_tbl[2][4][3] = { 630 { 631 {set_mac1_rmii_delay, set_mac1_rmii_delay, set_mac1_rmii_delay}, 632 {set_mac2_rmii_delay, set_mac2_rmii_delay, set_mac2_rmii_delay}, 633 #if defined(CONFIG_ASPEED_AST2600) 634 {set_mac3_rmii_delay, set_mac3_rmii_delay, set_mac3_rmii_delay}, 635 {set_mac4_rmii_delay, set_mac4_rmii_delay, set_mac4_rmii_delay}, 636 #else 637 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 638 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 639 #endif 640 }, 641 { 642 {set_mac1_1g_delay, set_mac1_100m_delay, set_mac1_10m_delay}, 643 {set_mac2_1g_delay, set_mac2_100m_delay, set_mac2_10m_delay}, 644 #if defined(CONFIG_ASPEED_AST2600) 645 {set_mac3_1g_delay, set_mac3_100m_delay, set_mac3_10m_delay}, 646 {set_mac4_1g_delay, set_mac4_100m_delay, set_mac4_10m_delay}, 647 #else 648 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 649 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 650 #endif 651 } 652 }; 653 654 void mac_set_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 655 { 656 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 657 uint32_t mac_idx = p_eng->run.mac_idx; 658 uint32_t speed_idx = p_eng->run.speed_idx; 659 660 set_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, rx_d, tx_d); 661 } 662 663 uint32_t mac_get_driving_strength(MAC_ENGINE *p_eng) 664 { 665 #ifdef CONFIG_ASPEED_AST2600 666 mac34_drv_t reg; 667 668 reg.w = readl(p_eng->io.mac34_drv_reg.addr); 669 /* ast2600 : only MAC#3 & MAC#4 have driving strength setting */ 670 if (p_eng->run.mac_idx == 2) { 671 return (reg.b.mac3_tx_drv); 672 } else if (p_eng->run.mac_idx == 3) { 673 return (reg.b.mac4_tx_drv); 674 } else { 675 return 0; 676 } 677 #else 678 mac12_drv_t reg; 679 680 reg.w = readl(p_eng->io.mac12_drv_reg.addr); 681 682 if (p_eng->run.mac_idx == 0) { 683 return (reg.b.mac1_tx_drv); 684 } else if (p_eng->run.mac_idx == 1) { 685 return (reg.b.mac2_tx_drv); 686 } else { 687 return 0; 688 } 689 #endif 690 } 691 void mac_set_driving_strength(MAC_ENGINE *p_eng, uint32_t strength) 692 { 693 #ifdef CONFIG_ASPEED_AST2600 694 mac34_drv_t reg; 695 696 if (strength > p_eng->io.mac34_drv_reg.drv_max) { 697 printf("invalid driving strength value\n"); 698 return; 699 } 700 701 /** 702 * read->modify->write for driving strength control register 703 * ast2600 : only MAC#3 & MAC#4 have driving strength setting 704 */ 705 reg.w = readl(p_eng->io.mac34_drv_reg.addr); 706 707 /* ast2600 : only MAC#3 & MAC#4 have driving strength setting */ 708 if (p_eng->run.mac_idx == 2) { 709 reg.b.mac3_tx_drv = strength; 710 } else if (p_eng->run.mac_idx == 3) { 711 reg.b.mac4_tx_drv = strength; 712 } 713 714 writel(reg.w, p_eng->io.mac34_drv_reg.addr); 715 #else 716 mac12_drv_t reg; 717 718 if (strength > p_eng->io.mac12_drv_reg.drv_max) { 719 printf("invalid driving strength value\n"); 720 return; 721 } 722 723 /* read->modify->write for driving strength control register */ 724 reg.w = readl(p_eng->io.mac12_drv_reg.addr); 725 if (p_eng->run.is_rgmii) { 726 if (p_eng->run.mac_idx == 0) { 727 reg.b.mac1_rgmii_tx_drv = 728 strength; 729 } else if (p_eng->run.mac_idx == 2) { 730 reg.b.mac2_rgmii_tx_drv = 731 strength; 732 } 733 } else { 734 if (p_eng->run.mac_idx == 0) { 735 reg.b.mac1_rmii_tx_drv = 736 strength; 737 } else if (p_eng->run.mac_idx == 1) { 738 reg.b.mac2_rmii_tx_drv = 739 strength; 740 } 741 } 742 writel(reg.w, p_eng->io.mac12_drv_reg.addr); 743 #endif 744 } 745 746 void mac_set_rmii_50m_output_enable(MAC_ENGINE *p_eng) 747 { 748 uint32_t addr; 749 mac_delay_1g_t value; 750 751 if (p_eng->run.mac_idx > 1) { 752 addr = p_eng->io.mac34_1g_delay.addr; 753 } else { 754 addr = p_eng->io.mac12_1g_delay.addr; 755 } 756 757 value.w = readl(addr); 758 if (p_eng->run.mac_idx & BIT(0)) { 759 value.b.rmii_50m_oe_2 = 1; 760 } else { 761 value.b.rmii_50m_oe_1 = 1; 762 } 763 writel(value.w, addr); 764 } 765 766 //------------------------------------------------------------ 767 int mac_set_scan_boundary(MAC_ENGINE *p_eng) 768 { 769 int32_t rx_cur, tx_cur; 770 int32_t rx_min, rx_max, tx_min, tx_max; 771 int32_t rx_scaling, tx_scaling; 772 773 nt_log_func_name(); 774 775 /* get current delay setting */ 776 mac_get_delay(p_eng, &rx_cur, &tx_cur); 777 778 /* get physical boundaries */ 779 mac_get_max_available_delay(p_eng, &rx_max, &tx_max); 780 mac_get_min_available_delay(p_eng, &rx_min, &tx_min); 781 782 if ((p_eng->run.is_rgmii) && (p_eng->arg.ctrl.b.inv_rgmii_rxclk)) { 783 rx_max = (rx_max > 0) ? 0 : rx_max; 784 } else { 785 rx_min = (rx_min < 0) ? 0 : rx_min; 786 } 787 788 if (p_eng->run.TM_IOTiming) { 789 if (p_eng->arg.ctrl.b.full_range) { 790 tx_scaling = 0; 791 rx_scaling = 0; 792 } else { 793 /* down-scaling to save test time */ 794 tx_scaling = TX_DELAY_SCALING; 795 rx_scaling = RX_DELAY_SCALING; 796 } 797 p_eng->io.rx_delay_scan.step = 1; 798 p_eng->io.tx_delay_scan.step = 1; 799 p_eng->io.rx_delay_scan.begin = rx_min >> rx_scaling; 800 p_eng->io.rx_delay_scan.end = rx_max >> rx_scaling; 801 p_eng->io.tx_delay_scan.begin = tx_min >> tx_scaling; 802 p_eng->io.tx_delay_scan.end = tx_max >> tx_scaling; 803 } else if (p_eng->run.delay_margin) { 804 p_eng->io.rx_delay_scan.step = 1; 805 p_eng->io.tx_delay_scan.step = 1; 806 p_eng->io.rx_delay_scan.begin = rx_cur - p_eng->run.delay_margin; 807 p_eng->io.rx_delay_scan.end = rx_cur + p_eng->run.delay_margin; 808 p_eng->io.tx_delay_scan.begin = tx_cur - p_eng->run.delay_margin; 809 p_eng->io.tx_delay_scan.end = tx_cur + p_eng->run.delay_margin; 810 } else { 811 p_eng->io.rx_delay_scan.step = 1; 812 p_eng->io.tx_delay_scan.step = 1; 813 p_eng->io.rx_delay_scan.begin = 0; 814 p_eng->io.rx_delay_scan.end = 0; 815 p_eng->io.tx_delay_scan.begin = 0; 816 p_eng->io.tx_delay_scan.end = 0; 817 } 818 819 /* backup current setting as the original for plotting result */ 820 p_eng->io.rx_delay_scan.orig = rx_cur; 821 p_eng->io.tx_delay_scan.orig = tx_cur; 822 823 /* check if setting is legal or not */ 824 if (p_eng->io.rx_delay_scan.begin < rx_min) 825 p_eng->io.rx_delay_scan.begin = rx_min; 826 827 if (p_eng->io.tx_delay_scan.begin < tx_min) 828 p_eng->io.tx_delay_scan.begin = tx_min; 829 830 if (p_eng->io.rx_delay_scan.end > rx_max) 831 p_eng->io.rx_delay_scan.end = rx_max; 832 833 if (p_eng->io.tx_delay_scan.end > tx_max) 834 p_eng->io.tx_delay_scan.end = tx_max; 835 836 if (p_eng->io.rx_delay_scan.begin > p_eng->io.rx_delay_scan.end) 837 p_eng->io.rx_delay_scan.begin = p_eng->io.rx_delay_scan.end; 838 839 if (p_eng->io.tx_delay_scan.begin > p_eng->io.tx_delay_scan.end) 840 p_eng->io.tx_delay_scan.begin = p_eng->io.tx_delay_scan.end; 841 842 if (p_eng->run.IO_MrgChk) { 843 if ((p_eng->io.rx_delay_scan.orig < 844 p_eng->io.rx_delay_scan.begin) || 845 (p_eng->io.rx_delay_scan.orig > 846 p_eng->io.rx_delay_scan.end)) { 847 printf("Warning: current delay is not in the " 848 "scan-range\n"); 849 printf("RX delay scan range:%d ~ %d, curr:%d\n", 850 p_eng->io.rx_delay_scan.begin, 851 p_eng->io.rx_delay_scan.end, 852 p_eng->io.rx_delay_scan.orig); 853 printf("TX delay scan range:%d ~ %d, curr:%d\n", 854 p_eng->io.tx_delay_scan.begin, 855 p_eng->io.tx_delay_scan.end, 856 p_eng->io.tx_delay_scan.orig); 857 } 858 } 859 860 return (0); 861 } 862 863 //------------------------------------------------------------ 864 // MAC 865 //------------------------------------------------------------ 866 void mac_set_addr(MAC_ENGINE *p_eng) 867 { 868 nt_log_func_name(); 869 870 uint32_t madr = p_eng->reg.mac_madr; 871 uint32_t ladr = p_eng->reg.mac_ladr; 872 873 if (((madr == 0x0000) && (ladr == 0x00000000)) || 874 ((madr == 0xffff) && (ladr == 0xffffffff))) { 875 /* FIXME: shall use random gen */ 876 madr = 0x0000000a; 877 ladr = 0xf7837dd4; 878 } 879 880 p_eng->inf.SA[0] = (madr >> 8) & 0xff; // MSB 881 p_eng->inf.SA[1] = (madr >> 0) & 0xff; 882 p_eng->inf.SA[2] = (ladr >> 24) & 0xff; 883 p_eng->inf.SA[3] = (ladr >> 16) & 0xff; 884 p_eng->inf.SA[4] = (ladr >> 8) & 0xff; 885 p_eng->inf.SA[5] = (ladr >> 0) & 0xff; // LSB 886 } 887 888 void mac_set_interal_loopback(MAC_ENGINE *p_eng) 889 { 890 uint32_t reg = mac_reg_read(p_eng, 0x40); 891 mac_reg_write(p_eng, 0x40, reg | BIT(30)); 892 } 893 894 //------------------------------------------------------------ 895 void init_mac (MAC_ENGINE *eng) 896 { 897 nt_log_func_name(); 898 899 mac_cr_t maccr; 900 901 #ifdef Enable_MAC_SWRst 902 maccr.w = 0; 903 maccr.b.sw_rst = 1; 904 mac_reg_write(eng, 0x50, maccr.w); 905 906 do { 907 DELAY(Delay_MACRst); 908 maccr.w = mac_reg_read(eng, 0x50); 909 } while(maccr.b.sw_rst); 910 #endif 911 912 mac_reg_write(eng, 0x20, eng->run.tdes_base - ASPEED_DRAM_BASE); 913 mac_reg_write(eng, 0x24, eng->run.rdes_base - ASPEED_DRAM_BASE); 914 915 mac_reg_write(eng, 0x08, eng->reg.mac_madr); 916 mac_reg_write(eng, 0x0c, eng->reg.mac_ladr); 917 918 #ifdef MAC_030_def 919 mac_reg_write( eng, 0x30, MAC_030_def );//Int Thr/Cnt 920 #endif 921 #ifdef MAC_034_def 922 mac_reg_write( eng, 0x34, MAC_034_def );//Poll Cnt 923 #endif 924 #ifdef MAC_038_def 925 mac_reg_write( eng, 0x38, MAC_038_def ); 926 #endif 927 #ifdef MAC_048_def 928 mac_reg_write( eng, 0x48, MAC_048_def ); 929 #endif 930 #ifdef MAC_058_def 931 mac_reg_write( eng, 0x58, MAC_058_def ); 932 #endif 933 934 if ( eng->arg.run_mode == MODE_NCSI ) 935 mac_reg_write( eng, 0x4c, NCSI_RxDMA_PakSize ); 936 else 937 mac_reg_write( eng, 0x4c, DMA_PakSize ); 938 939 maccr.b.txdma_en = 1; 940 maccr.b.rxdma_en = 1; 941 maccr.b.txmac_en = 1; 942 maccr.b.rxmac_en = 1; 943 maccr.b.fulldup = 1; 944 maccr.b.crc_apd = 1; 945 946 if (eng->run.speed_sel[0]) { 947 maccr.b.gmac_mode = 1; 948 } else if (eng->run.speed_sel[1]) { 949 maccr.b.speed_100 = 1; 950 } 951 952 if (eng->arg.run_mode == MODE_NCSI) { 953 maccr.b.rx_broadpkt_en = 1; 954 maccr.b.speed_100 = 1; 955 } 956 else { 957 maccr.b.rx_alladr = 1; 958 #ifdef Enable_Runt 959 maccr.b.rx_runt = 1; 960 #endif 961 } 962 mac_reg_write(eng, 0x50, maccr.w); 963 DELAY(Delay_MACRst); 964 } // End void init_mac (MAC_ENGINE *eng) 965 966 //------------------------------------------------------------ 967 // Basic 968 //------------------------------------------------------------ 969 void FPri_RegValue (MAC_ENGINE *eng, uint8_t option) 970 { 971 nt_log_func_name(); 972 973 PRINTF( option, "[SRAM] Date:%08x\n", SRAM_RD( 0x88 ) ); 974 PRINTF( option, "[SRAM] 80:%08x %08x %08x %08x\n", SRAM_RD( 0x80 ), SRAM_RD( 0x84 ), SRAM_RD( 0x88 ), SRAM_RD( 0x8c ) ); 975 976 PRINTF( option, "[SCU] a0:%08x a4:%08x b8:%08x bc:%08x\n", SCU_RD( 0x0a0 ), SCU_RD( 0x0a4 ), SCU_RD( 0x0b8 ), SCU_RD( 0x0bc )); 977 978 PRINTF( option, "[SCU] 13c:%08x 140:%08x 144:%08x 1dc:%08x\n", SCU_RD( 0x13c ), SCU_RD( 0x140 ), SCU_RD( 0x144 ), SCU_RD( 0x1dc ) ); 979 PRINTF( option, "[WDT] 0c:%08x 2c:%08x 4c:%08x\n", eng->reg.WDT_00c, eng->reg.WDT_02c, eng->reg.WDT_04c ); 980 PRINTF( option, "[MAC] A0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xa0 ), mac_reg_read( eng, 0xa4 ), mac_reg_read( eng, 0xa8 ), mac_reg_read( eng, 0xac ) ); 981 PRINTF( option, "[MAC] B0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xb0 ), mac_reg_read( eng, 0xb4 ), mac_reg_read( eng, 0xb8 ), mac_reg_read( eng, 0xbc ) ); 982 PRINTF( option, "[MAC] C0|%08x %08x %08x\n", mac_reg_read( eng, 0xc0 ), mac_reg_read( eng, 0xc4 ), mac_reg_read( eng, 0xc8 ) ); 983 984 } // End void FPri_RegValue (MAC_ENGINE *eng, uint8_t *fp) 985 986 //------------------------------------------------------------ 987 void FPri_End (MAC_ENGINE *eng, uint8_t option) 988 { 989 nt_log_func_name(); 990 if ((0 == eng->run.is_rgmii) && (eng->phy.RMIICK_IOMode != 0) && 991 eng->run.IO_MrgChk && eng->flg.all_fail) { 992 if ( eng->arg.ctrl.b.rmii_phy_in == 0 ) { 993 PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the OUTPUT mode now.\n" ); 994 PRINTF( option, " Maybe you can run the INPUT mode command \"mactest %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w | 0x80), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range ); 995 } 996 else { 997 PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the INPUT mode now.\n" ); 998 PRINTF( option, " Maybe you can run the OUTPUT mode command \"mactest %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w & 0x7f), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range ); 999 } 1000 } 1001 1002 if (!eng->run.TM_RxDataEn) { 1003 } else if (eng->flg.Err_Flag) { 1004 PRINTF(option, " \n----> fail !!!\n"); 1005 } 1006 1007 //------------------------------ 1008 //[Warning] PHY Address 1009 //------------------------------ 1010 if ( eng->arg.run_mode == MODE_DEDICATED ) { 1011 if ( eng->arg.phy_addr != eng->phy.Adr ) 1012 PRINTF( option, "\n[Warning] PHY Address change from %d to %d !!!\n", eng->arg.phy_addr, eng->phy.Adr ); 1013 } 1014 1015 //------------------------------ 1016 //[Warning] IO Strength 1017 //------------------------------ 1018 #ifdef CONFIG_ASPEED_AST2600 1019 if (eng->io.init_done && (eng->io.mac34_drv_reg.value.w != 0xf)) { 1020 PRINTF(option, 1021 "\n[Warning] [%08X] 0x%08x is not the suggestion value " 1022 "0xf.\n", 1023 eng->io.mac34_drv_reg.addr, 1024 eng->io.mac34_drv_reg.value.w); 1025 #else 1026 if (eng->io.init_done && eng->io.mac12_drv_reg.value.w) { 1027 PRINTF(option, 1028 "\n[Warning] [%08X] 0x%08x is not the suggestion value " 1029 "0.\n", 1030 eng->io.mac12_drv_reg.addr, 1031 eng->io.mac12_drv_reg.value.w); 1032 #endif 1033 PRINTF(option, " This change at this platform must " 1034 "been proven again by the ASPEED.\n"); 1035 } 1036 1037 //------------------------------ 1038 //[Warning] IO Timing 1039 //------------------------------ 1040 if ( eng->arg.run_mode == MODE_NCSI ) { 1041 PRINTF( option, "\n[Arg] %d %d %d %d %d %d %d {%d}\n", eng->arg.mac_idx, eng->arg.GPackageTolNum, eng->arg.GChannelTolNum, eng->arg.test_mode, eng->arg.delay_scan_range, eng->arg.ctrl.w, eng->arg.GARPNumCnt, TIME_OUT_NCSI ); 1042 1043 switch ( eng->ncsi_cap.PCI_DID_VID ) { 1044 case PCI_DID_VID_Intel_82574L : { PRINTF( option, "[NC]%08x %08x: Intel 82574L \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1045 case PCI_DID_VID_Intel_82575_10d6 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1046 case PCI_DID_VID_Intel_82575_10a7 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1047 case PCI_DID_VID_Intel_82575_10a9 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1048 case PCI_DID_VID_Intel_82576_10c9 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1049 case PCI_DID_VID_Intel_82576_10e6 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1050 case PCI_DID_VID_Intel_82576_10e7 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1051 case PCI_DID_VID_Intel_82576_10e8 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1052 case PCI_DID_VID_Intel_82576_1518 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1053 case PCI_DID_VID_Intel_82576_1526 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1054 case PCI_DID_VID_Intel_82576_150a : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1055 case PCI_DID_VID_Intel_82576_150d : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1056 case PCI_DID_VID_Intel_82599_10fb : { PRINTF( option, "[NC]%08x %08x: Intel 82599 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1057 case PCI_DID_VID_Intel_82599_1557 : { PRINTF( option, "[NC]%08x %08x: Intel 82599 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1058 case PCI_DID_VID_Intel_I210_1533 : { PRINTF( option, "[NC]%08x %08x: Intel I210 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1059 case PCI_DID_VID_Intel_I210_1537 : { PRINTF( option, "[NC]%08x %08x: Intel I210 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1060 case PCI_DID_VID_Intel_I350_1521 : { PRINTF( option, "[NC]%08x %08x: Intel I350 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1061 case PCI_DID_VID_Intel_I350_1523 : { PRINTF( option, "[NC]%08x %08x: Intel I350 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1062 case PCI_DID_VID_Intel_X540 : { PRINTF( option, "[NC]%08x %08x: Intel X540 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1063 case PCI_DID_VID_Intel_X550 : { PRINTF( option, "[NC]%08x %08x: Intel X550 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1064 case PCI_DID_VID_Intel_Broadwell_DE : { PRINTF( option, "[NC]%08x %08x: Intel Broadwell-DE \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1065 case PCI_DID_VID_Intel_X722_37d0 : { PRINTF( option, "[NC]%08x %08x: Intel X722 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1066 case PCI_DID_VID_Broadcom_BCM5718 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5718 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1067 case PCI_DID_VID_Broadcom_BCM5719 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5719 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1068 case PCI_DID_VID_Broadcom_BCM5720 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5720 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1069 case PCI_DID_VID_Broadcom_BCM5725 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5725 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1070 case PCI_DID_VID_Broadcom_BCM57810S : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57810S \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1071 case PCI_DID_VID_Broadcom_Cumulus : { PRINTF( option, "[NC]%08x %08x: Broadcom Cumulus \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1072 case PCI_DID_VID_Broadcom_BCM57302 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57302 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1073 case PCI_DID_VID_Broadcom_BCM957452 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM957452 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1074 case PCI_DID_VID_Mellanox_ConnectX_3_1003 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1075 case PCI_DID_VID_Mellanox_ConnectX_3_1007 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1076 case PCI_DID_VID_Mellanox_ConnectX_4 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-4\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1077 default: 1078 switch ( eng->ncsi_cap.manufacturer_id ) { 1079 case ManufacturerID_Intel : { PRINTF( option, "[NC]%08x %08x: Intel \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1080 case ManufacturerID_Broadcom : { PRINTF( option, "[NC]%08x %08x: Broadcom \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1081 case ManufacturerID_Mellanox : { PRINTF( option, "[NC]%08x %08x: Mellanox \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1082 case ManufacturerID_Mellanox1: { PRINTF( option, "[NC]%08x %08x: Mellanox \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1083 case ManufacturerID_Emulex : { PRINTF( option, "[NC]%08x %08x: Emulex \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1084 default : { PRINTF( option, "[NC]%08x %08x \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1085 } // End switch ( eng->ncsi_cap.manufacturer_id ) 1086 } // End switch ( eng->ncsi_cap.PCI_DID_VID ) 1087 } 1088 else { 1089 PRINTF( option, "[PHY] Adr:%d ID2:%04x ID3:%04x (%s)\n", eng->phy.Adr, eng->phy.PHY_ID2, eng->phy.PHY_ID3, eng->phy.phy_name); 1090 } // End if ( eng->arg.run_mode == MODE_NCSI ) 1091 } // End void FPri_End (MAC_ENGINE *eng, uint8_t option) 1092 1093 //------------------------------------------------------------ 1094 void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option) 1095 { 1096 nt_log_func_name(); 1097 if ( eng->flg.print_en ) { 1098 if ( eng->flg.Wrn_Flag ) { 1099 if ( eng->flg.Wrn_Flag & Wrn_Flag_IOMarginOUF ) { 1100 PRINTF(option, "[Warning] IO timing testing " 1101 "range out of boundary\n"); 1102 1103 if (0 == eng->run.is_rgmii) { 1104 PRINTF( option, " (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx, 1105 eng->io.Dly_out_reg_idx, 1106 eng->run.delay_margin, 1107 eng->io.Dly_in_min, 1108 eng->io.Dly_in_max, 1109 eng->io.Dly_out_min ); 1110 } 1111 else { 1112 PRINTF( option, " (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx, 1113 eng->io.Dly_out_reg_idx, 1114 eng->run.delay_margin, 1115 eng->run.delay_margin, 1116 eng->io.Dly_in_min, 1117 eng->io.Dly_in_max, 1118 eng->io.Dly_out_min, 1119 eng->io.Dly_out_max ); 1120 } 1121 } // End if ( eng->flg.Wrn_Flag & Wrn_Flag_IOMarginOUF ) 1122 if ( eng->flg.Wrn_Flag & Wrn_Flag_RxErFloatting ) { 1123 PRINTF( option, "[Warning] NCSI RXER pin may be floatting to the MAC !!!\n" ); 1124 PRINTF( option, " Please contact with the ASPEED Inc. for more help.\n" ); 1125 } // End if ( eng->flg.Wrn_Flag & Wrn_Flag_RxErFloatting ) 1126 } // End if ( eng->flg.Wrn_Flag ) 1127 1128 if ( eng->flg.Err_Flag ) { 1129 PRINTF( option, "\n\n" ); 1130 //PRINTF( option, "Err_Flag: %x\n\n", eng->flg.Err_Flag ); 1131 1132 if ( eng->flg.Err_Flag & Err_Flag_PHY_Type ) { PRINTF( option, "[Err] Unidentifiable PHY \n" ); } 1133 if ( eng->flg.Err_Flag & Err_Flag_MALLOC_FrmSize ) { PRINTF( option, "[Err] Malloc fail at frame size buffer \n" ); } 1134 if ( eng->flg.Err_Flag & Err_Flag_MALLOC_LastWP ) { PRINTF( option, "[Err] Malloc fail at last WP buffer \n" ); } 1135 if ( eng->flg.Err_Flag & Err_Flag_Check_Buf_Data ) { PRINTF( option, "[Err] Received data mismatch \n" ); } 1136 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Check_TxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Tx owner bit in NCSI packet \n" ); } 1137 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Check_RxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Rx owner bit in NCSI packet \n" ); } 1138 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Check_ARPOwnTimeOut) { PRINTF( option, "[Err] Time out of checking ARP owner bit in NCSI packet \n" ); } 1139 if ( eng->flg.Err_Flag & Err_Flag_NCSI_No_PHY ) { PRINTF( option, "[Err] Can not find NCSI PHY \n" ); } 1140 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[Err] NCSI Channel Number Mismatch \n" ); } 1141 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[Err] NCSI Package Number Mismatch \n" ); } 1142 if ( eng->flg.Err_Flag & Err_Flag_PHY_TimeOut_RW ) { PRINTF( option, "[Err] Time out of read/write PHY register \n" ); } 1143 if ( eng->flg.Err_Flag & Err_Flag_PHY_TimeOut_Rst ) { PRINTF( option, "[Err] Time out of reset PHY register \n" ); } 1144 if ( eng->flg.Err_Flag & Err_Flag_RXBUF_UNAVA ) { PRINTF( option, "[Err] MAC00h[2]:Receiving buffer unavailable \n" ); } 1145 if ( eng->flg.Err_Flag & Err_Flag_RPKT_LOST ) { PRINTF( option, "[Err] MAC00h[3]:Received packet lost due to RX FIFO full \n" ); } 1146 if ( eng->flg.Err_Flag & Err_Flag_NPTXBUF_UNAVA ) { PRINTF( option, "[Err] MAC00h[6]:Normal priority transmit buffer unavailable \n" ); } 1147 if ( eng->flg.Err_Flag & Err_Flag_TPKT_LOST ) { PRINTF( option, "[Err] MAC00h[7]:Packets transmitted to Ethernet lost \n" ); } 1148 if ( eng->flg.Err_Flag & Err_Flag_DMABufNum ) { PRINTF( option, "[Err] DMA Buffer is not enough \n" ); } 1149 if ( eng->flg.Err_Flag & Err_Flag_IOMargin ) { PRINTF( option, "[Err] IO timing margin is not enough \n" ); } 1150 1151 if ( eng->flg.Err_Flag & Err_Flag_MHCLK_Ratio ) { 1152 PRINTF( option, "[Err] Error setting of MAC AHB bus clock (SCU08[18:16]) \n" ); 1153 if ( eng->env.at_least_1g_valid ) 1154 { PRINTF( option, " SCU08[18:16] == 0x%01x is not the suggestion value 2.\n", eng->env.MHCLK_Ratio ); } 1155 else 1156 { PRINTF( option, " SCU08[18:16] == 0x%01x is not the suggestion value 4.\n", eng->env.MHCLK_Ratio ); } 1157 } // End if ( eng->flg.Err_Flag & Err_Flag_MHCLK_Ratio ) 1158 1159 if ( eng->flg.Err_Flag & Err_Flag_IOMarginOUF ) { 1160 PRINTF( option, "[Err] IO timing testing range out of boundary\n"); 1161 if (0 == eng->run.is_rgmii) { 1162 PRINTF( option, " (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx, 1163 eng->io.Dly_out_reg_idx, 1164 eng->run.delay_margin, 1165 eng->io.Dly_in_min, 1166 eng->io.Dly_in_max, 1167 eng->io.Dly_out_min ); 1168 } 1169 else { 1170 PRINTF( option, " (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx, 1171 eng->io.Dly_out_reg_idx, 1172 eng->run.delay_margin, 1173 eng->run.delay_margin, 1174 eng->io.Dly_in_min, 1175 eng->io.Dly_in_max, 1176 eng->io.Dly_out_min, 1177 eng->io.Dly_out_max ); 1178 } 1179 } // End if ( eng->flg.Err_Flag & Err_Flag_IOMarginOUF ) 1180 1181 if ( eng->flg.Err_Flag & Err_Flag_Check_Des ) { 1182 PRINTF( option, "[Err] Descriptor error\n"); 1183 if ( eng->flg.Des_Flag & Des_Flag_TxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Tx owner bit\n" ); } 1184 if ( eng->flg.Des_Flag & Des_Flag_RxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Rx owner bit\n" ); } 1185 if ( eng->flg.Des_Flag & Des_Flag_FrameLen ) { PRINTF( option, "[Des] Frame length mismatch \n" ); } 1186 if ( eng->flg.Des_Flag & Des_Flag_RxErr ) { PRINTF( option, "[Des] Input signal RxErr \n" ); } 1187 if ( eng->flg.Des_Flag & Des_Flag_CRC ) { PRINTF( option, "[Des] CRC error of frame \n" ); } 1188 if ( eng->flg.Des_Flag & Des_Flag_FTL ) { PRINTF( option, "[Des] Frame too long \n" ); } 1189 if ( eng->flg.Des_Flag & Des_Flag_Runt ) { PRINTF( option, "[Des] Runt packet \n" ); } 1190 if ( eng->flg.Des_Flag & Des_Flag_OddNibble ) { PRINTF( option, "[Des] Nibble bit happen \n" ); } 1191 if ( eng->flg.Des_Flag & Des_Flag_RxFIFOFull ) { PRINTF( option, "[Des] Rx FIFO full \n" ); } 1192 } // End if ( eng->flg.Err_Flag & Err_Flag_Check_Des ) 1193 1194 if ( eng->flg.Err_Flag & Err_Flag_MACMode ) { 1195 PRINTF( option, "[Err] MAC interface mode mismatch\n" ); 1196 for (int i = 0; i < 4; i++) { 1197 if (eng->env.is_1g_valid[i]) { 1198 PRINTF(option, 1199 "[MAC%d] is RGMII\n", i); 1200 } else { 1201 PRINTF(option, 1202 "[MAC%d] RMII\n", i); 1203 } 1204 } 1205 } // End if ( eng->flg.Err_Flag & Err_Flag_MACMode ) 1206 1207 if ( eng->arg.run_mode == MODE_NCSI ) { 1208 if ( eng->flg.Err_Flag & Err_Flag_NCSI_LinkFail ) { 1209 PRINTF( option, "[Err] NCSI packet retry number over flows when find channel\n" ); 1210 1211 if ( eng->flg.NCSI_Flag & NCSI_Flag_Get_Version_ID ) { PRINTF( option, "[NCSI] Time out when Get Version ID \n" ); } 1212 if ( eng->flg.NCSI_Flag & NCSI_Flag_Get_Capabilities ) { PRINTF( option, "[NCSI] Time out when Get Capabilities \n" ); } 1213 if ( eng->flg.NCSI_Flag & NCSI_Flag_Select_Active_Package ) { PRINTF( option, "[NCSI] Time out when Select Active Package \n" ); } 1214 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Set_MAC_Address ) { PRINTF( option, "[NCSI] Time out when Enable Set MAC Address \n" ); } 1215 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Broadcast_Filter ) { PRINTF( option, "[NCSI] Time out when Enable Broadcast Filter \n" ); } 1216 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Network_TX ) { PRINTF( option, "[NCSI] Time out when Enable Network TX \n" ); } 1217 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Channel ) { PRINTF( option, "[NCSI] Time out when Enable Channel \n" ); } 1218 if ( eng->flg.NCSI_Flag & NCSI_Flag_Disable_Network_TX ) { PRINTF( option, "[NCSI] Time out when Disable Network TX \n" ); } 1219 if ( eng->flg.NCSI_Flag & NCSI_Flag_Disable_Channel ) { PRINTF( option, "[NCSI] Time out when Disable Channel \n" ); } 1220 if ( eng->flg.NCSI_Flag & NCSI_Flag_Select_Package ) { PRINTF( option, "[NCSI] Time out when Select Package \n" ); } 1221 if ( eng->flg.NCSI_Flag & NCSI_Flag_Deselect_Package ) { PRINTF( option, "[NCSI] Time out when Deselect Package \n" ); } 1222 if ( eng->flg.NCSI_Flag & NCSI_Flag_Set_Link ) { PRINTF( option, "[NCSI] Time out when Set Link \n" ); } 1223 if ( eng->flg.NCSI_Flag & NCSI_Flag_Get_Controller_Packet_Statistics) { PRINTF( option, "[NCSI] Time out when Get Controller Packet Statistics\n" ); } 1224 } 1225 1226 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[NCSI] Channel number expected: %d, real: %d\n", eng->arg.GChannelTolNum, eng->dat.number_chl ); } 1227 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[NCSI] Peckage number expected: %d, real: %d\n", eng->arg.GPackageTolNum, eng->dat.number_pak ); } 1228 } // End if ( eng->arg.run_mode == MODE_NCSI ) 1229 } // End if ( eng->flg.Err_Flag ) 1230 } // End if ( eng->flg.print_en ) 1231 } // End void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option) 1232 1233 //------------------------------------------------------------ 1234 1235 //------------------------------------------------------------ 1236 int FindErr (MAC_ENGINE *p_eng, int value) 1237 { 1238 p_eng->flg.Err_Flag = p_eng->flg.Err_Flag | value; 1239 1240 if (DbgPrn_ErrFlg) 1241 printf("\nErr_Flag: [%08x]\n", p_eng->flg.Err_Flag); 1242 1243 return (1); 1244 } 1245 1246 //------------------------------------------------------------ 1247 int FindErr_Des (MAC_ENGINE *p_eng, int value) 1248 { 1249 p_eng->flg.Err_Flag = p_eng->flg.Err_Flag | Err_Flag_Check_Des; 1250 p_eng->flg.Des_Flag = p_eng->flg.Des_Flag | value; 1251 if (DbgPrn_ErrFlg) 1252 printf("\nErr_Flag: [%08x] Des_Flag: [%08x]\n", 1253 p_eng->flg.Err_Flag, p_eng->flg.Des_Flag); 1254 1255 return (1); 1256 } 1257 1258 //------------------------------------------------------------ 1259 // Get and Check status of Interrupt 1260 //------------------------------------------------------------ 1261 int check_int (MAC_ENGINE *eng, char *type ) 1262 { 1263 nt_log_func_name(); 1264 1265 uint32_t mac_00; 1266 1267 mac_00 = mac_reg_read(eng, 0x00); 1268 #ifdef CheckRxbufUNAVA 1269 if (mac_00 & BIT(2)) { 1270 PRINTF( FP_LOG, "[%sIntStatus] Receiving buffer unavailable : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1271 FindErr( eng, Err_Flag_RXBUF_UNAVA ); 1272 } 1273 #endif 1274 1275 #ifdef CheckRPktLost 1276 if (mac_00 & BIT(3)) { 1277 PRINTF( FP_LOG, "[%sIntStatus] Received packet lost due to RX FIFO full : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1278 FindErr( eng, Err_Flag_RPKT_LOST ); 1279 } 1280 #endif 1281 1282 #ifdef CheckNPTxbufUNAVA 1283 if (mac_00 & BIT(6) ) { 1284 PRINTF( FP_LOG, "[%sIntStatus] Normal priority transmit buffer unavailable: %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1285 FindErr( eng, Err_Flag_NPTXBUF_UNAVA ); 1286 } 1287 #endif 1288 1289 #ifdef CheckTPktLost 1290 if (mac_00 & BIT(7)) { 1291 PRINTF( FP_LOG, "[%sIntStatus] Packets transmitted to Ethernet lost : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1292 FindErr( eng, Err_Flag_TPKT_LOST ); 1293 } 1294 #endif 1295 1296 if ( eng->flg.Err_Flag ) 1297 return(1); 1298 else 1299 return(0); 1300 } // End int check_int (MAC_ENGINE *eng, char *type) 1301 1302 1303 //------------------------------------------------------------ 1304 // Buffer 1305 //------------------------------------------------------------ 1306 void setup_framesize (MAC_ENGINE *eng) 1307 { 1308 int32_t des_num; 1309 1310 nt_log_func_name(); 1311 1312 //------------------------------ 1313 // Fill Frame Size out descriptor area 1314 //------------------------------ 1315 if (0) { 1316 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1317 if ( RAND_SIZE_SIMPLE ) 1318 switch( rand() % 5 ) { 1319 case 0 : eng->dat.FRAME_LEN[ des_num ] = 0x4e ; break; 1320 case 1 : eng->dat.FRAME_LEN[ des_num ] = 0x4ba; break; 1321 default: eng->dat.FRAME_LEN[ des_num ] = 0x5ea; break; 1322 } 1323 else 1324 // eng->dat.FRAME_LEN[ des_num ] = ( rand() + RAND_SIZE_MIN ) % ( RAND_SIZE_MAX + 1 ); 1325 eng->dat.FRAME_LEN[ des_num ] = RAND_SIZE_MIN + ( rand() % ( RAND_SIZE_MAX - RAND_SIZE_MIN + 1 ) ); 1326 1327 if ( DbgPrn_FRAME_LEN ) 1328 PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1329 } 1330 } 1331 else { 1332 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1333 #ifdef SelectSimpleLength 1334 if ( des_num % FRAME_SELH_PERD ) 1335 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH; 1336 else 1337 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL; 1338 #else 1339 if ( eng->run.tm_tx_only ) { 1340 if ( eng->run.TM_IEEE ) 1341 eng->dat.FRAME_LEN[ des_num ] = 1514; 1342 else 1343 eng->dat.FRAME_LEN[ des_num ] = 60; 1344 } 1345 else { 1346 #ifdef SelectLengthInc 1347 eng->dat.FRAME_LEN[ des_num ] = 1514 - ( des_num % 1455 ); 1348 #else 1349 if ( des_num % FRAME_SELH_PERD ) 1350 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH; 1351 else 1352 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL; 1353 #endif 1354 } // End if ( eng->run.tm_tx_only ) 1355 #endif 1356 if ( DbgPrn_FRAME_LEN ) 1357 PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1358 1359 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1360 } // End if ( ENABLE_RAND_SIZE ) 1361 1362 // Calculate average of frame size 1363 #ifdef Enable_ShowBW 1364 eng->dat.Total_frame_len = 0; 1365 1366 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) 1367 eng->dat.Total_frame_len += eng->dat.FRAME_LEN[ des_num ]; 1368 #endif 1369 1370 //------------------------------ 1371 // Write Plane 1372 //------------------------------ 1373 switch( ZeroCopy_OFFSET & 0x3 ) { 1374 case 0: eng->dat.wp_fir = 0xffffffff; break; 1375 case 1: eng->dat.wp_fir = 0xffffff00; break; 1376 case 2: eng->dat.wp_fir = 0xffff0000; break; 1377 case 3: eng->dat.wp_fir = 0xff000000; break; 1378 } 1379 1380 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) 1381 switch( ( ZeroCopy_OFFSET + eng->dat.FRAME_LEN[ des_num ] - 1 ) & 0x3 ) { 1382 case 0: eng->dat.wp_lst[ des_num ] = 0x000000ff; break; 1383 case 1: eng->dat.wp_lst[ des_num ] = 0x0000ffff; break; 1384 case 2: eng->dat.wp_lst[ des_num ] = 0x00ffffff; break; 1385 case 3: eng->dat.wp_lst[ des_num ] = 0xffffffff; break; 1386 } 1387 } // End void setup_framesize (void) 1388 1389 //------------------------------------------------------------ 1390 void setup_arp (MAC_ENGINE *eng) 1391 { 1392 int i; 1393 1394 nt_log_func_name(); 1395 for (i = 0; i < 16; i++) 1396 eng->dat.ARP_data[i] = ARP_org_data[i]; 1397 1398 eng->dat.ARP_data[1] = 0x0000ffff | (eng->inf.SA[0] << 16) // MSB 1399 | (eng->inf.SA[1] << 24); 1400 1401 eng->dat.ARP_data[2] = (eng->inf.SA[2]) | (eng->inf.SA[3] << 8) | 1402 (eng->inf.SA[4] << 16) | 1403 (eng->inf.SA[5] << 24); // LSB 1404 1405 eng->dat.ARP_data[5] = 0x00000100 | (eng->inf.SA[0] << 16) // MSB 1406 | (eng->inf.SA[1] << 24); 1407 1408 eng->dat.ARP_data[6] = (eng->inf.SA[2]) | (eng->inf.SA[3] << 8) | 1409 (eng->inf.SA[4] << 16) | 1410 (eng->inf.SA[5] << 24); // LSB 1411 } // End void setup_arp (MAC_ENGINE *eng) 1412 1413 //------------------------------------------------------------ 1414 void setup_buf (MAC_ENGINE *eng) 1415 { 1416 int32_t des_num_max; 1417 int32_t des_num; 1418 int i; 1419 uint32_t adr; 1420 uint32_t adr_srt; 1421 uint32_t adr_end; 1422 uint32_t Current_framelen; 1423 uint32_t gdata = 0; 1424 #ifdef SelectSimpleDA 1425 int cnt; 1426 uint32_t len; 1427 #endif 1428 1429 nt_log_func_name(); 1430 1431 // It need be multiple of 4 1432 eng->dat.DMA_Base_Setup = DMA_BASE & 0xfffffffc; 1433 adr_srt = eng->dat.DMA_Base_Setup; 1434 1435 if (eng->run.tm_tx_only) { 1436 if (eng->run.TM_IEEE) { 1437 for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) { 1438 if ( DbgPrn_BufAdr ) 1439 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1440 #ifdef ENABLE_DASA 1441 Write_Mem_Dat_DD( adr_srt , 0xffffffff ); 1442 Write_Mem_Dat_DD( adr_srt + 4, eng->dat.ARP_data[1] ); 1443 Write_Mem_Dat_DD( adr_srt + 8, eng->dat.ARP_data[2] ); 1444 1445 for ( adr = (adr_srt + 12); adr < (adr_srt + DMA_PakSize); adr += 4 ) 1446 #else 1447 for ( adr = adr_srt; adr < (adr_srt + DMA_PakSize); adr += 4 ) 1448 #endif 1449 { 1450 switch (eng->arg.test_mode) { 1451 case 4: 1452 gdata = rand() | (rand() << 16); 1453 break; 1454 case 5: 1455 gdata = eng->arg.user_def_val; 1456 break; 1457 } 1458 Write_Mem_Dat_DD( adr, gdata ); 1459 } // End for() 1460 adr_srt += DMA_PakSize; 1461 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1462 } 1463 else { 1464 printf("----->[ARP] 60 bytes\n"); 1465 for (i = 0; i < 16; i++) 1466 printf(" [Tx%02d] %08x %08x\n", i, eng->dat.ARP_data[i], SWAP_4B( eng->dat.ARP_data[i] ) ); 1467 1468 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1469 if ( DbgPrn_BufAdr ) 1470 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1471 1472 for (i = 0; i < 16; i++) 1473 Write_Mem_Dat_DD( adr_srt + ( i << 2 ), eng->dat.ARP_data[i] ); 1474 1475 1476 adr_srt += DMA_PakSize; 1477 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1478 } // End if ( eng->run.TM_IEEE ) 1479 } else { 1480 if ( eng->arg.ctrl.b.single_packet ) 1481 des_num_max = 1; 1482 else 1483 des_num_max = eng->dat.Des_Num; 1484 1485 for (des_num = 0; des_num < des_num_max; des_num++) { 1486 if (DbgPrn_BufAdr) 1487 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1488 #ifdef SelectSimpleData 1489 #ifdef SimpleData_Fix 1490 switch( des_num % SimpleData_FixNum ) { 1491 case 0 : gdata = SimpleData_FixVal00; break; 1492 case 1 : gdata = SimpleData_FixVal01; break; 1493 case 2 : gdata = SimpleData_FixVal02; break; 1494 case 3 : gdata = SimpleData_FixVal03; break; 1495 case 4 : gdata = SimpleData_FixVal04; break; 1496 case 5 : gdata = SimpleData_FixVal05; break; 1497 case 6 : gdata = SimpleData_FixVal06; break; 1498 case 7 : gdata = SimpleData_FixVal07; break; 1499 case 8 : gdata = SimpleData_FixVal08; break; 1500 case 9 : gdata = SimpleData_FixVal09; break; 1501 case 10 : gdata = SimpleData_FixVal10; break; 1502 default : gdata = SimpleData_FixVal11; break; 1503 } 1504 #else 1505 gdata = 0x11111111 * ((des_num + SEED_START) % 256); 1506 #endif 1507 #else 1508 gdata = DATA_SEED( des_num + SEED_START ); 1509 #endif 1510 Current_framelen = eng->dat.FRAME_LEN[ des_num ]; 1511 1512 if ( DbgPrn_FRAME_LEN ) 1513 PRINTF( FP_LOG, "[setup_buf ] Current_framelen:%08x[Des:%d][loop[%d]:%d]\n", Current_framelen, des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1514 #ifdef SelectSimpleDA 1515 cnt = 0; 1516 len = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) | 1517 ( ( Current_framelen - 14 ) >> 8 ); 1518 #endif 1519 adr_end = adr_srt + DMA_PakSize; 1520 for ( adr = adr_srt; adr < adr_end; adr += 4 ) { 1521 #ifdef SelectSimpleDA 1522 cnt++; 1523 if ( cnt == 1 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat0 ); 1524 else if ( cnt == 2 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat1 ); 1525 else if ( cnt == 3 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat2 ); 1526 else if ( cnt == 4 ) Write_Mem_Dat_DD( adr, len | (len << 16) ); 1527 else 1528 #endif 1529 Write_Mem_Dat_DD( adr, gdata ); 1530 #ifdef SelectSimpleData 1531 gdata = gdata ^ SimpleData_XORVal; 1532 #else 1533 gdata += DATA_IncVal; 1534 #endif 1535 } 1536 adr_srt += DMA_PakSize; 1537 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1538 } // End if ( eng->run.tm_tx_only ) 1539 } // End void setup_buf (MAC_ENGINE *eng) 1540 1541 //------------------------------------------------------------ 1542 // Check data of one packet 1543 //------------------------------------------------------------ 1544 char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number) 1545 { 1546 int32_t number_dat; 1547 int index; 1548 uint32_t rdata; 1549 uint32_t wp_lst_cur; 1550 uint32_t adr_las; 1551 uint32_t adr; 1552 uint32_t adr_srt; 1553 uint32_t adr_end; 1554 #ifdef SelectSimpleDA 1555 int cnt; 1556 uint32_t len; 1557 uint32_t gdata_bak; 1558 #endif 1559 uint32_t gdata; 1560 1561 uint32_t wp; 1562 1563 nt_log_func_name(); 1564 1565 if (eng->arg.ctrl.b.single_packet) 1566 number_dat = 0; 1567 else 1568 number_dat = number; 1569 1570 wp_lst_cur = eng->dat.wp_lst[ number ]; 1571 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[ number_dat ]; 1572 1573 if ( DbgPrn_FRAME_LEN ) 1574 PRINTF( FP_LOG, "[check_Data ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN_Cur, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1575 1576 adr_srt = datbase; 1577 adr_end = adr_srt + PktByteSize; 1578 1579 #if defined(SelectSimpleData) 1580 #ifdef SimpleData_Fix 1581 switch( number_dat % SimpleData_FixNum ) { 1582 case 0 : gdata = SimpleData_FixVal00; break; 1583 case 1 : gdata = SimpleData_FixVal01; break; 1584 case 2 : gdata = SimpleData_FixVal02; break; 1585 case 3 : gdata = SimpleData_FixVal03; break; 1586 case 4 : gdata = SimpleData_FixVal04; break; 1587 case 5 : gdata = SimpleData_FixVal05; break; 1588 case 6 : gdata = SimpleData_FixVal06; break; 1589 case 7 : gdata = SimpleData_FixVal07; break; 1590 case 8 : gdata = SimpleData_FixVal08; break; 1591 case 9 : gdata = SimpleData_FixVal09; break; 1592 case 10 : gdata = SimpleData_FixVal10; break; 1593 default : gdata = SimpleData_FixVal11; break; 1594 } 1595 #else 1596 gdata = 0x11111111 * (( number_dat + SEED_START ) % 256 ); 1597 #endif 1598 #else 1599 gdata = DATA_SEED( number_dat + SEED_START ); 1600 #endif 1601 1602 //printf("check_buf: %08x - %08x [%08x]\n", adr_srt, adr_end, datbase); 1603 wp = eng->dat.wp_fir; 1604 adr_las = adr_end - 4; 1605 #ifdef SelectSimpleDA 1606 cnt = 0; 1607 len = ((( eng->dat.FRAME_LEN_Cur-14 ) & 0xff ) << 8 ) | 1608 ( ( eng->dat.FRAME_LEN_Cur-14 ) >> 8 ); 1609 #endif 1610 1611 if ( DbgPrn_Bufdat ) 1612 PRINTF( FP_LOG, " Inf:%08x ~ %08x(%08x) %08x [Des:%d][loop[%d]:%d]\n", adr_srt, adr_end, adr_las, gdata, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1613 1614 for ( adr = adr_srt; adr < adr_end; adr+=4 ) { 1615 #ifdef SelectSimpleDA 1616 cnt++; 1617 if ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; } 1618 else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; } 1619 else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; } 1620 else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16); } 1621 #endif 1622 rdata = Read_Mem_Dat_DD( adr ); 1623 if ( adr == adr_las ) 1624 wp = wp & wp_lst_cur; 1625 1626 if ( ( rdata & wp ) != ( gdata & wp ) ) { 1627 PRINTF( FP_LOG, "\nError: Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1628 for ( index = 0; index < 6; index++ ) 1629 PRINTF( FP_LOG, "Rep : Adr:%08x (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, Read_Mem_Dat_DD( adr ), gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1630 1631 if (DbgPrn_DumpMACCnt) 1632 dump_mac_ROreg(eng); 1633 1634 return( FindErr( eng, Err_Flag_Check_Buf_Data ) ); 1635 } // End if ( (rdata & wp) != (gdata & wp) ) 1636 if ( DbgPrn_BufdatDetail ) 1637 PRINTF( FP_LOG, " Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1638 1639 #ifdef SelectSimpleDA 1640 if ( cnt <= 4 ) 1641 gdata = gdata_bak; 1642 #endif 1643 1644 #if defined(SelectSimpleData) 1645 gdata = gdata ^ SimpleData_XORVal; 1646 #else 1647 gdata += DATA_IncVal; 1648 #endif 1649 1650 wp = 0xffffffff; 1651 } 1652 return(0); 1653 } // End char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number) 1654 1655 //------------------------------------------------------------ 1656 char check_buf (MAC_ENGINE *eng, int loopcnt) 1657 { 1658 int32_t des_num; 1659 uint32_t desadr; 1660 uint32_t datbase; 1661 1662 nt_log_func_name(); 1663 1664 desadr = eng->run.rdes_base + (16 * eng->dat.Des_Num) - 4; 1665 for (des_num = eng->dat.Des_Num - 1; des_num >= 0; des_num--) { 1666 #ifdef CHECK_RX_DATA 1667 datbase = AT_BUF_MEMRW(Read_Mem_Des_DD(desadr) & 0xfffffffc); 1668 if (check_Data(eng, datbase, des_num)) { 1669 check_int(eng, ""); 1670 return (1); 1671 } 1672 if (check_int(eng, "")) 1673 return 1; 1674 #endif 1675 desadr -= 16; 1676 } 1677 if (check_int(eng, "")) 1678 return (1); 1679 1680 #if defined(Delay_CheckData_LoopNum) && defined(Delay_CheckData) 1681 if ((loopcnt % Delay_CheckData_LoopNum) == 0) 1682 DELAY(Delay_CheckData); 1683 #endif 1684 return (0); 1685 } // End char check_buf (MAC_ENGINE *eng, int loopcnt) 1686 1687 //------------------------------------------------------------ 1688 // Descriptor 1689 //------------------------------------------------------------ 1690 void setup_txdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase) 1691 { 1692 uint32_t bufadr; 1693 uint32_t bufadrgap; 1694 uint32_t desval = 0; 1695 int32_t des_num; 1696 1697 nt_log_func_name(); 1698 1699 bufadr = bufbase; 1700 if (eng->arg.ctrl.b.single_packet) 1701 bufadrgap = 0; 1702 else 1703 bufadrgap = DMA_PakSize; 1704 1705 if (eng->run.TM_TxDataEn) { 1706 for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) { 1707 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1708 desval = TDES_IniVal; 1709 Write_Mem_Des_DD(desadr + 0x04, 0); 1710 Write_Mem_Des_DD(desadr + 0x08, 0); 1711 Write_Mem_Des_DD(desadr + 0x0C, bufadr); 1712 Write_Mem_Des_DD(desadr, desval); 1713 1714 if (DbgPrn_FRAME_LEN) 1715 PRINTF( 1716 FP_LOG, 1717 "[setup_txdes ] " 1718 "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", 1719 eng->dat.FRAME_LEN_Cur, des_num, 1720 eng->run.loop_of_cnt, eng->run.loop_cnt); 1721 1722 if (DbgPrn_BufAdr) 1723 printf("[loop[%d]:%4d][des:%4d][setup_txdes] " 1724 "%08x [%08x]\n", 1725 eng->run.loop_of_cnt, eng->run.loop_cnt, 1726 des_num, desadr, bufadr); 1727 1728 desadr += 16; 1729 bufadr += bufadrgap; 1730 } 1731 barrier(); 1732 Write_Mem_Des_DD(desadr - 0x10, desval | EOR_IniVal); 1733 } else { 1734 Write_Mem_Des_DD(desadr, 0); 1735 } 1736 } 1737 1738 //------------------------------------------------------------ 1739 void setup_rxdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase) 1740 { 1741 uint32_t bufadr; 1742 uint32_t desval; 1743 int32_t des_num; 1744 1745 nt_log_func_name(); 1746 1747 bufadr = bufbase; 1748 desval = RDES_IniVal; 1749 if ( eng->run.TM_RxDataEn ) { 1750 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1751 Write_Mem_Des_DD(desadr + 0x04, 0 ); 1752 Write_Mem_Des_DD(desadr + 0x08, 0 ); 1753 Write_Mem_Des_DD(desadr + 0x0C, bufadr); 1754 Write_Mem_Des_DD(desadr + 0x00, desval); 1755 1756 if ( DbgPrn_BufAdr ) 1757 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x [%08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, desadr, bufadr); 1758 1759 desadr += 16; 1760 bufadr += DMA_PakSize; 1761 } 1762 barrier(); 1763 Write_Mem_Des_DD( desadr - 0x10, desval | EOR_IniVal ); 1764 } 1765 else { 1766 Write_Mem_Des_DD( desadr, 0x80000000 ); 1767 } // End if ( eng->run.TM_RxDataEn ) 1768 } // End void setup_rxdes (uint32_t desadr, uint32_t bufbase) 1769 1770 //------------------------------------------------------------ 1771 // First setting TX and RX information 1772 //------------------------------------------------------------ 1773 void setup_des (MAC_ENGINE *eng, uint32_t bufnum) 1774 { 1775 if (DbgPrn_BufAdr) { 1776 printf("setup_des: %d\n", bufnum); 1777 debug_pause(); 1778 } 1779 1780 eng->dat.DMA_Base_Tx = 1781 ZeroCopy_OFFSET + eng->dat.DMA_Base_Setup; 1782 eng->dat.DMA_Base_Rx = ZeroCopy_OFFSET + GET_DMA_BASE(eng, 0); 1783 1784 setup_txdes(eng, eng->run.tdes_base, 1785 AT_MEMRW_BUF(eng->dat.DMA_Base_Tx)); 1786 setup_rxdes(eng, eng->run.rdes_base, 1787 AT_MEMRW_BUF(eng->dat.DMA_Base_Rx)); 1788 } // End void setup_des (uint32_t bufnum) 1789 1790 //------------------------------------------------------------ 1791 // Move buffer point of TX and RX descriptor to next DMA buffer 1792 //------------------------------------------------------------ 1793 void setup_des_loop (MAC_ENGINE *eng, uint32_t bufnum) 1794 { 1795 int32_t des_num; 1796 uint32_t H_rx_desadr; 1797 uint32_t H_tx_desadr; 1798 uint32_t H_tx_bufadr; 1799 uint32_t H_rx_bufadr; 1800 1801 nt_log_func_name(); 1802 1803 if (eng->run.TM_RxDataEn) { 1804 H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx); 1805 H_rx_desadr = eng->run.rdes_base; 1806 for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) { 1807 Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr); 1808 Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal); 1809 if (DbgPrn_BufAdr) 1810 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] " 1811 "%08x [%08x]\n", 1812 eng->run.loop_of_cnt, eng->run.loop_cnt, 1813 des_num, H_rx_desadr, H_rx_bufadr); 1814 1815 H_rx_bufadr += DMA_PakSize; 1816 H_rx_desadr += 16; 1817 } 1818 Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr); 1819 Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal | EOR_IniVal); 1820 if (DbgPrn_BufAdr) 1821 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x " 1822 "[%08x]\n", 1823 eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, 1824 H_rx_desadr, H_rx_bufadr); 1825 } 1826 1827 if (eng->run.TM_TxDataEn) { 1828 H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx); 1829 H_tx_desadr = eng->run.tdes_base; 1830 for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) { 1831 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1832 Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr); 1833 Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal); 1834 if (DbgPrn_BufAdr) 1835 printf("[loop[%d]:%4d][des:%4d][setup_txdes] " 1836 "%08x [%08x]\n", 1837 eng->run.loop_of_cnt, eng->run.loop_cnt, 1838 des_num, H_tx_desadr, H_tx_bufadr); 1839 1840 H_tx_bufadr += DMA_PakSize; 1841 H_tx_desadr += 16; 1842 } 1843 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1844 Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr); 1845 Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal | EOR_IniVal); 1846 if (DbgPrn_BufAdr) 1847 printf("[loop[%d]:%4d][des:%4d][setup_txdes] %08x " 1848 "[%08x]\n", 1849 eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, 1850 H_tx_desadr, H_tx_bufadr); 1851 } 1852 } // End void setup_des_loop (uint32_t bufnum) 1853 1854 //------------------------------------------------------------ 1855 char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1856 { 1857 int timeout = 0; 1858 1859 eng->dat.TxDes0DW = Read_Mem_Des_DD(adr); 1860 1861 while (HWOwnTx(eng->dat.TxDes0DW)) { 1862 // we will run again, if transfer has not been completed. 1863 if ((eng->run.tm_tx_only || eng->run.TM_RxDataEn) && 1864 (++timeout > eng->run.timeout_th)) { 1865 PRINTF(FP_LOG, 1866 "[%sTxDesOwn] Address %08x = %08x " 1867 "[Des:%d][loop[%d]:%d]\n", 1868 type, adr, eng->dat.TxDes0DW, desnum, 1869 eng->run.loop_of_cnt, eng->run.loop_cnt); 1870 return (FindErr_Des(eng, Des_Flag_TxOwnTimeOut)); 1871 } 1872 1873 #ifdef Delay_ChkTxOwn 1874 DELAY(Delay_ChkTxOwn); 1875 #endif 1876 eng->dat.TxDes0DW = Read_Mem_Des_DD(adr); 1877 } 1878 1879 return(0); 1880 } // End char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1881 1882 //------------------------------------------------------------ 1883 char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1884 { 1885 #ifdef CheckRxOwn 1886 int timeout = 0; 1887 1888 eng->dat.RxDes0DW = Read_Mem_Des_DD(adr); 1889 1890 while (HWOwnRx(eng->dat.RxDes0DW)) { 1891 // we will run again, if transfer has not been completed. 1892 if (eng->run.TM_TxDataEn && (++timeout > eng->run.timeout_th)) { 1893 #if 0 1894 printf("[%sRxDesOwn] Address %08x = %08x " 1895 "[Des:%d][loop[%d]:%d]\n", 1896 type, adr, eng->dat.RxDes0DW, desnum, 1897 eng->run.loop_of_cnt, eng->run.loop_cnt); 1898 #endif 1899 FindErr_Des(eng, Des_Flag_RxOwnTimeOut); 1900 return (2); 1901 } 1902 1903 #ifdef Delay_ChkRxOwn 1904 DELAY(Delay_ChkRxOwn); 1905 #endif 1906 eng->dat.RxDes0DW = Read_Mem_Des_DD(adr); 1907 }; 1908 1909 #ifdef CheckRxLen 1910 if ( DbgPrn_FRAME_LEN ) 1911 PRINTF( FP_LOG, "[%sRxDes ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", type, ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1912 1913 if ( ( eng->dat.RxDes0DW & 0x3fff ) != ( eng->dat.FRAME_LEN_Cur + 4 ) ) { 1914 eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 ); 1915 PRINTF( FP_LOG, "[%sRxDes] Error Frame Length %08x:%08x %08x(%4d/%4d) [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, ( eng->dat.RxDes0DW & 0x3fff ), ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1916 FindErr_Des( eng, Des_Flag_FrameLen ); 1917 } 1918 #endif // End CheckRxLen 1919 1920 if ( eng->dat.RxDes0DW & RXDES_EM_ALL ) { 1921 eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 ); 1922 #ifdef CheckRxErr 1923 if ( eng->dat.RxDes0DW & RXDES_EM_RXERR ) { 1924 PRINTF( FP_LOG, "[%sRxDes] Error RxErr %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1925 FindErr_Des( eng, Des_Flag_RxErr ); 1926 } 1927 #endif // End CheckRxErr 1928 1929 #ifdef CheckCRC 1930 if ( eng->dat.RxDes0DW & RXDES_EM_CRC ) { 1931 PRINTF( FP_LOG, "[%sRxDes] Error CRC %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1932 FindErr_Des( eng, Des_Flag_CRC ); 1933 } 1934 #endif // End CheckCRC 1935 1936 #ifdef CheckFTL 1937 if ( eng->dat.RxDes0DW & RXDES_EM_FTL ) { 1938 PRINTF( FP_LOG, "[%sRxDes] Error FTL %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1939 FindErr_Des( eng, Des_Flag_FTL ); 1940 } 1941 #endif // End CheckFTL 1942 1943 #ifdef CheckRunt 1944 if ( eng->dat.RxDes0DW & RXDES_EM_RUNT) { 1945 PRINTF( FP_LOG, "[%sRxDes] Error Runt %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1946 FindErr_Des( eng, Des_Flag_Runt ); 1947 } 1948 #endif // End CheckRunt 1949 1950 #ifdef CheckOddNibble 1951 if ( eng->dat.RxDes0DW & RXDES_EM_ODD_NB ) { 1952 PRINTF( FP_LOG, "[%sRxDes] Odd Nibble %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1953 FindErr_Des( eng, Des_Flag_OddNibble ); 1954 } 1955 #endif // End CheckOddNibble 1956 1957 #ifdef CheckRxFIFOFull 1958 if ( eng->dat.RxDes0DW & RXDES_EM_FIFO_FULL ) { 1959 PRINTF( FP_LOG, "[%sRxDes] Error Rx FIFO Full %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1960 FindErr_Des( eng, Des_Flag_RxFIFOFull ); 1961 } 1962 #endif // End CheckRxFIFOFull 1963 } 1964 1965 #endif // End CheckRxOwn 1966 1967 if ( eng->flg.Err_Flag ) 1968 return(1); 1969 else 1970 return(0); 1971 } // End char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1972 1973 //------------------------------------------------------------ 1974 char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint) 1975 { 1976 int32_t desnum; 1977 int8_t desnum_last; 1978 uint32_t H_rx_desadr; 1979 uint32_t H_tx_desadr; 1980 uint32_t H_tx_bufadr; 1981 uint32_t H_rx_bufadr; 1982 #ifdef Delay_DesGap 1983 uint32_t dly_cnt = 0; 1984 uint32_t dly_max = Delay_CntMaxIncVal; 1985 #endif 1986 int ret; 1987 1988 nt_log_func_name(); 1989 1990 /* Fire the engine to send and recvice */ 1991 mac_reg_write(eng, 0x1c, 0x00000001); // Rx Poll 1992 mac_reg_write(eng, 0x18, 0x00000001); // Tx Poll 1993 1994 #ifndef SelectSimpleDes 1995 /* base of the descriptors */ 1996 H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx); 1997 H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx); 1998 #endif 1999 H_rx_desadr = eng->run.rdes_base; 2000 H_tx_desadr = eng->run.tdes_base; 2001 2002 #ifdef Delay_DES 2003 DELAY(Delay_DES); 2004 #endif 2005 2006 for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) { 2007 desnum_last = (desnum == (eng->dat.Des_Num - 1)) ? 1 : 0; 2008 if ( DbgPrn_BufAdr ) { 2009 if ( checkpoint ) 2010 printf("[loop[%d]:%4d][des:%4d][check_des ] %08x %08x [%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ) ); 2011 else 2012 printf("[loop[%d]:%4d][des:%4d][check_des ] %08x %08x [%08x %08x]->[%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ), H_tx_bufadr, H_rx_bufadr ); 2013 } 2014 2015 //[Delay]-------------------- 2016 #ifdef Delay_DesGap 2017 // if ( dly_cnt++ > 3 ) { 2018 if ( dly_cnt > Delay_CntMax ) { 2019 // switch ( rand() % 12 ) { 2020 // case 1 : dly_max = 00000; break; 2021 // case 3 : dly_max = 20000; break; 2022 // case 5 : dly_max = 40000; break; 2023 // case 7 : dly_max = 60000; break; 2024 // defaule: dly_max = 70000; break; 2025 // } 2026 // 2027 // dly_max += ( rand() % 4 ) * 14321; 2028 // 2029 // while (dly_cnt < dly_max) { 2030 // dly_cnt++; 2031 // } 2032 DELAY( Delay_DesGap ); 2033 dly_cnt = 0; 2034 } 2035 else { 2036 dly_cnt++; 2037 // timeout = 0; 2038 // while (timeout < 50000) {timeout++;}; 2039 } 2040 #endif // End Delay_DesGap 2041 2042 //[Check Owner Bit]-------------------- 2043 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[desnum]; 2044 if (DbgPrn_FRAME_LEN) 2045 PRINTF(FP_LOG, 2046 "[check_des ] " 2047 "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]%d\n", 2048 eng->dat.FRAME_LEN_Cur, desnum, 2049 eng->run.loop_of_cnt, eng->run.loop_cnt, 2050 checkpoint); 2051 2052 // Check the description of Tx and Rx 2053 if (eng->run.TM_TxDataEn) { 2054 ret = check_des_header_Tx(eng, "", H_tx_desadr, desnum); 2055 if (ret) { 2056 eng->flg.CheckDesFail_DesNum = desnum; 2057 return ret; 2058 } 2059 } 2060 if (eng->run.TM_RxDataEn) { 2061 ret = check_des_header_Rx(eng, "", H_rx_desadr, desnum); 2062 if (ret) { 2063 eng->flg.CheckDesFail_DesNum = desnum; 2064 return ret; 2065 2066 } 2067 } 2068 2069 #ifndef SelectSimpleDes 2070 if (!checkpoint) { 2071 // Setting buffer address to description of Tx and Rx on next stage 2072 if ( eng->run.TM_RxDataEn ) { 2073 Write_Mem_Des_DD( H_rx_desadr + 0x0C, H_rx_bufadr ); 2074 if ( desnum_last ) 2075 Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal ); 2076 else 2077 Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal ); 2078 2079 readl(H_rx_desadr); 2080 mac_reg_write(eng, 0x1c, 0x00000000); //Rx Poll 2081 H_rx_bufadr += DMA_PakSize; 2082 } 2083 if ( eng->run.TM_TxDataEn ) { 2084 Write_Mem_Des_DD( H_tx_desadr + 0x0C, H_tx_bufadr ); 2085 if ( desnum_last ) 2086 Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal ); 2087 else 2088 Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal ); 2089 2090 readl(H_tx_desadr); 2091 mac_reg_write(eng, 0x18, 0x00000000); //Tx Poll 2092 H_tx_bufadr += DMA_PakSize; 2093 } 2094 } 2095 #endif // End SelectSimpleDes 2096 2097 H_rx_desadr += 16; 2098 H_tx_desadr += 16; 2099 } // End for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) 2100 2101 return(0); 2102 } // End char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint) 2103 //#endif 2104 2105 //------------------------------------------------------------ 2106 // Print 2107 //----------------------------------------------------------- 2108 void PrintIO_Header (MAC_ENGINE *eng, uint8_t option) 2109 { 2110 int32_t rx_d, step, tmp; 2111 2112 if (eng->run.TM_IOStrength) { 2113 if (eng->io.drv_upper_bond > 1) { 2114 #ifdef CONFIG_ASPEED_AST2600 2115 PRINTF(option, "<IO Strength register: [%08x] 0x%08x>", 2116 eng->io.mac34_drv_reg.addr, 2117 eng->io.mac34_drv_reg.value.w); 2118 #else 2119 PRINTF(option, "<IO Strength register: [%08x] 0x%08x>", 2120 eng->io.mac12_drv_reg.addr, 2121 eng->io.mac12_drv_reg.value.w); 2122 #endif 2123 } 2124 } 2125 2126 if ( eng->run.speed_sel[ 0 ] ) { PRINTF( option, "\n[1G ]========================================>\n" ); } 2127 else if ( eng->run.speed_sel[ 1 ] ) { PRINTF( option, "\n[100M]========================================>\n" ); } 2128 else { PRINTF( option, "\n[10M ]========================================>\n" ); } 2129 2130 if ( !(option == FP_LOG) ) { 2131 step = eng->io.rx_delay_scan.step; 2132 2133 PRINTF(option, "\n "); 2134 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2135 2136 if (rx_d < 0) { 2137 PRINTF(option, "-" ); 2138 } else { 2139 PRINTF(option, "+" ); 2140 } 2141 } 2142 2143 PRINTF(option, "\n "); 2144 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2145 tmp = (abs(rx_d) >> 4) & 0xf; 2146 if (tmp == 0) { 2147 PRINTF(option, "0" ); 2148 } else { 2149 PRINTF(option, "%1x", tmp); 2150 } 2151 } 2152 2153 PRINTF(option, "\n "); 2154 for (rx_d = eng->io.rx_delay_scan.begin; 2155 rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2156 PRINTF(option, "%1x", (uint32_t)abs(rx_d) & 0xf); 2157 } 2158 2159 PRINTF(option, "\n "); 2160 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2161 if (eng->io.rx_delay_scan.orig == rx_d) { 2162 PRINTF(option, "|" ); 2163 } else { 2164 PRINTF(option, " " ); 2165 } 2166 } 2167 PRINTF( option, "\n"); 2168 } 2169 } 2170 2171 //------------------------------------------------------------ 2172 void PrintIO_LineS(MAC_ENGINE *p_eng, uint8_t option) 2173 { 2174 if (p_eng->io.tx_delay_scan.orig == p_eng->io.Dly_out_selval) { 2175 PRINTF( option, "%02x:-", p_eng->io.Dly_out_selval); 2176 } else { 2177 PRINTF( option, "%02x: ", p_eng->io.Dly_out_selval); 2178 } 2179 } // End void PrintIO_LineS (MAC_ENGINE *eng, uint8_t option) 2180 2181 //------------------------------------------------------------ 2182 void PrintIO_Line(MAC_ENGINE *p_eng, uint8_t option) 2183 { 2184 if ((p_eng->io.Dly_in_selval == p_eng->io.rx_delay_scan.orig) && 2185 (p_eng->io.Dly_out_selval == p_eng->io.tx_delay_scan.orig)) { 2186 if (1 == p_eng->io.result) { 2187 PRINTF(option, "X"); 2188 } else if (2 == p_eng->io.result) { 2189 PRINTF(option, "*"); 2190 } else { 2191 PRINTF(option, "O"); 2192 } 2193 } else { 2194 if (1 == p_eng->io.result) { 2195 PRINTF(option, "x"); 2196 } else if (2 == p_eng->io.result) { 2197 PRINTF(option, "."); 2198 } else { 2199 PRINTF(option, "o"); 2200 } 2201 } 2202 } 2203 2204 //------------------------------------------------------------ 2205 // main 2206 //------------------------------------------------------------ 2207 2208 //------------------------------------------------------------ 2209 void TestingSetup (MAC_ENGINE *eng) 2210 { 2211 nt_log_func_name(); 2212 2213 //[Setup]-------------------- 2214 setup_framesize( eng ); 2215 setup_buf( eng ); 2216 } 2217 2218 //------------------------------------------------------------ 2219 // Return 1 ==> fail 2220 // Return 0 ==> PASS 2221 //------------------------------------------------------------ 2222 char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum) 2223 { 2224 char checkprd; 2225 char looplast; 2226 char checken; 2227 int ret; 2228 2229 nt_log_func_name(); 2230 2231 if (DbgPrn_DumpMACCnt) 2232 dump_mac_ROreg(eng); 2233 2234 //[Setup]-------------------- 2235 eng->run.loop_cnt = 0; 2236 checkprd = 0; 2237 checken = 0; 2238 looplast = 0; 2239 2240 2241 setup_des(eng, 0); 2242 2243 if ( eng->run.TM_WaitStart ) { 2244 printf("Press any key to start...\n"); 2245 GET_CAHR(); 2246 } 2247 2248 2249 while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) { 2250 looplast = !eng->arg.loop_inf && ( eng->run.loop_cnt == eng->run.loop_max - 1 ); 2251 2252 #ifdef CheckRxBuf 2253 if (!eng->run.tm_tx_only) 2254 checkprd = ((eng->run.loop_cnt % loop_checknum) == (loop_checknum - 1)); 2255 checken = looplast | checkprd; 2256 #endif 2257 2258 if (DbgPrn_BufAdr) { 2259 printf("for start ======> [%d]%d/%d(%d) looplast:%d " 2260 "checkprd:%d checken:%d\n", 2261 eng->run.loop_of_cnt, eng->run.loop_cnt, 2262 eng->run.loop_max, eng->arg.loop_inf, 2263 looplast, checkprd, checken); 2264 debug_pause(); 2265 } 2266 2267 2268 if (eng->run.TM_RxDataEn) 2269 eng->dat.DMA_Base_Tx = eng->dat.DMA_Base_Rx; 2270 2271 eng->dat.DMA_Base_Rx = 2272 ZeroCopy_OFFSET + GET_DMA_BASE(eng, eng->run.loop_cnt + 1); 2273 //[Check DES]-------------------- 2274 if (ret = check_des(eng, eng->run.loop_cnt, checken)) { 2275 //descriptor error 2276 eng->dat.Des_Num = eng->flg.CheckDesFail_DesNum + 1; 2277 #ifdef CheckRxBuf 2278 if (checkprd) 2279 check_buf(eng, loop_checknum); 2280 else 2281 check_buf(eng, (eng->run.loop_max % loop_checknum)); 2282 eng->dat.Des_Num = eng->dat.Des_Num_Org; 2283 #endif 2284 2285 if (DbgPrn_DumpMACCnt) 2286 dump_mac_ROreg(eng); 2287 2288 return ret; 2289 } 2290 2291 //[Check Buf]-------------------- 2292 if (eng->run.TM_RxDataEn && checken) { 2293 if (checkprd) { 2294 #ifdef Enable_ShowBW 2295 printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused); 2296 PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused ); 2297 #endif 2298 2299 #ifdef CheckRxBuf 2300 if (check_buf(eng, loop_checknum)) 2301 return(1); 2302 #endif 2303 } else { 2304 #ifdef Enable_ShowBW 2305 printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused); 2306 PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused ); 2307 #endif 2308 2309 #ifdef CheckRxBuf 2310 if (check_buf(eng, (eng->run.loop_max % loop_checknum))) 2311 return(1); 2312 #endif 2313 } // End if ( checkprd ) 2314 2315 #ifndef SelectSimpleDes 2316 if (!looplast) 2317 setup_des_loop(eng, eng->run.loop_cnt); 2318 #endif 2319 2320 #ifdef Enable_ShowBW 2321 timeold = clock(); 2322 #endif 2323 } // End if ( eng->run.TM_RxDataEn && checken ) 2324 2325 #ifdef SelectSimpleDes 2326 if (!looplast) 2327 setup_des_loop(eng, eng->run.loop_cnt); 2328 #endif 2329 2330 if ( eng->arg.loop_inf ) 2331 printf("===============> Loop[%d]: %d \r", eng->run.loop_of_cnt, eng->run.loop_cnt); 2332 else if ( eng->arg.test_mode == 0 ) { 2333 if ( !( DbgPrn_BufAdr || eng->run.delay_margin ) ) 2334 printf(" [%d]%d \r", eng->run.loop_of_cnt, eng->run.loop_cnt); 2335 } 2336 2337 if (DbgPrn_BufAdr) { 2338 printf("for end ======> [%d]%d/%d(%d)\n", 2339 eng->run.loop_of_cnt, eng->run.loop_cnt, 2340 eng->run.loop_max, eng->arg.loop_inf); 2341 debug_pause(); 2342 } 2343 2344 if (eng->run.loop_cnt >= 0x7fffffff) { 2345 debug("loop counter wrapped around\n"); 2346 eng->run.loop_cnt = 0; 2347 eng->run.loop_of_cnt++; 2348 } else 2349 eng->run.loop_cnt++; 2350 } // End while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) 2351 2352 eng->flg.all_fail = 0; 2353 return(0); 2354 } // End char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum) 2355