1 /* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11 //#define MAC_DEBUG_REGRW_MAC 12 //#define MAC_DEBUG_REGRW_PHY 13 //#define MAC_DEBUG_REGRW_SCU 14 //#define MAC_DEBUG_REGRW_WDT 15 //#define MAC_DEBUG_REGRW_SDR 16 //#define MAC_DEBUG_REGRW_SMB 17 //#define MAC_DEBUG_REGRW_TIMER 18 //#define MAC_DEBUG_REGRW_GPIO 19 //#define MAC_DEBUG_MEMRW_Dat 20 //#define MAC_DEBUG_MEMRW_Des 21 22 #define MAC_C 23 24 #include "swfunc.h" 25 26 #include "comminf.h" 27 #include <command.h> 28 #include <common.h> 29 #include <malloc.h> 30 #include "mem_io.h" 31 // ------------------------------------------------------------- 32 const uint32_t ARP_org_data[16] = { 33 0xffffffff, 34 0x0000ffff, // SA:00-00- 35 0x12345678, // SA:78-56-34-12 36 0x01000608, // ARP(0x0806) 37 0x04060008, 38 0x00000100, // sender MAC Address: 00 00 39 0x12345678, // sender MAC Address: 12 34 56 78 40 0xeb00a8c0, // sender IP Address: 192.168.0.235 (C0.A8.0.EB) 41 0x00000000, // target MAC Address: 00 00 00 00 42 0xa8c00000, // target MAC Address: 00 00, target IP Address:192.168 43 0x00005c00, // target IP Address: 0.92 (C0.A8.0.5C) 44 // 0x00000100, // target IP Address: 0.1 (C0.A8.0.1) 45 // 0x0000de00, // target IP Address: 0.222 (C0.A8.0.DE) 46 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc68e2bd5}; 47 48 //------------------------------------------------------------ 49 // Read Memory 50 //------------------------------------------------------------ 51 uint32_t Read_Mem_Dat_NCSI_DD(uint32_t addr) 52 { 53 #ifdef MAC_DEBUG_MEMRW_Dat 54 printf("[MEMRd-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( readl(addr) ) ); 55 #endif 56 return ( SWAP_4B_LEDN_MEM( readl(addr) ) ); 57 } 58 59 uint32_t Read_Mem_Des_NCSI_DD(uint32_t addr) 60 { 61 #ifdef MAC_DEBUG_MEMRW_Des 62 printf("[MEMRd-Des] %08x = %08x\n", addr, 63 SWAP_4B_LEDN_MEM(readl(addr))); 64 #endif 65 return (SWAP_4B_LEDN_MEM(readl(addr))); 66 } 67 68 uint32_t Read_Mem_Dat_DD(uint32_t addr) 69 { 70 #ifdef MAC_DEBUG_MEMRW_Dat 71 printf("[MEMRd-Dat] %08x = %08x\n", addr, 72 SWAP_4B_LEDN_MEM(readl(addr))); 73 #endif 74 return (SWAP_4B_LEDN_MEM(readl(addr))); 75 } 76 77 uint32_t Read_Mem_Des_DD(uint32_t addr) 78 { 79 #ifdef MAC_DEBUG_MEMRW_Des 80 printf("[MEMRd-Des] %08x = %08x\n", addr, 81 SWAP_4B_LEDN_MEM(readl(addr))); 82 #endif 83 return (SWAP_4B_LEDN_MEM(readl(addr))); 84 } 85 86 //------------------------------------------------------------ 87 // Read Register 88 //------------------------------------------------------------ 89 uint32_t mac_reg_read(MAC_ENGINE *p_eng, uint32_t addr) 90 { 91 return readl(p_eng->run.mac_base + addr); 92 } 93 94 //------------------------------------------------------------ 95 // Write Memory 96 //------------------------------------------------------------ 97 void Write_Mem_Dat_NCSI_DD (uint32_t addr, uint32_t data) { 98 #ifdef MAC_DEBUG_MEMRW_Dat 99 printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 100 #endif 101 writel(data, addr); 102 } 103 void Write_Mem_Des_NCSI_DD (uint32_t addr, uint32_t data) { 104 #ifdef MAC_DEBUG_MEMRW_Des 105 printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 106 #endif 107 writel(data, addr); 108 } 109 void Write_Mem_Dat_DD (uint32_t addr, uint32_t data) { 110 #ifdef MAC_DEBUG_MEMRW_Dat 111 printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 112 #endif 113 writel(data, addr); 114 } 115 void Write_Mem_Des_DD (uint32_t addr, uint32_t data) { 116 #ifdef MAC_DEBUG_MEMRW_Des 117 printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 118 #endif 119 writel(data, addr); 120 } 121 122 //------------------------------------------------------------ 123 // Write Register 124 //------------------------------------------------------------ 125 void mac_reg_write(MAC_ENGINE *p_eng, uint32_t addr, uint32_t data) 126 { 127 writel(data, p_eng->run.mac_base + addr); 128 } 129 130 131 //------------------------------------------------------------ 132 // Others 133 //------------------------------------------------------------ 134 void debug_pause (void) { 135 #ifdef DbgPrn_Enable_Debug_pause 136 GET_CAHR(); 137 #endif 138 } 139 140 //------------------------------------------------------------ 141 void dump_mac_ROreg(MAC_ENGINE *p_eng) 142 { 143 int i = 0xa0; 144 145 printf("\nMAC%d base 0x%08x", p_eng->run.mac_idx, p_eng->run.mac_base); 146 printf("\n%02x:", i); 147 for (i = 0xa0; i <= 0xc8; i += 4) { 148 printf("%08x ", mac_reg_read(p_eng, i)); 149 if ((i & 0xf) == 0xc) 150 printf("\n%02x:", i + 4); 151 } 152 printf("\n"); 153 } 154 155 //------------------------------------------------------------ 156 // IO delay 157 //------------------------------------------------------------ 158 static void get_mac_1g_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 159 { 160 int tx_d, rx_d; 161 mac_delay_1g_t reg; 162 163 reg.w = readl(addr); 164 tx_d = reg.b.tx_delay_1; 165 rx_d = reg.b.rx_delay_1; 166 #ifdef CONFIG_ASPEED_AST2600 167 if (reg.b.rx_clk_inv_1 == 1) { 168 rx_d = (-1) * rx_d; 169 } 170 #endif 171 *p_tx_d = tx_d; 172 *p_rx_d = rx_d; 173 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 174 rx_d, tx_d); 175 } 176 177 static void get_mac_1g_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 178 { 179 int tx_d, rx_d; 180 mac_delay_1g_t reg; 181 182 reg.w = readl(addr); 183 tx_d = reg.b.tx_delay_2; 184 rx_d = reg.b.rx_delay_2; 185 #ifdef CONFIG_ASPEED_AST2600 186 if (reg.b.rx_clk_inv_2 == 1) { 187 rx_d = (-1) * rx_d; 188 } 189 #endif 190 *p_tx_d = tx_d; 191 *p_rx_d = rx_d; 192 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 193 rx_d, tx_d); 194 } 195 196 static void get_mac_100_10_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 197 { 198 int tx_d, rx_d; 199 mac_delay_100_10_t reg; 200 201 reg.w = readl(addr); 202 tx_d = reg.b.tx_delay_1; 203 rx_d = reg.b.rx_delay_1; 204 #ifdef CONFIG_ASPEED_AST2600 205 if (reg.b.rx_clk_inv_1 == 1) { 206 rx_d = (-1) * rx_d; 207 } 208 #endif 209 *p_tx_d = tx_d; 210 *p_rx_d = rx_d; 211 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 212 rx_d, tx_d); 213 } 214 215 static void get_mac_100_10_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 216 { 217 int tx_d, rx_d; 218 mac_delay_100_10_t reg; 219 220 reg.w = readl(addr); 221 tx_d = reg.b.tx_delay_2; 222 rx_d = reg.b.rx_delay_2; 223 #ifdef CONFIG_ASPEED_AST2600 224 if (reg.b.rx_clk_inv_2 == 1) { 225 rx_d = (-1) * rx_d; 226 } 227 #endif 228 *p_tx_d = tx_d; 229 *p_rx_d = rx_d; 230 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 231 rx_d, tx_d); 232 } 233 234 static void get_mac_rmii_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 235 { 236 mac_delay_1g_t reg; 237 238 reg.w = readl(addr); 239 *p_rx_d = reg.b.rx_delay_1; 240 *p_tx_d = reg.b.rmii_tx_data_at_falling_1; 241 242 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 243 *p_rx_d, *p_tx_d); 244 } 245 static void get_mac_rmii_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 246 { 247 mac_delay_1g_t reg; 248 249 reg.w = readl(addr); 250 *p_rx_d = reg.b.rx_delay_2; 251 *p_tx_d = reg.b.rmii_tx_data_at_falling_2; 252 253 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 254 *p_rx_d, *p_tx_d); 255 } 256 257 static 258 void get_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 259 { 260 get_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 261 } 262 static 263 void get_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 264 { 265 get_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d); 266 } 267 static 268 void get_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 269 { 270 get_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d); 271 } 272 static 273 void get_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 274 { 275 get_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 276 } 277 static 278 void get_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 279 { 280 get_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d); 281 } 282 static 283 void get_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 284 { 285 get_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d); 286 } 287 static 288 void get_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 289 { 290 get_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 291 } 292 static 293 void get_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 294 { 295 get_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d); 296 } 297 static 298 void get_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 299 { 300 get_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d); 301 } 302 static 303 void get_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 304 { 305 get_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 306 } 307 static 308 void get_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 309 { 310 get_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d); 311 } 312 static 313 void get_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 314 { 315 get_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d); 316 } 317 static 318 void get_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 319 { 320 get_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 321 } 322 static 323 void get_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 324 { 325 get_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 326 } 327 static 328 void get_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 329 { 330 get_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 331 } 332 static 333 void get_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 334 { 335 get_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 336 } 337 static 338 void get_dummy_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 339 { 340 debug("%s\n", __func__); 341 } 342 343 /** 344 * @brief function pointer table to get current delay setting 345 * 346 * get_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m] 347 */ 348 typedef void (*pfn_get_delay) (MAC_ENGINE *, int32_t *, int32_t *); 349 pfn_get_delay get_delay_func_tbl[2][4][3] = { 350 { 351 {get_mac1_rmii_delay, get_mac1_rmii_delay, get_mac1_rmii_delay}, 352 {get_mac2_rmii_delay, get_mac2_rmii_delay, get_mac2_rmii_delay}, 353 #if defined(CONFIG_ASPEED_AST2600) 354 {get_mac3_rmii_delay, get_mac3_rmii_delay, get_mac3_rmii_delay}, 355 {get_mac4_rmii_delay, get_mac4_rmii_delay, get_mac4_rmii_delay}, 356 #else 357 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 358 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 359 #endif 360 }, 361 { 362 {get_mac1_1g_delay, get_mac1_100m_delay, get_mac1_10m_delay}, 363 {get_mac2_1g_delay, get_mac2_100m_delay, get_mac2_10m_delay}, 364 #if defined(CONFIG_ASPEED_AST2600) 365 {get_mac3_1g_delay, get_mac3_100m_delay, get_mac3_10m_delay}, 366 {get_mac4_1g_delay, get_mac4_100m_delay, get_mac4_10m_delay}, 367 #else 368 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 369 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 370 #endif 371 } 372 }; 373 void mac_get_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 374 { 375 #if 1 376 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 377 uint32_t mac_idx = p_eng->run.mac_idx; 378 uint32_t speed_idx = p_eng->run.speed_idx; 379 380 get_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, p_rx_d, p_tx_d); 381 #else 382 /* for test */ 383 uint32_t rgmii; 384 uint32_t mac_idx; 385 uint32_t speed_idx; 386 for (rgmii = 0; rgmii < 2; rgmii++) 387 for (mac_idx = 0; mac_idx < 4; mac_idx++) 388 for (speed_idx = 0; speed_idx < 3; speed_idx++) 389 get_delay_func_tbl[rgmii][mac_idx][speed_idx]( 390 p_eng, p_rx_d, p_tx_d); 391 #endif 392 } 393 394 void mac_get_max_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 395 { 396 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 397 uint32_t mac_idx = p_eng->run.mac_idx; 398 int32_t tx_max, rx_max; 399 400 if (rgmii) { 401 if (mac_idx > 1) { 402 tx_max = p_eng->io.mac34_1g_delay.tx_max; 403 rx_max = p_eng->io.mac34_1g_delay.rx_max; 404 } else { 405 tx_max = p_eng->io.mac12_1g_delay.tx_max; 406 rx_max = p_eng->io.mac12_1g_delay.rx_max; 407 } 408 } else { 409 if (mac_idx > 1) { 410 tx_max = p_eng->io.mac34_1g_delay.rmii_tx_max; 411 rx_max = p_eng->io.mac34_1g_delay.rmii_rx_max; 412 } else { 413 tx_max = p_eng->io.mac12_1g_delay.rmii_tx_max; 414 rx_max = p_eng->io.mac12_1g_delay.rmii_rx_max; 415 } 416 } 417 *p_tx_d = tx_max; 418 *p_rx_d = rx_max; 419 } 420 421 void mac_get_min_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 422 { 423 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 424 uint32_t mac_idx = p_eng->run.mac_idx; 425 int32_t tx_min, rx_min; 426 427 if (rgmii) { 428 if (mac_idx > 1) { 429 tx_min = p_eng->io.mac34_1g_delay.tx_min; 430 rx_min = p_eng->io.mac34_1g_delay.rx_min; 431 } else { 432 tx_min = p_eng->io.mac12_1g_delay.tx_min; 433 rx_min = p_eng->io.mac12_1g_delay.rx_min; 434 } 435 } else { 436 if (mac_idx > 1) { 437 tx_min = p_eng->io.mac34_1g_delay.rmii_tx_min; 438 rx_min = p_eng->io.mac34_1g_delay.rmii_rx_min; 439 } else { 440 tx_min = p_eng->io.mac12_1g_delay.rmii_tx_min; 441 rx_min = p_eng->io.mac12_1g_delay.rmii_rx_min; 442 } 443 } 444 *p_tx_d = tx_min; 445 *p_rx_d = rx_min; 446 } 447 448 static void set_mac_1g_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 449 { 450 mac_delay_1g_t reg; 451 452 reg.w = readl(addr); 453 #ifdef CONFIG_ASPEED_AST2600 454 if (rx_d < 0) { 455 reg.b.rx_clk_inv_1 = 1; 456 rx_d = abs(rx_d); 457 } 458 #endif 459 reg.b.rx_delay_1 = rx_d; 460 reg.b.tx_delay_1 = tx_d; 461 writel(reg.w, addr); 462 463 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 464 rx_d, tx_d); 465 } 466 467 static void set_mac_1g_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 468 { 469 mac_delay_1g_t reg; 470 471 reg.w = readl(addr); 472 #ifdef CONFIG_ASPEED_AST2600 473 if (rx_d < 0) { 474 reg.b.rx_clk_inv_2 = 1; 475 rx_d = abs(rx_d); 476 } 477 #endif 478 reg.b.rx_delay_2 = rx_d; 479 reg.b.tx_delay_2 = tx_d; 480 writel(reg.w, addr); 481 482 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 483 rx_d, tx_d); 484 } 485 486 static void set_mac_100_10_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 487 { 488 mac_delay_100_10_t reg; 489 490 reg.w = readl(addr); 491 #ifdef CONFIG_ASPEED_AST2600 492 if (rx_d < 0) { 493 reg.b.rx_clk_inv_1 = 1; 494 rx_d = abs(rx_d); 495 } 496 #endif 497 reg.b.rx_delay_1 = rx_d; 498 reg.b.tx_delay_1 = tx_d; 499 writel(reg.w, addr); 500 501 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 502 rx_d, tx_d); 503 } 504 505 static void set_mac_100_10_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 506 { 507 mac_delay_100_10_t reg; 508 509 reg.w = readl(addr); 510 #ifdef CONFIG_ASPEED_AST2600 511 if (rx_d < 0) { 512 reg.b.rx_clk_inv_2 = 1; 513 rx_d = abs(rx_d); 514 } 515 #endif 516 reg.b.rx_delay_2 = rx_d; 517 reg.b.tx_delay_2 = tx_d; 518 writel(reg.w, addr); 519 520 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 521 rx_d, tx_d); 522 } 523 524 static void set_mac_rmii_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 525 { 526 mac_delay_1g_t reg; 527 528 reg.w = readl(addr); 529 reg.b.rmii_tx_data_at_falling_1 = tx_d; 530 reg.b.rx_delay_1 = rx_d; 531 writel(reg.w, addr); 532 533 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 534 rx_d, tx_d); 535 } 536 537 static void set_mac_rmii_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 538 { 539 mac_delay_1g_t reg; 540 541 reg.w = readl(addr); 542 reg.b.rmii_tx_data_at_falling_2 = tx_d; 543 reg.b.rx_delay_2 = rx_d; 544 writel(reg.w, addr); 545 546 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 547 rx_d, tx_d); 548 } 549 550 551 static void set_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 552 { 553 set_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 554 } 555 static void set_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 556 { 557 set_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d); 558 } 559 static void set_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 560 { 561 set_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d); 562 } 563 static void set_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 564 { 565 set_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 566 } 567 static void set_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 568 { 569 set_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d); 570 } 571 static void set_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 572 { 573 set_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d); 574 } 575 static void set_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 576 { 577 set_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 578 } 579 static void set_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 580 { 581 set_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d); 582 } 583 static void set_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 584 { 585 set_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d); 586 } 587 static void set_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 588 { 589 set_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 590 } 591 static void set_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 592 { 593 set_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d); 594 } 595 static void set_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 596 { 597 set_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d); 598 } 599 static void set_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 600 { 601 set_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 602 } 603 static void set_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 604 { 605 set_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 606 } 607 608 static void set_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 609 { 610 set_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 611 } 612 613 static void set_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 614 { 615 set_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 616 } 617 618 void set_dummy_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 619 { 620 printf("%s: %d, %d\n", __func__, rx_d, tx_d); 621 } 622 623 /** 624 * @brief function pointer table for delay setting 625 * 626 * set_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m] 627 */ 628 typedef void (*pfn_set_delay) (MAC_ENGINE *, int32_t, int32_t); 629 pfn_set_delay set_delay_func_tbl[2][4][3] = { 630 { 631 {set_mac1_rmii_delay, set_mac1_rmii_delay, set_mac1_rmii_delay}, 632 {set_mac2_rmii_delay, set_mac2_rmii_delay, set_mac2_rmii_delay}, 633 #if defined(CONFIG_ASPEED_AST2600) 634 {set_mac3_rmii_delay, set_mac3_rmii_delay, set_mac3_rmii_delay}, 635 {set_mac4_rmii_delay, set_mac4_rmii_delay, set_mac4_rmii_delay}, 636 #else 637 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 638 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 639 #endif 640 }, 641 { 642 {set_mac1_1g_delay, set_mac1_100m_delay, set_mac1_10m_delay}, 643 {set_mac2_1g_delay, set_mac2_100m_delay, set_mac2_10m_delay}, 644 #if defined(CONFIG_ASPEED_AST2600) 645 {set_mac3_1g_delay, set_mac3_100m_delay, set_mac3_10m_delay}, 646 {set_mac4_1g_delay, set_mac4_100m_delay, set_mac4_10m_delay}, 647 #else 648 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 649 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 650 #endif 651 } 652 }; 653 654 void mac_set_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 655 { 656 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 657 uint32_t mac_idx = p_eng->run.mac_idx; 658 uint32_t speed_idx = p_eng->run.speed_idx; 659 660 set_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, rx_d, tx_d); 661 } 662 663 uint32_t mac_get_driving_strength(MAC_ENGINE *p_eng) 664 { 665 #ifdef CONFIG_ASPEED_AST2600 666 mac34_drv_t reg; 667 668 reg.w = readl(p_eng->io.mac34_drv_reg.addr); 669 /* ast2600 : only MAC#3 & MAC#4 have driving strength setting */ 670 if (p_eng->run.mac_idx == 2) { 671 return (reg.b.mac3_tx_drv); 672 } else if (p_eng->run.mac_idx == 3) { 673 return (reg.b.mac4_tx_drv); 674 } else { 675 return 0; 676 } 677 #else 678 mac12_drv_t reg; 679 680 reg.w = readl(p_eng->io.mac12_drv_reg.addr); 681 682 if (p_eng->run.mac_idx == 0) { 683 return (reg.b.mac1_tx_drv); 684 } else if (p_eng->run.mac_idx == 1) { 685 return (reg.b.mac2_tx_drv); 686 } else { 687 return 0; 688 } 689 #endif 690 } 691 void mac_set_driving_strength(MAC_ENGINE *p_eng, uint32_t strength) 692 { 693 #ifdef CONFIG_ASPEED_AST2600 694 mac34_drv_t reg; 695 696 if (strength > p_eng->io.mac34_drv_reg.drv_max) { 697 printf("invalid driving strength value\n"); 698 return; 699 } 700 701 /** 702 * read->modify->write for driving strength control register 703 * ast2600 : only MAC#3 & MAC#4 have driving strength setting 704 */ 705 reg.w = readl(p_eng->io.mac34_drv_reg.addr); 706 707 /* ast2600 : only MAC#3 & MAC#4 have driving strength setting */ 708 if (p_eng->run.mac_idx == 2) { 709 reg.b.mac3_tx_drv = strength; 710 } else if (p_eng->run.mac_idx == 3) { 711 reg.b.mac4_tx_drv = strength; 712 } 713 714 writel(reg.w, p_eng->io.mac34_drv_reg.addr); 715 #else 716 mac12_drv_t reg; 717 718 if (strength > p_eng->io.mac12_drv_reg.drv_max) { 719 printf("invalid driving strength value\n"); 720 return; 721 } 722 723 /* read->modify->write for driving strength control register */ 724 reg.w = readl(p_eng->io.mac12_drv_reg.addr); 725 if (p_eng->run.is_rgmii) { 726 if (p_eng->run.mac_idx == 0) { 727 reg.b.mac1_rgmii_tx_drv = 728 strength; 729 } else if (p_eng->run.mac_idx == 2) { 730 reg.b.mac2_rgmii_tx_drv = 731 strength; 732 } 733 } else { 734 if (p_eng->run.mac_idx == 0) { 735 reg.b.mac1_rmii_tx_drv = 736 strength; 737 } else if (p_eng->run.mac_idx == 1) { 738 reg.b.mac2_rmii_tx_drv = 739 strength; 740 } 741 } 742 writel(reg.w, p_eng->io.mac12_drv_reg.addr); 743 #endif 744 } 745 746 void mac_set_rmii_50m_output_enable(MAC_ENGINE *p_eng) 747 { 748 uint32_t addr; 749 mac_delay_1g_t value; 750 751 if (p_eng->run.mac_idx > 1) { 752 addr = p_eng->io.mac34_1g_delay.addr; 753 } else { 754 addr = p_eng->io.mac12_1g_delay.addr; 755 } 756 757 value.w = readl(addr); 758 if (p_eng->run.mac_idx & BIT(0)) { 759 value.b.rmii_50m_oe_2 = 1; 760 } else { 761 value.b.rmii_50m_oe_1 = 1; 762 } 763 writel(value.w, addr); 764 } 765 766 //------------------------------------------------------------ 767 int mac_set_scan_boundary(MAC_ENGINE *p_eng) 768 { 769 int32_t rx_cur, tx_cur; 770 int32_t rx_min, rx_max, tx_min, tx_max; 771 int32_t rx_scaling, tx_scaling; 772 773 nt_log_func_name(); 774 775 /* get current delay setting */ 776 mac_get_delay(p_eng, &rx_cur, &tx_cur); 777 778 /* get physical boundaries */ 779 mac_get_max_available_delay(p_eng, &rx_max, &tx_max); 780 mac_get_min_available_delay(p_eng, &rx_min, &tx_min); 781 782 if ((p_eng->run.is_rgmii) && (p_eng->arg.ctrl.b.inv_rgmii_rxclk)) { 783 rx_max = (rx_max > 0) ? 0 : rx_max; 784 } else { 785 rx_min = (rx_min < 0) ? 0 : rx_min; 786 } 787 788 if (p_eng->run.TM_IOTiming) { 789 if (p_eng->arg.ctrl.b.full_range) { 790 tx_scaling = 0; 791 rx_scaling = 0; 792 } else { 793 /* down-scaling to save test time */ 794 tx_scaling = TX_DELAY_SCALING; 795 rx_scaling = RX_DELAY_SCALING; 796 } 797 p_eng->io.rx_delay_scan.step = 1; 798 p_eng->io.tx_delay_scan.step = 1; 799 p_eng->io.rx_delay_scan.begin = rx_min >> rx_scaling; 800 p_eng->io.rx_delay_scan.end = rx_max >> rx_scaling; 801 p_eng->io.tx_delay_scan.begin = tx_min >> tx_scaling; 802 p_eng->io.tx_delay_scan.end = tx_max >> tx_scaling; 803 } else if (p_eng->run.delay_margin) { 804 p_eng->io.rx_delay_scan.step = 1; 805 p_eng->io.tx_delay_scan.step = 1; 806 p_eng->io.rx_delay_scan.begin = rx_cur - p_eng->run.delay_margin; 807 p_eng->io.rx_delay_scan.end = rx_cur + p_eng->run.delay_margin; 808 p_eng->io.tx_delay_scan.begin = tx_cur - p_eng->run.delay_margin; 809 p_eng->io.tx_delay_scan.end = tx_cur + p_eng->run.delay_margin; 810 } else { 811 p_eng->io.rx_delay_scan.step = 1; 812 p_eng->io.tx_delay_scan.step = 1; 813 p_eng->io.rx_delay_scan.begin = 0; 814 p_eng->io.rx_delay_scan.end = 0; 815 p_eng->io.tx_delay_scan.begin = 0; 816 p_eng->io.tx_delay_scan.end = 0; 817 } 818 819 /* backup current setting as the original for plotting result */ 820 p_eng->io.rx_delay_scan.orig = rx_cur; 821 p_eng->io.tx_delay_scan.orig = tx_cur; 822 823 /* check if setting is legal or not */ 824 if (p_eng->io.rx_delay_scan.begin < rx_min) 825 p_eng->io.rx_delay_scan.begin = rx_min; 826 827 if (p_eng->io.tx_delay_scan.begin < tx_min) 828 p_eng->io.tx_delay_scan.begin = tx_min; 829 830 if (p_eng->io.rx_delay_scan.end > rx_max) 831 p_eng->io.rx_delay_scan.end = rx_max; 832 833 if (p_eng->io.tx_delay_scan.end > tx_max) 834 p_eng->io.tx_delay_scan.end = tx_max; 835 836 if (p_eng->io.rx_delay_scan.begin > p_eng->io.rx_delay_scan.end) 837 p_eng->io.rx_delay_scan.begin = p_eng->io.rx_delay_scan.end; 838 839 if (p_eng->io.tx_delay_scan.begin > p_eng->io.tx_delay_scan.end) 840 p_eng->io.tx_delay_scan.begin = p_eng->io.tx_delay_scan.end; 841 842 if (p_eng->run.IO_MrgChk) { 843 if ((p_eng->io.rx_delay_scan.orig < 844 p_eng->io.rx_delay_scan.begin) || 845 (p_eng->io.rx_delay_scan.orig > 846 p_eng->io.rx_delay_scan.end)) { 847 printf("Warning: current delay is not in the " 848 "scan-range\n"); 849 printf("RX delay scan range:%d ~ %d, curr:%d\n", 850 p_eng->io.rx_delay_scan.begin, 851 p_eng->io.rx_delay_scan.end, 852 p_eng->io.rx_delay_scan.orig); 853 printf("TX delay scan range:%d ~ %d, curr:%d\n", 854 p_eng->io.tx_delay_scan.begin, 855 p_eng->io.tx_delay_scan.end, 856 p_eng->io.tx_delay_scan.orig); 857 } 858 } 859 860 return (0); 861 } 862 863 //------------------------------------------------------------ 864 // MAC 865 //------------------------------------------------------------ 866 void mac_set_addr(MAC_ENGINE *p_eng) 867 { 868 nt_log_func_name(); 869 870 uint32_t madr = p_eng->reg.mac_madr; 871 uint32_t ladr = p_eng->reg.mac_ladr; 872 873 if (((madr == 0x0000) && (ladr == 0x00000000)) || 874 ((madr == 0xffff) && (ladr == 0xffffffff))) { 875 /* FIXME: shall use random gen */ 876 madr = 0x0000000a; 877 ladr = 0xf7837dd4; 878 } 879 880 printf("%s: madr:%08x ladr:%08x\n", __func__, madr, ladr); 881 882 p_eng->inf.SA[0] = (madr >> 8) & 0xff; // MSB 883 p_eng->inf.SA[1] = (madr >> 0) & 0xff; 884 p_eng->inf.SA[2] = (ladr >> 24) & 0xff; 885 p_eng->inf.SA[3] = (ladr >> 16) & 0xff; 886 p_eng->inf.SA[4] = (ladr >> 8) & 0xff; 887 p_eng->inf.SA[5] = (ladr >> 0) & 0xff; // LSB 888 889 printf("%s: [0]:%02x [1]:%02x\n", __func__, p_eng->inf.SA[0], p_eng->inf.SA[1]); 890 printf("%s: [2]:%02x [3]:%02x\n", __func__, p_eng->inf.SA[2], p_eng->inf.SA[3]); 891 printf("%s: [4]:%02x [5]:%02x\n", __func__, p_eng->inf.SA[4], p_eng->inf.SA[5]); 892 } 893 894 void mac_set_interal_loopback(MAC_ENGINE *p_eng) 895 { 896 uint32_t reg = mac_reg_read(p_eng, 0x40); 897 mac_reg_write(p_eng, 0x40, reg | BIT(30)); 898 } 899 900 //------------------------------------------------------------ 901 void init_mac (MAC_ENGINE *eng) 902 { 903 nt_log_func_name(); 904 905 mac_cr_t maccr; 906 907 #ifdef Enable_MAC_SWRst 908 maccr.w = 0; 909 maccr.b.sw_rst = 1; 910 mac_reg_write(eng, 0x50, maccr.w); 911 912 do { 913 DELAY(Delay_MACRst); 914 maccr.w = mac_reg_read(eng, 0x50); 915 } while(maccr.b.sw_rst); 916 #endif 917 918 mac_reg_write(eng, 0x20, eng->run.tdes_base - ASPEED_DRAM_BASE); 919 mac_reg_write(eng, 0x24, eng->run.rdes_base - ASPEED_DRAM_BASE); 920 921 mac_reg_write(eng, 0x08, eng->reg.mac_madr); 922 mac_reg_write(eng, 0x0c, eng->reg.mac_ladr); 923 924 #ifdef MAC_030_def 925 mac_reg_write( eng, 0x30, MAC_030_def );//Int Thr/Cnt 926 #endif 927 #ifdef MAC_034_def 928 mac_reg_write( eng, 0x34, MAC_034_def );//Poll Cnt 929 #endif 930 #ifdef MAC_038_def 931 mac_reg_write( eng, 0x38, MAC_038_def ); 932 #endif 933 #ifdef MAC_048_def 934 mac_reg_write( eng, 0x48, MAC_048_def ); 935 #endif 936 #ifdef MAC_058_def 937 mac_reg_write( eng, 0x58, MAC_058_def ); 938 #endif 939 940 if ( eng->arg.run_mode == MODE_NCSI ) 941 mac_reg_write( eng, 0x4c, NCSI_RxDMA_PakSize ); 942 else 943 mac_reg_write( eng, 0x4c, DMA_PakSize ); 944 945 maccr.b.txdma_en = 1; 946 maccr.b.rxdma_en = 1; 947 maccr.b.txmac_en = 1; 948 maccr.b.rxmac_en = 1; 949 maccr.b.fulldup = 1; 950 maccr.b.crc_apd = 1; 951 952 if (eng->run.speed_sel[0]) { 953 maccr.b.gmac_mode = 1; 954 } else if (eng->run.speed_sel[1]) { 955 maccr.b.speed_100 = 1; 956 } 957 958 if (eng->arg.run_mode == MODE_NCSI) { 959 maccr.b.rx_broadpkt_en = 1; 960 maccr.b.speed_100 = 1; 961 } 962 else { 963 maccr.b.rx_alladr = 1; 964 #ifdef Enable_Runt 965 maccr.b.rx_runt = 1; 966 #endif 967 } 968 mac_reg_write(eng, 0x50, maccr.w); 969 DELAY(Delay_MACRst); 970 } // End void init_mac (MAC_ENGINE *eng) 971 972 //------------------------------------------------------------ 973 // Basic 974 //------------------------------------------------------------ 975 void FPri_RegValue (MAC_ENGINE *eng, uint8_t option) 976 { 977 nt_log_func_name(); 978 979 PRINTF( option, "[SRAM] Date:%08x\n", SRAM_RD( 0x88 ) ); 980 PRINTF( option, "[SRAM] 80:%08x %08x %08x %08x\n", SRAM_RD( 0x80 ), SRAM_RD( 0x84 ), SRAM_RD( 0x88 ), SRAM_RD( 0x8c ) ); 981 982 PRINTF( option, "[SCU] a0:%08x a4:%08x b8:%08x bc:%08x\n", SCU_RD( 0x0a0 ), SCU_RD( 0x0a4 ), SCU_RD( 0x0b8 ), SCU_RD( 0x0bc )); 983 984 PRINTF( option, "[SCU] 13c:%08x 140:%08x 144:%08x 1dc:%08x\n", SCU_RD( 0x13c ), SCU_RD( 0x140 ), SCU_RD( 0x144 ), SCU_RD( 0x1dc ) ); 985 PRINTF( option, "[WDT] 0c:%08x 2c:%08x 4c:%08x\n", eng->reg.WDT_00c, eng->reg.WDT_02c, eng->reg.WDT_04c ); 986 PRINTF( option, "[MAC] A0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xa0 ), mac_reg_read( eng, 0xa4 ), mac_reg_read( eng, 0xa8 ), mac_reg_read( eng, 0xac ) ); 987 PRINTF( option, "[MAC] B0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xb0 ), mac_reg_read( eng, 0xb4 ), mac_reg_read( eng, 0xb8 ), mac_reg_read( eng, 0xbc ) ); 988 PRINTF( option, "[MAC] C0|%08x %08x %08x\n", mac_reg_read( eng, 0xc0 ), mac_reg_read( eng, 0xc4 ), mac_reg_read( eng, 0xc8 ) ); 989 990 } // End void FPri_RegValue (MAC_ENGINE *eng, uint8_t *fp) 991 992 //------------------------------------------------------------ 993 void FPri_End (MAC_ENGINE *eng, uint8_t option) 994 { 995 nt_log_func_name(); 996 if ((0 == eng->run.is_rgmii) && (eng->phy.RMIICK_IOMode != 0) && 997 eng->run.IO_MrgChk && eng->flg.all_fail) { 998 if ( eng->arg.ctrl.b.rmii_phy_in == 0 ) { 999 PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the OUTPUT mode now.\n" ); 1000 PRINTF( option, " Maybe you can run the INPUT mode command \"mactest %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w | 0x80), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range ); 1001 } 1002 else { 1003 PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the INPUT mode now.\n" ); 1004 PRINTF( option, " Maybe you can run the OUTPUT mode command \"mactest %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w & 0x7f), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range ); 1005 } 1006 } 1007 1008 if (!eng->run.TM_RxDataEn) { 1009 } else if (eng->flg.Err_Flag) { 1010 PRINTF(option, " \n----> fail !!!\n"); 1011 } 1012 1013 //------------------------------ 1014 //[Warning] PHY Address 1015 //------------------------------ 1016 if ( eng->arg.run_mode == MODE_DEDICATED ) { 1017 if ( eng->arg.phy_addr != eng->phy.Adr ) 1018 PRINTF( option, "\n[Warning] PHY Address change from %d to %d !!!\n", eng->arg.phy_addr, eng->phy.Adr ); 1019 } 1020 1021 //------------------------------ 1022 //[Warning] IO Strength 1023 //------------------------------ 1024 #ifdef CONFIG_ASPEED_AST2600 1025 if (eng->io.init_done && (eng->io.mac34_drv_reg.value.w != 0xf)) { 1026 PRINTF(option, 1027 "\n[Warning] [%08X] 0x%08x is not the suggestion value " 1028 "0xf.\n", 1029 eng->io.mac34_drv_reg.addr, 1030 eng->io.mac34_drv_reg.value.w); 1031 #else 1032 if (eng->io.init_done && eng->io.mac12_drv_reg.value.w) { 1033 PRINTF(option, 1034 "\n[Warning] [%08X] 0x%08x is not the suggestion value " 1035 "0.\n", 1036 eng->io.mac12_drv_reg.addr, 1037 eng->io.mac12_drv_reg.value.w); 1038 #endif 1039 PRINTF(option, " This change at this platform must " 1040 "been proven again by the ASPEED.\n"); 1041 } 1042 1043 //------------------------------ 1044 //[Warning] IO Timing 1045 //------------------------------ 1046 if ( eng->arg.run_mode == MODE_NCSI ) { 1047 PRINTF( option, "\n[Arg] %d %d %d %d %d %d %d {%d}\n", eng->arg.mac_idx, eng->arg.GPackageTolNum, eng->arg.GChannelTolNum, eng->arg.test_mode, eng->arg.delay_scan_range, eng->arg.ctrl.w, eng->arg.GARPNumCnt, TIME_OUT_NCSI ); 1048 1049 switch ( eng->ncsi_cap.PCI_DID_VID ) { 1050 case PCI_DID_VID_Intel_82574L : { PRINTF( option, "[NC]%08x %08x: Intel 82574L \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1051 case PCI_DID_VID_Intel_82575_10d6 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1052 case PCI_DID_VID_Intel_82575_10a7 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1053 case PCI_DID_VID_Intel_82575_10a9 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1054 case PCI_DID_VID_Intel_82576_10c9 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1055 case PCI_DID_VID_Intel_82576_10e6 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1056 case PCI_DID_VID_Intel_82576_10e7 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1057 case PCI_DID_VID_Intel_82576_10e8 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1058 case PCI_DID_VID_Intel_82576_1518 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1059 case PCI_DID_VID_Intel_82576_1526 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1060 case PCI_DID_VID_Intel_82576_150a : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1061 case PCI_DID_VID_Intel_82576_150d : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1062 case PCI_DID_VID_Intel_82599_10fb : { PRINTF( option, "[NC]%08x %08x: Intel 82599 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1063 case PCI_DID_VID_Intel_82599_1557 : { PRINTF( option, "[NC]%08x %08x: Intel 82599 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1064 case PCI_DID_VID_Intel_I210_1533 : { PRINTF( option, "[NC]%08x %08x: Intel I210 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1065 case PCI_DID_VID_Intel_I210_1537 : { PRINTF( option, "[NC]%08x %08x: Intel I210 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1066 case PCI_DID_VID_Intel_I350_1521 : { PRINTF( option, "[NC]%08x %08x: Intel I350 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1067 case PCI_DID_VID_Intel_I350_1523 : { PRINTF( option, "[NC]%08x %08x: Intel I350 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1068 case PCI_DID_VID_Intel_X540 : { PRINTF( option, "[NC]%08x %08x: Intel X540 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1069 case PCI_DID_VID_Intel_X550 : { PRINTF( option, "[NC]%08x %08x: Intel X550 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1070 case PCI_DID_VID_Intel_Broadwell_DE : { PRINTF( option, "[NC]%08x %08x: Intel Broadwell-DE \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1071 case PCI_DID_VID_Intel_X722_37d0 : { PRINTF( option, "[NC]%08x %08x: Intel X722 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1072 case PCI_DID_VID_Broadcom_BCM5718 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5718 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1073 case PCI_DID_VID_Broadcom_BCM5719 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5719 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1074 case PCI_DID_VID_Broadcom_BCM5720 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5720 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1075 case PCI_DID_VID_Broadcom_BCM5725 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5725 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1076 case PCI_DID_VID_Broadcom_BCM57810S : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57810S \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1077 case PCI_DID_VID_Broadcom_Cumulus : { PRINTF( option, "[NC]%08x %08x: Broadcom Cumulus \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1078 case PCI_DID_VID_Broadcom_BCM57302 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57302 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1079 case PCI_DID_VID_Broadcom_BCM957452 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM957452 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1080 case PCI_DID_VID_Mellanox_ConnectX_3_1003 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1081 case PCI_DID_VID_Mellanox_ConnectX_3_1007 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1082 case PCI_DID_VID_Mellanox_ConnectX_4 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-4\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1083 default: 1084 switch ( eng->ncsi_cap.manufacturer_id ) { 1085 case ManufacturerID_Intel : { PRINTF( option, "[NC]%08x %08x: Intel \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1086 case ManufacturerID_Broadcom : { PRINTF( option, "[NC]%08x %08x: Broadcom \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1087 case ManufacturerID_Mellanox : { PRINTF( option, "[NC]%08x %08x: Mellanox \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1088 case ManufacturerID_Mellanox1: { PRINTF( option, "[NC]%08x %08x: Mellanox \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1089 case ManufacturerID_Emulex : { PRINTF( option, "[NC]%08x %08x: Emulex \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1090 default : { PRINTF( option, "[NC]%08x %08x \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1091 } // End switch ( eng->ncsi_cap.manufacturer_id ) 1092 } // End switch ( eng->ncsi_cap.PCI_DID_VID ) 1093 } 1094 else { 1095 PRINTF(option, "[PHY] @addr %d: id = %04x_%04x (%s)\n", 1096 eng->phy.Adr, eng->phy.id1, eng->phy.id2, 1097 eng->phy.phy_name); 1098 } // End if ( eng->arg.run_mode == MODE_NCSI ) 1099 } // End void FPri_End (MAC_ENGINE *eng, uint8_t option) 1100 1101 //------------------------------------------------------------ 1102 void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option) 1103 { 1104 nt_log_func_name(); 1105 if ( eng->flg.print_en ) { 1106 if ( eng->flg.Wrn_Flag ) { 1107 if ( eng->flg.Wrn_Flag & Wrn_Flag_IOMarginOUF ) { 1108 PRINTF(option, "[Warning] IO timing testing " 1109 "range out of boundary\n"); 1110 1111 if (0 == eng->run.is_rgmii) { 1112 PRINTF( option, " (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx, 1113 eng->io.Dly_out_reg_idx, 1114 eng->run.delay_margin, 1115 eng->io.Dly_in_min, 1116 eng->io.Dly_in_max, 1117 eng->io.Dly_out_min ); 1118 } 1119 else { 1120 PRINTF( option, " (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx, 1121 eng->io.Dly_out_reg_idx, 1122 eng->run.delay_margin, 1123 eng->run.delay_margin, 1124 eng->io.Dly_in_min, 1125 eng->io.Dly_in_max, 1126 eng->io.Dly_out_min, 1127 eng->io.Dly_out_max ); 1128 } 1129 } // End if ( eng->flg.Wrn_Flag & Wrn_Flag_IOMarginOUF ) 1130 if ( eng->flg.Wrn_Flag & Wrn_Flag_RxErFloatting ) { 1131 PRINTF( option, "[Warning] NCSI RXER pin may be floatting to the MAC !!!\n" ); 1132 PRINTF( option, " Please contact with the ASPEED Inc. for more help.\n" ); 1133 } // End if ( eng->flg.Wrn_Flag & Wrn_Flag_RxErFloatting ) 1134 } // End if ( eng->flg.Wrn_Flag ) 1135 1136 if ( eng->flg.Err_Flag ) { 1137 PRINTF( option, "\n\n" ); 1138 //PRINTF( option, "Err_Flag: %x\n\n", eng->flg.Err_Flag ); 1139 1140 if ( eng->flg.Err_Flag & Err_Flag_PHY_Type ) { PRINTF( option, "[Err] Unidentifiable PHY \n" ); } 1141 if ( eng->flg.Err_Flag & Err_Flag_MALLOC_FrmSize ) { PRINTF( option, "[Err] Malloc fail at frame size buffer \n" ); } 1142 if ( eng->flg.Err_Flag & Err_Flag_MALLOC_LastWP ) { PRINTF( option, "[Err] Malloc fail at last WP buffer \n" ); } 1143 if ( eng->flg.Err_Flag & Err_Flag_Check_Buf_Data ) { PRINTF( option, "[Err] Received data mismatch \n" ); } 1144 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Check_TxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Tx owner bit in NCSI packet \n" ); } 1145 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Check_RxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Rx owner bit in NCSI packet \n" ); } 1146 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Check_ARPOwnTimeOut) { PRINTF( option, "[Err] Time out of checking ARP owner bit in NCSI packet \n" ); } 1147 if ( eng->flg.Err_Flag & Err_Flag_NCSI_No_PHY ) { PRINTF( option, "[Err] Can not find NCSI PHY \n" ); } 1148 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[Err] NCSI Channel Number Mismatch \n" ); } 1149 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[Err] NCSI Package Number Mismatch \n" ); } 1150 if ( eng->flg.Err_Flag & Err_Flag_PHY_TimeOut_RW ) { PRINTF( option, "[Err] Time out of read/write PHY register \n" ); } 1151 if ( eng->flg.Err_Flag & Err_Flag_PHY_TimeOut_Rst ) { PRINTF( option, "[Err] Time out of reset PHY register \n" ); } 1152 if ( eng->flg.Err_Flag & Err_Flag_RXBUF_UNAVA ) { PRINTF( option, "[Err] MAC00h[2]:Receiving buffer unavailable \n" ); } 1153 if ( eng->flg.Err_Flag & Err_Flag_RPKT_LOST ) { PRINTF( option, "[Err] MAC00h[3]:Received packet lost due to RX FIFO full \n" ); } 1154 if ( eng->flg.Err_Flag & Err_Flag_NPTXBUF_UNAVA ) { PRINTF( option, "[Err] MAC00h[6]:Normal priority transmit buffer unavailable \n" ); } 1155 if ( eng->flg.Err_Flag & Err_Flag_TPKT_LOST ) { PRINTF( option, "[Err] MAC00h[7]:Packets transmitted to Ethernet lost \n" ); } 1156 if ( eng->flg.Err_Flag & Err_Flag_DMABufNum ) { PRINTF( option, "[Err] DMA Buffer is not enough \n" ); } 1157 if ( eng->flg.Err_Flag & Err_Flag_IOMargin ) { PRINTF( option, "[Err] IO timing margin is not enough \n" ); } 1158 1159 if ( eng->flg.Err_Flag & Err_Flag_MHCLK_Ratio ) { 1160 PRINTF( option, "[Err] Error setting of MAC AHB bus clock (SCU08[18:16]) \n" ); 1161 if ( eng->env.at_least_1g_valid ) 1162 { PRINTF( option, " SCU08[18:16] == 0x%01x is not the suggestion value 2.\n", eng->env.MHCLK_Ratio ); } 1163 else 1164 { PRINTF( option, " SCU08[18:16] == 0x%01x is not the suggestion value 4.\n", eng->env.MHCLK_Ratio ); } 1165 } // End if ( eng->flg.Err_Flag & Err_Flag_MHCLK_Ratio ) 1166 1167 if ( eng->flg.Err_Flag & Err_Flag_IOMarginOUF ) { 1168 PRINTF( option, "[Err] IO timing testing range out of boundary\n"); 1169 if (0 == eng->run.is_rgmii) { 1170 PRINTF( option, " (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx, 1171 eng->io.Dly_out_reg_idx, 1172 eng->run.delay_margin, 1173 eng->io.Dly_in_min, 1174 eng->io.Dly_in_max, 1175 eng->io.Dly_out_min ); 1176 } 1177 else { 1178 PRINTF( option, " (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx, 1179 eng->io.Dly_out_reg_idx, 1180 eng->run.delay_margin, 1181 eng->run.delay_margin, 1182 eng->io.Dly_in_min, 1183 eng->io.Dly_in_max, 1184 eng->io.Dly_out_min, 1185 eng->io.Dly_out_max ); 1186 } 1187 } // End if ( eng->flg.Err_Flag & Err_Flag_IOMarginOUF ) 1188 1189 if ( eng->flg.Err_Flag & Err_Flag_Check_Des ) { 1190 PRINTF( option, "[Err] Descriptor error\n"); 1191 if ( eng->flg.Des_Flag & Des_Flag_TxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Tx owner bit\n" ); } 1192 if ( eng->flg.Des_Flag & Des_Flag_RxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Rx owner bit\n" ); } 1193 if ( eng->flg.Des_Flag & Des_Flag_FrameLen ) { PRINTF( option, "[Des] Frame length mismatch \n" ); } 1194 if ( eng->flg.Des_Flag & Des_Flag_RxErr ) { PRINTF( option, "[Des] Input signal RxErr \n" ); } 1195 if ( eng->flg.Des_Flag & Des_Flag_CRC ) { PRINTF( option, "[Des] CRC error of frame \n" ); } 1196 if ( eng->flg.Des_Flag & Des_Flag_FTL ) { PRINTF( option, "[Des] Frame too long \n" ); } 1197 if ( eng->flg.Des_Flag & Des_Flag_Runt ) { PRINTF( option, "[Des] Runt packet \n" ); } 1198 if ( eng->flg.Des_Flag & Des_Flag_OddNibble ) { PRINTF( option, "[Des] Nibble bit happen \n" ); } 1199 if ( eng->flg.Des_Flag & Des_Flag_RxFIFOFull ) { PRINTF( option, "[Des] Rx FIFO full \n" ); } 1200 } // End if ( eng->flg.Err_Flag & Err_Flag_Check_Des ) 1201 1202 if ( eng->flg.Err_Flag & Err_Flag_MACMode ) { 1203 PRINTF( option, "[Err] MAC interface mode mismatch\n" ); 1204 for (int i = 0; i < 4; i++) { 1205 if (eng->env.is_1g_valid[i]) { 1206 PRINTF(option, 1207 "[MAC%d] is RGMII\n", i); 1208 } else { 1209 PRINTF(option, 1210 "[MAC%d] RMII\n", i); 1211 } 1212 } 1213 } // End if ( eng->flg.Err_Flag & Err_Flag_MACMode ) 1214 1215 if ( eng->arg.run_mode == MODE_NCSI ) { 1216 if ( eng->flg.Err_Flag & Err_Flag_NCSI_LinkFail ) { 1217 PRINTF( option, "[Err] NCSI packet retry number over flows when find channel\n" ); 1218 1219 if ( eng->flg.NCSI_Flag & NCSI_Flag_Get_Version_ID ) { PRINTF( option, "[NCSI] Time out when Get Version ID \n" ); } 1220 if ( eng->flg.NCSI_Flag & NCSI_Flag_Get_Capabilities ) { PRINTF( option, "[NCSI] Time out when Get Capabilities \n" ); } 1221 if ( eng->flg.NCSI_Flag & NCSI_Flag_Select_Active_Package ) { PRINTF( option, "[NCSI] Time out when Select Active Package \n" ); } 1222 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Set_MAC_Address ) { PRINTF( option, "[NCSI] Time out when Enable Set MAC Address \n" ); } 1223 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Broadcast_Filter ) { PRINTF( option, "[NCSI] Time out when Enable Broadcast Filter \n" ); } 1224 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Network_TX ) { PRINTF( option, "[NCSI] Time out when Enable Network TX \n" ); } 1225 if ( eng->flg.NCSI_Flag & NCSI_Flag_Enable_Channel ) { PRINTF( option, "[NCSI] Time out when Enable Channel \n" ); } 1226 if ( eng->flg.NCSI_Flag & NCSI_Flag_Disable_Network_TX ) { PRINTF( option, "[NCSI] Time out when Disable Network TX \n" ); } 1227 if ( eng->flg.NCSI_Flag & NCSI_Flag_Disable_Channel ) { PRINTF( option, "[NCSI] Time out when Disable Channel \n" ); } 1228 if ( eng->flg.NCSI_Flag & NCSI_Flag_Select_Package ) { PRINTF( option, "[NCSI] Time out when Select Package \n" ); } 1229 if ( eng->flg.NCSI_Flag & NCSI_Flag_Deselect_Package ) { PRINTF( option, "[NCSI] Time out when Deselect Package \n" ); } 1230 if ( eng->flg.NCSI_Flag & NCSI_Flag_Set_Link ) { PRINTF( option, "[NCSI] Time out when Set Link \n" ); } 1231 if ( eng->flg.NCSI_Flag & NCSI_Flag_Get_Controller_Packet_Statistics) { PRINTF( option, "[NCSI] Time out when Get Controller Packet Statistics\n" ); } 1232 } 1233 1234 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[NCSI] Channel number expected: %d, real: %d\n", eng->arg.GChannelTolNum, eng->dat.number_chl ); } 1235 if ( eng->flg.Err_Flag & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[NCSI] Peckage number expected: %d, real: %d\n", eng->arg.GPackageTolNum, eng->dat.number_pak ); } 1236 } // End if ( eng->arg.run_mode == MODE_NCSI ) 1237 } // End if ( eng->flg.Err_Flag ) 1238 } // End if ( eng->flg.print_en ) 1239 } // End void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option) 1240 1241 //------------------------------------------------------------ 1242 1243 //------------------------------------------------------------ 1244 int FindErr (MAC_ENGINE *p_eng, int value) 1245 { 1246 p_eng->flg.Err_Flag = p_eng->flg.Err_Flag | value; 1247 1248 if (DbgPrn_ErrFlg) 1249 printf("\nErr_Flag: [%08x]\n", p_eng->flg.Err_Flag); 1250 1251 return (1); 1252 } 1253 1254 //------------------------------------------------------------ 1255 int FindErr_Des (MAC_ENGINE *p_eng, int value) 1256 { 1257 p_eng->flg.Err_Flag = p_eng->flg.Err_Flag | Err_Flag_Check_Des; 1258 p_eng->flg.Des_Flag = p_eng->flg.Des_Flag | value; 1259 if (DbgPrn_ErrFlg) 1260 printf("\nErr_Flag: [%08x] Des_Flag: [%08x]\n", 1261 p_eng->flg.Err_Flag, p_eng->flg.Des_Flag); 1262 1263 return (1); 1264 } 1265 1266 //------------------------------------------------------------ 1267 // Get and Check status of Interrupt 1268 //------------------------------------------------------------ 1269 int check_int (MAC_ENGINE *eng, char *type ) 1270 { 1271 nt_log_func_name(); 1272 1273 uint32_t mac_00; 1274 1275 mac_00 = mac_reg_read(eng, 0x00); 1276 #ifdef CheckRxbufUNAVA 1277 if (mac_00 & BIT(2)) { 1278 PRINTF( FP_LOG, "[%sIntStatus] Receiving buffer unavailable : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1279 FindErr( eng, Err_Flag_RXBUF_UNAVA ); 1280 } 1281 #endif 1282 1283 #ifdef CheckRPktLost 1284 if (mac_00 & BIT(3)) { 1285 PRINTF( FP_LOG, "[%sIntStatus] Received packet lost due to RX FIFO full : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1286 FindErr( eng, Err_Flag_RPKT_LOST ); 1287 } 1288 #endif 1289 1290 #ifdef CheckNPTxbufUNAVA 1291 if (mac_00 & BIT(6) ) { 1292 PRINTF( FP_LOG, "[%sIntStatus] Normal priority transmit buffer unavailable: %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1293 FindErr( eng, Err_Flag_NPTXBUF_UNAVA ); 1294 } 1295 #endif 1296 1297 #ifdef CheckTPktLost 1298 if (mac_00 & BIT(7)) { 1299 PRINTF( FP_LOG, "[%sIntStatus] Packets transmitted to Ethernet lost : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1300 FindErr( eng, Err_Flag_TPKT_LOST ); 1301 } 1302 #endif 1303 1304 if ( eng->flg.Err_Flag ) 1305 return(1); 1306 else 1307 return(0); 1308 } // End int check_int (MAC_ENGINE *eng, char *type) 1309 1310 1311 //------------------------------------------------------------ 1312 // Buffer 1313 //------------------------------------------------------------ 1314 void setup_framesize (MAC_ENGINE *eng) 1315 { 1316 int32_t des_num; 1317 1318 nt_log_func_name(); 1319 1320 //------------------------------ 1321 // Fill Frame Size out descriptor area 1322 //------------------------------ 1323 if (0) { 1324 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1325 if ( RAND_SIZE_SIMPLE ) 1326 switch( rand() % 5 ) { 1327 case 0 : eng->dat.FRAME_LEN[ des_num ] = 0x4e ; break; 1328 case 1 : eng->dat.FRAME_LEN[ des_num ] = 0x4ba; break; 1329 default: eng->dat.FRAME_LEN[ des_num ] = 0x5ea; break; 1330 } 1331 else 1332 // eng->dat.FRAME_LEN[ des_num ] = ( rand() + RAND_SIZE_MIN ) % ( RAND_SIZE_MAX + 1 ); 1333 eng->dat.FRAME_LEN[ des_num ] = RAND_SIZE_MIN + ( rand() % ( RAND_SIZE_MAX - RAND_SIZE_MIN + 1 ) ); 1334 1335 if ( DbgPrn_FRAME_LEN ) 1336 PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1337 } 1338 } 1339 else { 1340 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1341 #ifdef SelectSimpleLength 1342 if ( des_num % FRAME_SELH_PERD ) 1343 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH; 1344 else 1345 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL; 1346 #else 1347 if ( eng->run.tm_tx_only ) { 1348 if ( eng->run.TM_IEEE ) 1349 eng->dat.FRAME_LEN[ des_num ] = 1514; 1350 else 1351 eng->dat.FRAME_LEN[ des_num ] = 60; 1352 } 1353 else { 1354 #ifdef SelectLengthInc 1355 eng->dat.FRAME_LEN[ des_num ] = 1514 - ( des_num % 1455 ); 1356 #else 1357 if ( des_num % FRAME_SELH_PERD ) 1358 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH; 1359 else 1360 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL; 1361 #endif 1362 } // End if ( eng->run.tm_tx_only ) 1363 #endif 1364 if ( DbgPrn_FRAME_LEN ) 1365 PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1366 1367 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1368 } // End if ( ENABLE_RAND_SIZE ) 1369 1370 // Calculate average of frame size 1371 #ifdef Enable_ShowBW 1372 eng->dat.Total_frame_len = 0; 1373 1374 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) 1375 eng->dat.Total_frame_len += eng->dat.FRAME_LEN[ des_num ]; 1376 #endif 1377 1378 //------------------------------ 1379 // Write Plane 1380 //------------------------------ 1381 switch( ZeroCopy_OFFSET & 0x3 ) { 1382 case 0: eng->dat.wp_fir = 0xffffffff; break; 1383 case 1: eng->dat.wp_fir = 0xffffff00; break; 1384 case 2: eng->dat.wp_fir = 0xffff0000; break; 1385 case 3: eng->dat.wp_fir = 0xff000000; break; 1386 } 1387 1388 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) 1389 switch( ( ZeroCopy_OFFSET + eng->dat.FRAME_LEN[ des_num ] - 1 ) & 0x3 ) { 1390 case 0: eng->dat.wp_lst[ des_num ] = 0x000000ff; break; 1391 case 1: eng->dat.wp_lst[ des_num ] = 0x0000ffff; break; 1392 case 2: eng->dat.wp_lst[ des_num ] = 0x00ffffff; break; 1393 case 3: eng->dat.wp_lst[ des_num ] = 0xffffffff; break; 1394 } 1395 } // End void setup_framesize (void) 1396 1397 //------------------------------------------------------------ 1398 void setup_arp(MAC_ENGINE *eng) 1399 { 1400 1401 nt_log_func_name(); 1402 1403 memcpy(eng->dat.ARP_data, ARP_org_data, sizeof(ARP_org_data)); 1404 1405 eng->dat.ARP_data[1] &= ~GENMASK(31, 16); 1406 eng->dat.ARP_data[1] |= (eng->inf.SA[1] << 24) | (eng->inf.SA[0] << 16); 1407 eng->dat.ARP_data[2] = (eng->inf.SA[5] << 24) | (eng->inf.SA[4] << 16) | 1408 (eng->inf.SA[3] << 8) | (eng->inf.SA[2]); 1409 eng->dat.ARP_data[5] &= ~GENMASK(31, 16); 1410 eng->dat.ARP_data[5] |= (eng->inf.SA[1] << 24) | (eng->inf.SA[0] << 16); 1411 eng->dat.ARP_data[6] = (eng->inf.SA[5] << 24) | (eng->inf.SA[4] << 16) | 1412 (eng->inf.SA[3] << 8) | (eng->inf.SA[2]); 1413 } 1414 1415 //------------------------------------------------------------ 1416 void setup_buf (MAC_ENGINE *eng) 1417 { 1418 int32_t des_num_max; 1419 int32_t des_num; 1420 int i; 1421 uint32_t adr; 1422 uint32_t adr_srt; 1423 uint32_t adr_end; 1424 uint32_t Current_framelen; 1425 uint32_t gdata = 0; 1426 #ifdef SelectSimpleDA 1427 int cnt; 1428 uint32_t len; 1429 #endif 1430 1431 nt_log_func_name(); 1432 1433 // It need be multiple of 4 1434 eng->dat.DMA_Base_Setup = DMA_BASE & 0xfffffffc; 1435 adr_srt = eng->dat.DMA_Base_Setup; 1436 1437 if (eng->run.tm_tx_only) { 1438 if (eng->run.TM_IEEE) { 1439 for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) { 1440 if ( DbgPrn_BufAdr ) 1441 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1442 Write_Mem_Dat_DD(adr_srt, 0xffffffff); 1443 Write_Mem_Dat_DD(adr_srt + 4, 1444 eng->dat.ARP_data[1]); 1445 Write_Mem_Dat_DD(adr_srt + 8, 1446 eng->dat.ARP_data[2]); 1447 1448 for (adr = (adr_srt + 12); 1449 adr < (adr_srt + DMA_PakSize); adr += 4) { 1450 switch (eng->arg.test_mode) { 1451 case 4: 1452 gdata = rand() | (rand() << 16); 1453 break; 1454 case 5: 1455 gdata = eng->arg.user_def_val; 1456 break; 1457 } 1458 Write_Mem_Dat_DD(adr, gdata); 1459 } 1460 adr_srt += DMA_PakSize; 1461 } 1462 } else { 1463 printf("----->[ARP] 60 bytes\n"); 1464 for (i = 0; i < 16; i++) 1465 printf(" [Tx%02d] %08x %08x\n", i, eng->dat.ARP_data[i], SWAP_4B( eng->dat.ARP_data[i] ) ); 1466 1467 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1468 if ( DbgPrn_BufAdr ) 1469 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1470 1471 for (i = 0; i < 16; i++) 1472 Write_Mem_Dat_DD( adr_srt + ( i << 2 ), eng->dat.ARP_data[i] ); 1473 1474 1475 adr_srt += DMA_PakSize; 1476 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1477 } // End if ( eng->run.TM_IEEE ) 1478 } else { 1479 if ( eng->arg.ctrl.b.single_packet ) 1480 des_num_max = 1; 1481 else 1482 des_num_max = eng->dat.Des_Num; 1483 1484 for (des_num = 0; des_num < des_num_max; des_num++) { 1485 if (DbgPrn_BufAdr) 1486 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1487 #ifdef SelectSimpleData 1488 #ifdef SimpleData_Fix 1489 switch( des_num % SimpleData_FixNum ) { 1490 case 0 : gdata = SimpleData_FixVal00; break; 1491 case 1 : gdata = SimpleData_FixVal01; break; 1492 case 2 : gdata = SimpleData_FixVal02; break; 1493 case 3 : gdata = SimpleData_FixVal03; break; 1494 case 4 : gdata = SimpleData_FixVal04; break; 1495 case 5 : gdata = SimpleData_FixVal05; break; 1496 case 6 : gdata = SimpleData_FixVal06; break; 1497 case 7 : gdata = SimpleData_FixVal07; break; 1498 case 8 : gdata = SimpleData_FixVal08; break; 1499 case 9 : gdata = SimpleData_FixVal09; break; 1500 case 10 : gdata = SimpleData_FixVal10; break; 1501 default : gdata = SimpleData_FixVal11; break; 1502 } 1503 #else 1504 gdata = 0x11111111 * ((des_num + SEED_START) % 256); 1505 #endif 1506 #else 1507 gdata = DATA_SEED( des_num + SEED_START ); 1508 #endif 1509 Current_framelen = eng->dat.FRAME_LEN[ des_num ]; 1510 1511 if ( DbgPrn_FRAME_LEN ) 1512 PRINTF( FP_LOG, "[setup_buf ] Current_framelen:%08x[Des:%d][loop[%d]:%d]\n", Current_framelen, des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1513 #ifdef SelectSimpleDA 1514 cnt = 0; 1515 len = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) | 1516 ( ( Current_framelen - 14 ) >> 8 ); 1517 #endif 1518 adr_end = adr_srt + DMA_PakSize; 1519 for ( adr = adr_srt; adr < adr_end; adr += 4 ) { 1520 #ifdef SelectSimpleDA 1521 cnt++; 1522 if ( cnt == 1 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat0 ); 1523 else if ( cnt == 2 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat1 ); 1524 else if ( cnt == 3 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat2 ); 1525 else if ( cnt == 4 ) Write_Mem_Dat_DD( adr, len | (len << 16) ); 1526 else 1527 #endif 1528 Write_Mem_Dat_DD( adr, gdata ); 1529 #ifdef SelectSimpleData 1530 gdata = gdata ^ SimpleData_XORVal; 1531 #else 1532 gdata += DATA_IncVal; 1533 #endif 1534 } 1535 adr_srt += DMA_PakSize; 1536 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1537 } // End if ( eng->run.tm_tx_only ) 1538 } // End void setup_buf (MAC_ENGINE *eng) 1539 1540 //------------------------------------------------------------ 1541 // Check data of one packet 1542 //------------------------------------------------------------ 1543 char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number) 1544 { 1545 int32_t number_dat; 1546 int index; 1547 uint32_t rdata; 1548 uint32_t wp_lst_cur; 1549 uint32_t adr_las; 1550 uint32_t adr; 1551 uint32_t adr_srt; 1552 uint32_t adr_end; 1553 #ifdef SelectSimpleDA 1554 int cnt; 1555 uint32_t len; 1556 uint32_t gdata_bak; 1557 #endif 1558 uint32_t gdata; 1559 1560 uint32_t wp; 1561 1562 nt_log_func_name(); 1563 1564 if (eng->arg.ctrl.b.single_packet) 1565 number_dat = 0; 1566 else 1567 number_dat = number; 1568 1569 wp_lst_cur = eng->dat.wp_lst[ number ]; 1570 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[ number_dat ]; 1571 1572 if ( DbgPrn_FRAME_LEN ) 1573 PRINTF( FP_LOG, "[check_Data ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN_Cur, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1574 1575 adr_srt = datbase; 1576 adr_end = adr_srt + PktByteSize; 1577 1578 #if defined(SelectSimpleData) 1579 #ifdef SimpleData_Fix 1580 switch( number_dat % SimpleData_FixNum ) { 1581 case 0 : gdata = SimpleData_FixVal00; break; 1582 case 1 : gdata = SimpleData_FixVal01; break; 1583 case 2 : gdata = SimpleData_FixVal02; break; 1584 case 3 : gdata = SimpleData_FixVal03; break; 1585 case 4 : gdata = SimpleData_FixVal04; break; 1586 case 5 : gdata = SimpleData_FixVal05; break; 1587 case 6 : gdata = SimpleData_FixVal06; break; 1588 case 7 : gdata = SimpleData_FixVal07; break; 1589 case 8 : gdata = SimpleData_FixVal08; break; 1590 case 9 : gdata = SimpleData_FixVal09; break; 1591 case 10 : gdata = SimpleData_FixVal10; break; 1592 default : gdata = SimpleData_FixVal11; break; 1593 } 1594 #else 1595 gdata = 0x11111111 * (( number_dat + SEED_START ) % 256 ); 1596 #endif 1597 #else 1598 gdata = DATA_SEED( number_dat + SEED_START ); 1599 #endif 1600 1601 //printf("check_buf: %08x - %08x [%08x]\n", adr_srt, adr_end, datbase); 1602 wp = eng->dat.wp_fir; 1603 adr_las = adr_end - 4; 1604 #ifdef SelectSimpleDA 1605 cnt = 0; 1606 len = ((( eng->dat.FRAME_LEN_Cur-14 ) & 0xff ) << 8 ) | 1607 ( ( eng->dat.FRAME_LEN_Cur-14 ) >> 8 ); 1608 #endif 1609 1610 if ( DbgPrn_Bufdat ) 1611 PRINTF( FP_LOG, " Inf:%08x ~ %08x(%08x) %08x [Des:%d][loop[%d]:%d]\n", adr_srt, adr_end, adr_las, gdata, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1612 1613 for ( adr = adr_srt; adr < adr_end; adr+=4 ) { 1614 #ifdef SelectSimpleDA 1615 cnt++; 1616 if ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; } 1617 else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; } 1618 else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; } 1619 else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16); } 1620 #endif 1621 rdata = Read_Mem_Dat_DD( adr ); 1622 if ( adr == adr_las ) 1623 wp = wp & wp_lst_cur; 1624 1625 if ( ( rdata & wp ) != ( gdata & wp ) ) { 1626 PRINTF( FP_LOG, "\nError: Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1627 for ( index = 0; index < 6; index++ ) 1628 PRINTF( FP_LOG, "Rep : Adr:%08x (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, Read_Mem_Dat_DD( adr ), gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1629 1630 if (DbgPrn_DumpMACCnt) 1631 dump_mac_ROreg(eng); 1632 1633 return( FindErr( eng, Err_Flag_Check_Buf_Data ) ); 1634 } // End if ( (rdata & wp) != (gdata & wp) ) 1635 if ( DbgPrn_BufdatDetail ) 1636 PRINTF( FP_LOG, " Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1637 1638 #ifdef SelectSimpleDA 1639 if ( cnt <= 4 ) 1640 gdata = gdata_bak; 1641 #endif 1642 1643 #if defined(SelectSimpleData) 1644 gdata = gdata ^ SimpleData_XORVal; 1645 #else 1646 gdata += DATA_IncVal; 1647 #endif 1648 1649 wp = 0xffffffff; 1650 } 1651 return(0); 1652 } // End char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number) 1653 1654 //------------------------------------------------------------ 1655 char check_buf (MAC_ENGINE *eng, int loopcnt) 1656 { 1657 int32_t des_num; 1658 uint32_t desadr; 1659 uint32_t datbase; 1660 1661 nt_log_func_name(); 1662 1663 desadr = eng->run.rdes_base + (16 * eng->dat.Des_Num) - 4; 1664 for (des_num = eng->dat.Des_Num - 1; des_num >= 0; des_num--) { 1665 #ifdef CHECK_RX_DATA 1666 datbase = AT_BUF_MEMRW(Read_Mem_Des_DD(desadr) & 0xfffffffc); 1667 if (check_Data(eng, datbase, des_num)) { 1668 check_int(eng, ""); 1669 return (1); 1670 } 1671 if (check_int(eng, "")) 1672 return 1; 1673 #endif 1674 desadr -= 16; 1675 } 1676 if (check_int(eng, "")) 1677 return (1); 1678 1679 #if defined(Delay_CheckData_LoopNum) && defined(Delay_CheckData) 1680 if ((loopcnt % Delay_CheckData_LoopNum) == 0) 1681 DELAY(Delay_CheckData); 1682 #endif 1683 return (0); 1684 } // End char check_buf (MAC_ENGINE *eng, int loopcnt) 1685 1686 //------------------------------------------------------------ 1687 // Descriptor 1688 //------------------------------------------------------------ 1689 void setup_txdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase) 1690 { 1691 uint32_t bufadr; 1692 uint32_t bufadrgap; 1693 uint32_t desval = 0; 1694 int32_t des_num; 1695 1696 nt_log_func_name(); 1697 1698 bufadr = bufbase; 1699 if (eng->arg.ctrl.b.single_packet) 1700 bufadrgap = 0; 1701 else 1702 bufadrgap = DMA_PakSize; 1703 1704 if (eng->run.TM_TxDataEn) { 1705 for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) { 1706 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1707 desval = TDES_IniVal; 1708 Write_Mem_Des_DD(desadr + 0x04, 0); 1709 Write_Mem_Des_DD(desadr + 0x08, 0); 1710 Write_Mem_Des_DD(desadr + 0x0C, bufadr); 1711 Write_Mem_Des_DD(desadr, desval); 1712 1713 if (DbgPrn_FRAME_LEN) 1714 PRINTF( 1715 FP_LOG, 1716 "[setup_txdes ] " 1717 "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", 1718 eng->dat.FRAME_LEN_Cur, des_num, 1719 eng->run.loop_of_cnt, eng->run.loop_cnt); 1720 1721 if (DbgPrn_BufAdr) 1722 printf("[loop[%d]:%4d][des:%4d][setup_txdes] " 1723 "%08x [%08x]\n", 1724 eng->run.loop_of_cnt, eng->run.loop_cnt, 1725 des_num, desadr, bufadr); 1726 1727 desadr += 16; 1728 bufadr += bufadrgap; 1729 } 1730 barrier(); 1731 Write_Mem_Des_DD(desadr - 0x10, desval | EOR_IniVal); 1732 } else { 1733 Write_Mem_Des_DD(desadr, 0); 1734 } 1735 } 1736 1737 //------------------------------------------------------------ 1738 void setup_rxdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase) 1739 { 1740 uint32_t bufadr; 1741 uint32_t desval; 1742 int32_t des_num; 1743 1744 nt_log_func_name(); 1745 1746 bufadr = bufbase; 1747 desval = RDES_IniVal; 1748 if ( eng->run.TM_RxDataEn ) { 1749 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1750 Write_Mem_Des_DD(desadr + 0x04, 0 ); 1751 Write_Mem_Des_DD(desadr + 0x08, 0 ); 1752 Write_Mem_Des_DD(desadr + 0x0C, bufadr); 1753 Write_Mem_Des_DD(desadr + 0x00, desval); 1754 1755 if ( DbgPrn_BufAdr ) 1756 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x [%08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, desadr, bufadr); 1757 1758 desadr += 16; 1759 bufadr += DMA_PakSize; 1760 } 1761 barrier(); 1762 Write_Mem_Des_DD( desadr - 0x10, desval | EOR_IniVal ); 1763 } 1764 else { 1765 Write_Mem_Des_DD( desadr, 0x80000000 ); 1766 } // End if ( eng->run.TM_RxDataEn ) 1767 } // End void setup_rxdes (uint32_t desadr, uint32_t bufbase) 1768 1769 //------------------------------------------------------------ 1770 // First setting TX and RX information 1771 //------------------------------------------------------------ 1772 void setup_des (MAC_ENGINE *eng, uint32_t bufnum) 1773 { 1774 if (DbgPrn_BufAdr) { 1775 printf("setup_des: %d\n", bufnum); 1776 debug_pause(); 1777 } 1778 1779 eng->dat.DMA_Base_Tx = 1780 ZeroCopy_OFFSET + eng->dat.DMA_Base_Setup; 1781 eng->dat.DMA_Base_Rx = ZeroCopy_OFFSET + GET_DMA_BASE(eng, 0); 1782 1783 setup_txdes(eng, eng->run.tdes_base, 1784 AT_MEMRW_BUF(eng->dat.DMA_Base_Tx)); 1785 setup_rxdes(eng, eng->run.rdes_base, 1786 AT_MEMRW_BUF(eng->dat.DMA_Base_Rx)); 1787 } // End void setup_des (uint32_t bufnum) 1788 1789 //------------------------------------------------------------ 1790 // Move buffer point of TX and RX descriptor to next DMA buffer 1791 //------------------------------------------------------------ 1792 void setup_des_loop (MAC_ENGINE *eng, uint32_t bufnum) 1793 { 1794 int32_t des_num; 1795 uint32_t H_rx_desadr; 1796 uint32_t H_tx_desadr; 1797 uint32_t H_tx_bufadr; 1798 uint32_t H_rx_bufadr; 1799 1800 nt_log_func_name(); 1801 1802 if (eng->run.TM_RxDataEn) { 1803 H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx); 1804 H_rx_desadr = eng->run.rdes_base; 1805 for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) { 1806 Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr); 1807 Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal); 1808 if (DbgPrn_BufAdr) 1809 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] " 1810 "%08x [%08x]\n", 1811 eng->run.loop_of_cnt, eng->run.loop_cnt, 1812 des_num, H_rx_desadr, H_rx_bufadr); 1813 1814 H_rx_bufadr += DMA_PakSize; 1815 H_rx_desadr += 16; 1816 } 1817 Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr); 1818 Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal | EOR_IniVal); 1819 if (DbgPrn_BufAdr) 1820 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x " 1821 "[%08x]\n", 1822 eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, 1823 H_rx_desadr, H_rx_bufadr); 1824 } 1825 1826 if (eng->run.TM_TxDataEn) { 1827 H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx); 1828 H_tx_desadr = eng->run.tdes_base; 1829 for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) { 1830 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1831 Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr); 1832 Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal); 1833 if (DbgPrn_BufAdr) 1834 printf("[loop[%d]:%4d][des:%4d][setup_txdes] " 1835 "%08x [%08x]\n", 1836 eng->run.loop_of_cnt, eng->run.loop_cnt, 1837 des_num, H_tx_desadr, H_tx_bufadr); 1838 1839 H_tx_bufadr += DMA_PakSize; 1840 H_tx_desadr += 16; 1841 } 1842 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1843 Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr); 1844 Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal | EOR_IniVal); 1845 if (DbgPrn_BufAdr) 1846 printf("[loop[%d]:%4d][des:%4d][setup_txdes] %08x " 1847 "[%08x]\n", 1848 eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, 1849 H_tx_desadr, H_tx_bufadr); 1850 } 1851 } // End void setup_des_loop (uint32_t bufnum) 1852 1853 //------------------------------------------------------------ 1854 char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1855 { 1856 int timeout = 0; 1857 1858 eng->dat.TxDes0DW = Read_Mem_Des_DD(adr); 1859 1860 while (HWOwnTx(eng->dat.TxDes0DW)) { 1861 // we will run again, if transfer has not been completed. 1862 if ((eng->run.tm_tx_only || eng->run.TM_RxDataEn) && 1863 (++timeout > eng->run.timeout_th)) { 1864 PRINTF(FP_LOG, 1865 "[%sTxDesOwn] Address %08x = %08x " 1866 "[Des:%d][loop[%d]:%d]\n", 1867 type, adr, eng->dat.TxDes0DW, desnum, 1868 eng->run.loop_of_cnt, eng->run.loop_cnt); 1869 return (FindErr_Des(eng, Des_Flag_TxOwnTimeOut)); 1870 } 1871 1872 #ifdef Delay_ChkTxOwn 1873 DELAY(Delay_ChkTxOwn); 1874 #endif 1875 eng->dat.TxDes0DW = Read_Mem_Des_DD(adr); 1876 } 1877 1878 return(0); 1879 } // End char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1880 1881 //------------------------------------------------------------ 1882 char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1883 { 1884 #ifdef CheckRxOwn 1885 int timeout = 0; 1886 1887 eng->dat.RxDes0DW = Read_Mem_Des_DD(adr); 1888 1889 while (HWOwnRx(eng->dat.RxDes0DW)) { 1890 // we will run again, if transfer has not been completed. 1891 if (eng->run.TM_TxDataEn && (++timeout > eng->run.timeout_th)) { 1892 #if 0 1893 printf("[%sRxDesOwn] Address %08x = %08x " 1894 "[Des:%d][loop[%d]:%d]\n", 1895 type, adr, eng->dat.RxDes0DW, desnum, 1896 eng->run.loop_of_cnt, eng->run.loop_cnt); 1897 #endif 1898 FindErr_Des(eng, Des_Flag_RxOwnTimeOut); 1899 return (2); 1900 } 1901 1902 #ifdef Delay_ChkRxOwn 1903 DELAY(Delay_ChkRxOwn); 1904 #endif 1905 eng->dat.RxDes0DW = Read_Mem_Des_DD(adr); 1906 }; 1907 1908 #ifdef CheckRxLen 1909 if ( DbgPrn_FRAME_LEN ) 1910 PRINTF( FP_LOG, "[%sRxDes ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", type, ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1911 1912 if ( ( eng->dat.RxDes0DW & 0x3fff ) != ( eng->dat.FRAME_LEN_Cur + 4 ) ) { 1913 eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 ); 1914 PRINTF( FP_LOG, "[%sRxDes] Error Frame Length %08x:%08x %08x(%4d/%4d) [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, ( eng->dat.RxDes0DW & 0x3fff ), ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1915 FindErr_Des( eng, Des_Flag_FrameLen ); 1916 } 1917 #endif // End CheckRxLen 1918 1919 if ( eng->dat.RxDes0DW & RXDES_EM_ALL ) { 1920 eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 ); 1921 #ifdef CheckRxErr 1922 if ( eng->dat.RxDes0DW & RXDES_EM_RXERR ) { 1923 PRINTF( FP_LOG, "[%sRxDes] Error RxErr %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1924 FindErr_Des( eng, Des_Flag_RxErr ); 1925 } 1926 #endif // End CheckRxErr 1927 1928 #ifdef CheckCRC 1929 if ( eng->dat.RxDes0DW & RXDES_EM_CRC ) { 1930 PRINTF( FP_LOG, "[%sRxDes] Error CRC %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1931 FindErr_Des( eng, Des_Flag_CRC ); 1932 } 1933 #endif // End CheckCRC 1934 1935 #ifdef CheckFTL 1936 if ( eng->dat.RxDes0DW & RXDES_EM_FTL ) { 1937 PRINTF( FP_LOG, "[%sRxDes] Error FTL %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1938 FindErr_Des( eng, Des_Flag_FTL ); 1939 } 1940 #endif // End CheckFTL 1941 1942 #ifdef CheckRunt 1943 if ( eng->dat.RxDes0DW & RXDES_EM_RUNT) { 1944 PRINTF( FP_LOG, "[%sRxDes] Error Runt %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1945 FindErr_Des( eng, Des_Flag_Runt ); 1946 } 1947 #endif // End CheckRunt 1948 1949 #ifdef CheckOddNibble 1950 if ( eng->dat.RxDes0DW & RXDES_EM_ODD_NB ) { 1951 PRINTF( FP_LOG, "[%sRxDes] Odd Nibble %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1952 FindErr_Des( eng, Des_Flag_OddNibble ); 1953 } 1954 #endif // End CheckOddNibble 1955 1956 #ifdef CheckRxFIFOFull 1957 if ( eng->dat.RxDes0DW & RXDES_EM_FIFO_FULL ) { 1958 PRINTF( FP_LOG, "[%sRxDes] Error Rx FIFO Full %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1959 FindErr_Des( eng, Des_Flag_RxFIFOFull ); 1960 } 1961 #endif // End CheckRxFIFOFull 1962 } 1963 1964 #endif // End CheckRxOwn 1965 1966 if ( eng->flg.Err_Flag ) 1967 return(1); 1968 else 1969 return(0); 1970 } // End char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1971 1972 //------------------------------------------------------------ 1973 char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint) 1974 { 1975 int32_t desnum; 1976 int8_t desnum_last; 1977 uint32_t H_rx_desadr; 1978 uint32_t H_tx_desadr; 1979 uint32_t H_tx_bufadr; 1980 uint32_t H_rx_bufadr; 1981 #ifdef Delay_DesGap 1982 uint32_t dly_cnt = 0; 1983 uint32_t dly_max = Delay_CntMaxIncVal; 1984 #endif 1985 int ret; 1986 1987 nt_log_func_name(); 1988 1989 /* Fire the engine to send and recvice */ 1990 mac_reg_write(eng, 0x1c, 0x00000001); // Rx Poll 1991 mac_reg_write(eng, 0x18, 0x00000001); // Tx Poll 1992 1993 #ifndef SelectSimpleDes 1994 /* base of the descriptors */ 1995 H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx); 1996 H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx); 1997 #endif 1998 H_rx_desadr = eng->run.rdes_base; 1999 H_tx_desadr = eng->run.tdes_base; 2000 2001 #ifdef Delay_DES 2002 DELAY(Delay_DES); 2003 #endif 2004 2005 for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) { 2006 desnum_last = (desnum == (eng->dat.Des_Num - 1)) ? 1 : 0; 2007 if ( DbgPrn_BufAdr ) { 2008 if ( checkpoint ) 2009 printf("[loop[%d]:%4d][des:%4d][check_des ] %08x %08x [%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ) ); 2010 else 2011 printf("[loop[%d]:%4d][des:%4d][check_des ] %08x %08x [%08x %08x]->[%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ), H_tx_bufadr, H_rx_bufadr ); 2012 } 2013 2014 //[Delay]-------------------- 2015 #ifdef Delay_DesGap 2016 // if ( dly_cnt++ > 3 ) { 2017 if ( dly_cnt > Delay_CntMax ) { 2018 // switch ( rand() % 12 ) { 2019 // case 1 : dly_max = 00000; break; 2020 // case 3 : dly_max = 20000; break; 2021 // case 5 : dly_max = 40000; break; 2022 // case 7 : dly_max = 60000; break; 2023 // defaule: dly_max = 70000; break; 2024 // } 2025 // 2026 // dly_max += ( rand() % 4 ) * 14321; 2027 // 2028 // while (dly_cnt < dly_max) { 2029 // dly_cnt++; 2030 // } 2031 DELAY( Delay_DesGap ); 2032 dly_cnt = 0; 2033 } 2034 else { 2035 dly_cnt++; 2036 // timeout = 0; 2037 // while (timeout < 50000) {timeout++;}; 2038 } 2039 #endif // End Delay_DesGap 2040 2041 //[Check Owner Bit]-------------------- 2042 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[desnum]; 2043 if (DbgPrn_FRAME_LEN) 2044 PRINTF(FP_LOG, 2045 "[check_des ] " 2046 "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]%d\n", 2047 eng->dat.FRAME_LEN_Cur, desnum, 2048 eng->run.loop_of_cnt, eng->run.loop_cnt, 2049 checkpoint); 2050 2051 // Check the description of Tx and Rx 2052 if (eng->run.TM_TxDataEn) { 2053 ret = check_des_header_Tx(eng, "", H_tx_desadr, desnum); 2054 if (ret) { 2055 eng->flg.CheckDesFail_DesNum = desnum; 2056 return ret; 2057 } 2058 } 2059 if (eng->run.TM_RxDataEn) { 2060 ret = check_des_header_Rx(eng, "", H_rx_desadr, desnum); 2061 if (ret) { 2062 eng->flg.CheckDesFail_DesNum = desnum; 2063 return ret; 2064 2065 } 2066 } 2067 2068 #ifndef SelectSimpleDes 2069 if (!checkpoint) { 2070 // Setting buffer address to description of Tx and Rx on next stage 2071 if ( eng->run.TM_RxDataEn ) { 2072 Write_Mem_Des_DD( H_rx_desadr + 0x0C, H_rx_bufadr ); 2073 if ( desnum_last ) 2074 Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal ); 2075 else 2076 Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal ); 2077 2078 readl(H_rx_desadr); 2079 mac_reg_write(eng, 0x1c, 0x00000000); //Rx Poll 2080 H_rx_bufadr += DMA_PakSize; 2081 } 2082 if ( eng->run.TM_TxDataEn ) { 2083 Write_Mem_Des_DD( H_tx_desadr + 0x0C, H_tx_bufadr ); 2084 if ( desnum_last ) 2085 Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal ); 2086 else 2087 Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal ); 2088 2089 readl(H_tx_desadr); 2090 mac_reg_write(eng, 0x18, 0x00000000); //Tx Poll 2091 H_tx_bufadr += DMA_PakSize; 2092 } 2093 } 2094 #endif // End SelectSimpleDes 2095 2096 H_rx_desadr += 16; 2097 H_tx_desadr += 16; 2098 } // End for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) 2099 2100 return(0); 2101 } // End char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint) 2102 //#endif 2103 2104 //------------------------------------------------------------ 2105 // Print 2106 //----------------------------------------------------------- 2107 void PrintIO_Header (MAC_ENGINE *eng, uint8_t option) 2108 { 2109 int32_t rx_d, step, tmp; 2110 2111 if (eng->run.TM_IOStrength) { 2112 if (eng->io.drv_upper_bond > 1) { 2113 #ifdef CONFIG_ASPEED_AST2600 2114 PRINTF(option, "<IO Strength register: [%08x] 0x%08x>", 2115 eng->io.mac34_drv_reg.addr, 2116 eng->io.mac34_drv_reg.value.w); 2117 #else 2118 PRINTF(option, "<IO Strength register: [%08x] 0x%08x>", 2119 eng->io.mac12_drv_reg.addr, 2120 eng->io.mac12_drv_reg.value.w); 2121 #endif 2122 } 2123 } 2124 2125 if ( eng->run.speed_sel[ 0 ] ) { PRINTF( option, "\n[1G ]========================================>\n" ); } 2126 else if ( eng->run.speed_sel[ 1 ] ) { PRINTF( option, "\n[100M]========================================>\n" ); } 2127 else { PRINTF( option, "\n[10M ]========================================>\n" ); } 2128 2129 if ( !(option == FP_LOG) ) { 2130 step = eng->io.rx_delay_scan.step; 2131 2132 PRINTF(option, "\n "); 2133 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2134 2135 if (rx_d < 0) { 2136 PRINTF(option, "-" ); 2137 } else { 2138 PRINTF(option, "+" ); 2139 } 2140 } 2141 2142 PRINTF(option, "\n "); 2143 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2144 tmp = (abs(rx_d) >> 4) & 0xf; 2145 if (tmp == 0) { 2146 PRINTF(option, "0" ); 2147 } else { 2148 PRINTF(option, "%1x", tmp); 2149 } 2150 } 2151 2152 PRINTF(option, "\n "); 2153 for (rx_d = eng->io.rx_delay_scan.begin; 2154 rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2155 PRINTF(option, "%1x", (uint32_t)abs(rx_d) & 0xf); 2156 } 2157 2158 PRINTF(option, "\n "); 2159 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2160 if (eng->io.rx_delay_scan.orig == rx_d) { 2161 PRINTF(option, "|" ); 2162 } else { 2163 PRINTF(option, " " ); 2164 } 2165 } 2166 PRINTF( option, "\n"); 2167 } 2168 } 2169 2170 //------------------------------------------------------------ 2171 void PrintIO_LineS(MAC_ENGINE *p_eng, uint8_t option) 2172 { 2173 if (p_eng->io.tx_delay_scan.orig == p_eng->io.Dly_out_selval) { 2174 PRINTF( option, "%02x:-", p_eng->io.Dly_out_selval); 2175 } else { 2176 PRINTF( option, "%02x: ", p_eng->io.Dly_out_selval); 2177 } 2178 } // End void PrintIO_LineS (MAC_ENGINE *eng, uint8_t option) 2179 2180 //------------------------------------------------------------ 2181 void PrintIO_Line(MAC_ENGINE *p_eng, uint8_t option) 2182 { 2183 if ((p_eng->io.Dly_in_selval == p_eng->io.rx_delay_scan.orig) && 2184 (p_eng->io.Dly_out_selval == p_eng->io.tx_delay_scan.orig)) { 2185 if (1 == p_eng->io.result) { 2186 PRINTF(option, "X"); 2187 } else if (2 == p_eng->io.result) { 2188 PRINTF(option, "*"); 2189 } else { 2190 PRINTF(option, "O"); 2191 } 2192 } else { 2193 if (1 == p_eng->io.result) { 2194 PRINTF(option, "x"); 2195 } else if (2 == p_eng->io.result) { 2196 PRINTF(option, "."); 2197 } else { 2198 PRINTF(option, "o"); 2199 } 2200 } 2201 } 2202 2203 //------------------------------------------------------------ 2204 // main 2205 //------------------------------------------------------------ 2206 2207 //------------------------------------------------------------ 2208 void TestingSetup (MAC_ENGINE *eng) 2209 { 2210 nt_log_func_name(); 2211 2212 //[Setup]-------------------- 2213 setup_framesize( eng ); 2214 setup_buf( eng ); 2215 } 2216 2217 //------------------------------------------------------------ 2218 // Return 1 ==> fail 2219 // Return 0 ==> PASS 2220 //------------------------------------------------------------ 2221 char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum) 2222 { 2223 char checkprd; 2224 char looplast; 2225 char checken; 2226 int ret; 2227 2228 nt_log_func_name(); 2229 2230 if (DbgPrn_DumpMACCnt) 2231 dump_mac_ROreg(eng); 2232 2233 //[Setup]-------------------- 2234 eng->run.loop_cnt = 0; 2235 checkprd = 0; 2236 checken = 0; 2237 looplast = 0; 2238 2239 2240 setup_des(eng, 0); 2241 2242 if ( eng->run.TM_WaitStart ) { 2243 printf("Press any key to start...\n"); 2244 GET_CAHR(); 2245 } 2246 2247 2248 while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) { 2249 looplast = !eng->arg.loop_inf && ( eng->run.loop_cnt == eng->run.loop_max - 1 ); 2250 2251 #ifdef CheckRxBuf 2252 if (!eng->run.tm_tx_only) 2253 checkprd = ((eng->run.loop_cnt % loop_checknum) == (loop_checknum - 1)); 2254 checken = looplast | checkprd; 2255 #endif 2256 2257 if (DbgPrn_BufAdr) { 2258 printf("for start ======> [%d]%d/%d(%d) looplast:%d " 2259 "checkprd:%d checken:%d\n", 2260 eng->run.loop_of_cnt, eng->run.loop_cnt, 2261 eng->run.loop_max, eng->arg.loop_inf, 2262 looplast, checkprd, checken); 2263 debug_pause(); 2264 } 2265 2266 2267 if (eng->run.TM_RxDataEn) 2268 eng->dat.DMA_Base_Tx = eng->dat.DMA_Base_Rx; 2269 2270 eng->dat.DMA_Base_Rx = 2271 ZeroCopy_OFFSET + GET_DMA_BASE(eng, eng->run.loop_cnt + 1); 2272 //[Check DES]-------------------- 2273 if (ret = check_des(eng, eng->run.loop_cnt, checken)) { 2274 //descriptor error 2275 eng->dat.Des_Num = eng->flg.CheckDesFail_DesNum + 1; 2276 #ifdef CheckRxBuf 2277 if (checkprd) 2278 check_buf(eng, loop_checknum); 2279 else 2280 check_buf(eng, (eng->run.loop_max % loop_checknum)); 2281 eng->dat.Des_Num = eng->dat.Des_Num_Org; 2282 #endif 2283 2284 if (DbgPrn_DumpMACCnt) 2285 dump_mac_ROreg(eng); 2286 2287 return ret; 2288 } 2289 2290 //[Check Buf]-------------------- 2291 if (eng->run.TM_RxDataEn && checken) { 2292 if (checkprd) { 2293 #ifdef Enable_ShowBW 2294 printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused); 2295 PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused ); 2296 #endif 2297 2298 #ifdef CheckRxBuf 2299 if (check_buf(eng, loop_checknum)) 2300 return(1); 2301 #endif 2302 } else { 2303 #ifdef Enable_ShowBW 2304 printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused); 2305 PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused ); 2306 #endif 2307 2308 #ifdef CheckRxBuf 2309 if (check_buf(eng, (eng->run.loop_max % loop_checknum))) 2310 return(1); 2311 #endif 2312 } // End if ( checkprd ) 2313 2314 #ifndef SelectSimpleDes 2315 if (!looplast) 2316 setup_des_loop(eng, eng->run.loop_cnt); 2317 #endif 2318 2319 #ifdef Enable_ShowBW 2320 timeold = clock(); 2321 #endif 2322 } // End if ( eng->run.TM_RxDataEn && checken ) 2323 2324 #ifdef SelectSimpleDes 2325 if (!looplast) 2326 setup_des_loop(eng, eng->run.loop_cnt); 2327 #endif 2328 2329 if ( eng->arg.loop_inf ) 2330 printf("===============> Loop[%d]: %d \r", eng->run.loop_of_cnt, eng->run.loop_cnt); 2331 else if ( eng->arg.test_mode == 0 ) { 2332 if ( !( DbgPrn_BufAdr || eng->run.delay_margin ) ) 2333 printf(" [%d]%d \r", eng->run.loop_of_cnt, eng->run.loop_cnt); 2334 } 2335 2336 if (DbgPrn_BufAdr) { 2337 printf("for end ======> [%d]%d/%d(%d)\n", 2338 eng->run.loop_of_cnt, eng->run.loop_cnt, 2339 eng->run.loop_max, eng->arg.loop_inf); 2340 debug_pause(); 2341 } 2342 2343 if (eng->run.loop_cnt >= 0x7fffffff) { 2344 debug("loop counter wrapped around\n"); 2345 eng->run.loop_cnt = 0; 2346 eng->run.loop_of_cnt++; 2347 } else 2348 eng->run.loop_cnt++; 2349 } // End while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) 2350 2351 eng->flg.all_fail = 0; 2352 return(0); 2353 } // End char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum) 2354