1 /* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11 //#define MAC_DEBUG_REGRW_MAC 12 //#define MAC_DEBUG_REGRW_PHY 13 //#define MAC_DEBUG_REGRW_SCU 14 //#define MAC_DEBUG_REGRW_WDT 15 //#define MAC_DEBUG_REGRW_SDR 16 //#define MAC_DEBUG_REGRW_SMB 17 //#define MAC_DEBUG_REGRW_TIMER 18 //#define MAC_DEBUG_REGRW_GPIO 19 //#define MAC_DEBUG_MEMRW_Dat 20 //#define MAC_DEBUG_MEMRW_Des 21 22 #define MAC_C 23 24 #include "swfunc.h" 25 26 #include "comminf.h" 27 #include <command.h> 28 #include <common.h> 29 #include <malloc.h> 30 #include "mem_io.h" 31 // ------------------------------------------------------------- 32 const uint32_t ARP_org_data[16] = { 33 0xffffffff, 34 0x0000ffff, // SA:00-00- 35 0x12345678, // SA:78-56-34-12 36 0x01000608, // ARP(0x0806) 37 0x04060008, 38 0x00000100, // sender MAC Address: 00 00 39 0x12345678, // sender MAC Address: 12 34 56 78 40 0xeb00a8c0, // sender IP Address: 192.168.0.235 (C0.A8.0.EB) 41 0x00000000, // target MAC Address: 00 00 00 00 42 0xa8c00000, // target MAC Address: 00 00, target IP Address:192.168 43 0x00005c00, // target IP Address: 0.92 (C0.A8.0.5C) 44 // 0x00000100, // target IP Address: 0.1 (C0.A8.0.1) 45 // 0x0000de00, // target IP Address: 0.222 (C0.A8.0.DE) 46 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc68e2bd5}; 47 48 //------------------------------------------------------------ 49 // Read Memory 50 //------------------------------------------------------------ 51 uint32_t Read_Mem_Dat_NCSI_DD(uint32_t addr) 52 { 53 #ifdef MAC_DEBUG_MEMRW_Dat 54 printf("[MEMRd-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( readl(addr) ) ); 55 #endif 56 return ( SWAP_4B_LEDN_MEM( readl(addr) ) ); 57 } 58 59 uint32_t Read_Mem_Des_NCSI_DD(uint32_t addr) 60 { 61 #ifdef MAC_DEBUG_MEMRW_Des 62 printf("[MEMRd-Des] %08x = %08x\n", addr, 63 SWAP_4B_LEDN_MEM(readl(addr))); 64 #endif 65 return (SWAP_4B_LEDN_MEM(readl(addr))); 66 } 67 68 uint32_t Read_Mem_Dat_DD(uint32_t addr) 69 { 70 #ifdef MAC_DEBUG_MEMRW_Dat 71 printf("[MEMRd-Dat] %08x = %08x\n", addr, 72 SWAP_4B_LEDN_MEM(readl(addr))); 73 #endif 74 return (SWAP_4B_LEDN_MEM(readl(addr))); 75 } 76 77 uint32_t Read_Mem_Des_DD(uint32_t addr) 78 { 79 #ifdef MAC_DEBUG_MEMRW_Des 80 printf("[MEMRd-Des] %08x = %08x\n", addr, 81 SWAP_4B_LEDN_MEM(readl(addr))); 82 #endif 83 return (SWAP_4B_LEDN_MEM(readl(addr))); 84 } 85 86 //------------------------------------------------------------ 87 // Read Register 88 //------------------------------------------------------------ 89 uint32_t mac_reg_read(MAC_ENGINE *p_eng, uint32_t addr) 90 { 91 return readl(p_eng->run.mac_base + addr); 92 } 93 94 //------------------------------------------------------------ 95 // Write Memory 96 //------------------------------------------------------------ 97 void Write_Mem_Dat_NCSI_DD (uint32_t addr, uint32_t data) { 98 #ifdef MAC_DEBUG_MEMRW_Dat 99 printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 100 #endif 101 writel(data, addr); 102 } 103 void Write_Mem_Des_NCSI_DD (uint32_t addr, uint32_t data) { 104 #ifdef MAC_DEBUG_MEMRW_Des 105 printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 106 #endif 107 writel(data, addr); 108 } 109 void Write_Mem_Dat_DD (uint32_t addr, uint32_t data) { 110 #ifdef MAC_DEBUG_MEMRW_Dat 111 printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 112 #endif 113 writel(data, addr); 114 } 115 void Write_Mem_Des_DD (uint32_t addr, uint32_t data) { 116 #ifdef MAC_DEBUG_MEMRW_Des 117 printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) ); 118 #endif 119 writel(data, addr); 120 } 121 122 //------------------------------------------------------------ 123 // Write Register 124 //------------------------------------------------------------ 125 void mac_reg_write(MAC_ENGINE *p_eng, uint32_t addr, uint32_t data) 126 { 127 writel(data, p_eng->run.mac_base + addr); 128 } 129 130 131 //------------------------------------------------------------ 132 // Others 133 //------------------------------------------------------------ 134 void debug_pause (void) { 135 #ifdef DbgPrn_Enable_Debug_pause 136 GET_CAHR(); 137 #endif 138 } 139 140 //------------------------------------------------------------ 141 void dump_mac_ROreg(MAC_ENGINE *p_eng) 142 { 143 int i = 0xa0; 144 145 printf("\nMAC%d base 0x%08x", p_eng->run.mac_idx, p_eng->run.mac_base); 146 printf("\n%02x:", i); 147 for (i = 0xa0; i <= 0xc8; i += 4) { 148 printf("%08x ", mac_reg_read(p_eng, i)); 149 if ((i & 0xf) == 0xc) 150 printf("\n%02x:", i + 4); 151 } 152 printf("\n"); 153 } 154 155 //------------------------------------------------------------ 156 // IO delay 157 //------------------------------------------------------------ 158 static void get_mac_1g_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 159 { 160 int tx_d, rx_d; 161 mac_delay_1g_t reg; 162 163 reg.w = readl(addr); 164 tx_d = reg.b.tx_delay_1; 165 rx_d = reg.b.rx_delay_1; 166 #ifdef CONFIG_ASPEED_AST2600 167 if (reg.b.rx_clk_inv_1 == 1) { 168 rx_d = (-1) * rx_d; 169 } 170 #endif 171 *p_tx_d = tx_d; 172 *p_rx_d = rx_d; 173 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 174 rx_d, tx_d); 175 } 176 177 static void get_mac_1g_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 178 { 179 int tx_d, rx_d; 180 mac_delay_1g_t reg; 181 182 reg.w = readl(addr); 183 tx_d = reg.b.tx_delay_2; 184 rx_d = reg.b.rx_delay_2; 185 #ifdef CONFIG_ASPEED_AST2600 186 if (reg.b.rx_clk_inv_2 == 1) { 187 rx_d = (-1) * rx_d; 188 } 189 #endif 190 *p_tx_d = tx_d; 191 *p_rx_d = rx_d; 192 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 193 rx_d, tx_d); 194 } 195 196 static void get_mac_100_10_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 197 { 198 int tx_d, rx_d; 199 mac_delay_100_10_t reg; 200 201 reg.w = readl(addr); 202 tx_d = reg.b.tx_delay_1; 203 rx_d = reg.b.rx_delay_1; 204 #ifdef CONFIG_ASPEED_AST2600 205 if (reg.b.rx_clk_inv_1 == 1) { 206 rx_d = (-1) * rx_d; 207 } 208 #endif 209 *p_tx_d = tx_d; 210 *p_rx_d = rx_d; 211 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 212 rx_d, tx_d); 213 } 214 215 static void get_mac_100_10_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 216 { 217 int tx_d, rx_d; 218 mac_delay_100_10_t reg; 219 220 reg.w = readl(addr); 221 tx_d = reg.b.tx_delay_2; 222 rx_d = reg.b.rx_delay_2; 223 #ifdef CONFIG_ASPEED_AST2600 224 if (reg.b.rx_clk_inv_2 == 1) { 225 rx_d = (-1) * rx_d; 226 } 227 #endif 228 *p_tx_d = tx_d; 229 *p_rx_d = rx_d; 230 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 231 rx_d, tx_d); 232 } 233 234 static void get_mac_rmii_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 235 { 236 mac_delay_1g_t reg; 237 238 reg.w = readl(addr); 239 *p_rx_d = reg.b.rx_delay_1; 240 *p_tx_d = reg.b.rmii_tx_data_at_falling_1; 241 242 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 243 *p_rx_d, *p_tx_d); 244 } 245 static void get_mac_rmii_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d) 246 { 247 mac_delay_1g_t reg; 248 249 reg.w = readl(addr); 250 *p_rx_d = reg.b.rx_delay_2; 251 *p_tx_d = reg.b.rmii_tx_data_at_falling_2; 252 253 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 254 *p_rx_d, *p_tx_d); 255 } 256 257 static 258 void get_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 259 { 260 get_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 261 } 262 static 263 void get_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 264 { 265 get_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d); 266 } 267 static 268 void get_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 269 { 270 get_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d); 271 } 272 static 273 void get_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 274 { 275 get_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 276 } 277 static 278 void get_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 279 { 280 get_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d); 281 } 282 static 283 void get_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 284 { 285 get_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d); 286 } 287 static 288 void get_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 289 { 290 get_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 291 } 292 static 293 void get_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 294 { 295 get_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d); 296 } 297 static 298 void get_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 299 { 300 get_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d); 301 } 302 static 303 void get_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 304 { 305 get_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 306 } 307 static 308 void get_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 309 { 310 get_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d); 311 } 312 static 313 void get_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 314 { 315 get_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d); 316 } 317 static 318 void get_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 319 { 320 get_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 321 } 322 static 323 void get_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 324 { 325 get_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d); 326 } 327 static 328 void get_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 329 { 330 get_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 331 } 332 static 333 void get_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 334 { 335 get_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d); 336 } 337 #if !defined(CONFIG_ASPEED_AST2600) 338 static 339 void get_dummy_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 340 { 341 debug("%s\n", __func__); 342 } 343 #endif 344 345 /** 346 * @brief function pointer table to get current delay setting 347 * 348 * get_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m] 349 */ 350 typedef void (*pfn_get_delay) (MAC_ENGINE *, int32_t *, int32_t *); 351 pfn_get_delay get_delay_func_tbl[2][4][3] = { 352 { 353 {get_mac1_rmii_delay, get_mac1_rmii_delay, get_mac1_rmii_delay}, 354 {get_mac2_rmii_delay, get_mac2_rmii_delay, get_mac2_rmii_delay}, 355 #if defined(CONFIG_ASPEED_AST2600) 356 {get_mac3_rmii_delay, get_mac3_rmii_delay, get_mac3_rmii_delay}, 357 {get_mac4_rmii_delay, get_mac4_rmii_delay, get_mac4_rmii_delay}, 358 #else 359 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 360 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 361 #endif 362 }, 363 { 364 {get_mac1_1g_delay, get_mac1_100m_delay, get_mac1_10m_delay}, 365 {get_mac2_1g_delay, get_mac2_100m_delay, get_mac2_10m_delay}, 366 #if defined(CONFIG_ASPEED_AST2600) 367 {get_mac3_1g_delay, get_mac3_100m_delay, get_mac3_10m_delay}, 368 {get_mac4_1g_delay, get_mac4_100m_delay, get_mac4_10m_delay}, 369 #else 370 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 371 {get_dummy_delay, get_dummy_delay, get_dummy_delay}, 372 #endif 373 } 374 }; 375 void mac_get_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 376 { 377 #if 1 378 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 379 uint32_t mac_idx = p_eng->run.mac_idx; 380 uint32_t speed_idx = p_eng->run.speed_idx; 381 382 get_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, p_rx_d, p_tx_d); 383 #else 384 /* for test */ 385 uint32_t rgmii; 386 uint32_t mac_idx; 387 uint32_t speed_idx; 388 for (rgmii = 0; rgmii < 2; rgmii++) 389 for (mac_idx = 0; mac_idx < 4; mac_idx++) 390 for (speed_idx = 0; speed_idx < 3; speed_idx++) 391 get_delay_func_tbl[rgmii][mac_idx][speed_idx]( 392 p_eng, p_rx_d, p_tx_d); 393 #endif 394 } 395 396 void mac_get_max_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 397 { 398 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 399 uint32_t mac_idx = p_eng->run.mac_idx; 400 int32_t tx_max, rx_max; 401 402 if (rgmii) { 403 if (mac_idx > 1) { 404 tx_max = p_eng->io.mac34_1g_delay.tx_max; 405 rx_max = p_eng->io.mac34_1g_delay.rx_max; 406 } else { 407 tx_max = p_eng->io.mac12_1g_delay.tx_max; 408 rx_max = p_eng->io.mac12_1g_delay.rx_max; 409 } 410 } else { 411 if (mac_idx > 1) { 412 tx_max = p_eng->io.mac34_1g_delay.rmii_tx_max; 413 rx_max = p_eng->io.mac34_1g_delay.rmii_rx_max; 414 } else { 415 tx_max = p_eng->io.mac12_1g_delay.rmii_tx_max; 416 rx_max = p_eng->io.mac12_1g_delay.rmii_rx_max; 417 } 418 } 419 *p_tx_d = tx_max; 420 *p_rx_d = rx_max; 421 } 422 423 void mac_get_min_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d) 424 { 425 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 426 uint32_t mac_idx = p_eng->run.mac_idx; 427 int32_t tx_min, rx_min; 428 429 if (rgmii) { 430 if (mac_idx > 1) { 431 tx_min = p_eng->io.mac34_1g_delay.tx_min; 432 rx_min = p_eng->io.mac34_1g_delay.rx_min; 433 } else { 434 tx_min = p_eng->io.mac12_1g_delay.tx_min; 435 rx_min = p_eng->io.mac12_1g_delay.rx_min; 436 } 437 } else { 438 if (mac_idx > 1) { 439 tx_min = p_eng->io.mac34_1g_delay.rmii_tx_min; 440 rx_min = p_eng->io.mac34_1g_delay.rmii_rx_min; 441 } else { 442 tx_min = p_eng->io.mac12_1g_delay.rmii_tx_min; 443 rx_min = p_eng->io.mac12_1g_delay.rmii_rx_min; 444 } 445 } 446 *p_tx_d = tx_min; 447 *p_rx_d = rx_min; 448 } 449 450 static void set_mac_1g_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 451 { 452 mac_delay_1g_t reg; 453 454 reg.w = readl(addr); 455 #ifdef CONFIG_ASPEED_AST2600 456 if (rx_d < 0) { 457 reg.b.rx_clk_inv_1 = 1; 458 rx_d = abs(rx_d); 459 } 460 #endif 461 reg.b.rx_delay_1 = rx_d; 462 reg.b.tx_delay_1 = tx_d; 463 writel(reg.w, addr); 464 465 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 466 rx_d, tx_d); 467 } 468 469 static void set_mac_1g_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 470 { 471 mac_delay_1g_t reg; 472 473 reg.w = readl(addr); 474 #ifdef CONFIG_ASPEED_AST2600 475 if (rx_d < 0) { 476 reg.b.rx_clk_inv_2 = 1; 477 rx_d = abs(rx_d); 478 } 479 #endif 480 reg.b.rx_delay_2 = rx_d; 481 reg.b.tx_delay_2 = tx_d; 482 writel(reg.w, addr); 483 484 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 485 rx_d, tx_d); 486 } 487 488 static void set_mac_100_10_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 489 { 490 mac_delay_100_10_t reg; 491 492 reg.w = readl(addr); 493 #ifdef CONFIG_ASPEED_AST2600 494 if (rx_d < 0) { 495 reg.b.rx_clk_inv_1 = 1; 496 rx_d = abs(rx_d); 497 } 498 #endif 499 reg.b.rx_delay_1 = rx_d; 500 reg.b.tx_delay_1 = tx_d; 501 writel(reg.w, addr); 502 503 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 504 rx_d, tx_d); 505 } 506 507 static void set_mac_100_10_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 508 { 509 mac_delay_100_10_t reg; 510 511 reg.w = readl(addr); 512 #ifdef CONFIG_ASPEED_AST2600 513 if (rx_d < 0) { 514 reg.b.rx_clk_inv_2 = 1; 515 rx_d = abs(rx_d); 516 } 517 #endif 518 reg.b.rx_delay_2 = rx_d; 519 reg.b.tx_delay_2 = tx_d; 520 writel(reg.w, addr); 521 522 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 523 rx_d, tx_d); 524 } 525 526 static void set_mac_rmii_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d) 527 { 528 mac_delay_1g_t reg; 529 530 reg.w = readl(addr); 531 reg.b.rmii_tx_data_at_falling_1 = tx_d; 532 reg.b.rx_delay_1 = rx_d; 533 writel(reg.w, addr); 534 535 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 536 rx_d, tx_d); 537 } 538 539 static void set_mac_rmii_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d) 540 { 541 mac_delay_1g_t reg; 542 543 reg.w = readl(addr); 544 reg.b.rmii_tx_data_at_falling_2 = tx_d; 545 reg.b.rx_delay_2 = rx_d; 546 writel(reg.w, addr); 547 548 debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w, 549 rx_d, tx_d); 550 } 551 552 553 static void set_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 554 { 555 set_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 556 } 557 static void set_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 558 { 559 set_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d); 560 } 561 static void set_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 562 { 563 set_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d); 564 } 565 static void set_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 566 { 567 set_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 568 } 569 static void set_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 570 { 571 set_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d); 572 } 573 static void set_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 574 { 575 set_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d); 576 } 577 static void set_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 578 { 579 set_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 580 } 581 static void set_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 582 { 583 set_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d); 584 } 585 static void set_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 586 { 587 set_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d); 588 } 589 static void set_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 590 { 591 set_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 592 } 593 static void set_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 594 { 595 set_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d); 596 } 597 static void set_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 598 { 599 set_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d); 600 } 601 static void set_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 602 { 603 set_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 604 } 605 static void set_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 606 { 607 set_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d); 608 } 609 610 static void set_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 611 { 612 set_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 613 } 614 615 static void set_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 616 { 617 set_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d); 618 } 619 620 void set_dummy_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 621 { 622 printf("%s: %d, %d\n", __func__, rx_d, tx_d); 623 } 624 625 /** 626 * @brief function pointer table for delay setting 627 * 628 * set_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m] 629 */ 630 typedef void (*pfn_set_delay) (MAC_ENGINE *, int32_t, int32_t); 631 pfn_set_delay set_delay_func_tbl[2][4][3] = { 632 { 633 {set_mac1_rmii_delay, set_mac1_rmii_delay, set_mac1_rmii_delay}, 634 {set_mac2_rmii_delay, set_mac2_rmii_delay, set_mac2_rmii_delay}, 635 #if defined(CONFIG_ASPEED_AST2600) 636 {set_mac3_rmii_delay, set_mac3_rmii_delay, set_mac3_rmii_delay}, 637 {set_mac4_rmii_delay, set_mac4_rmii_delay, set_mac4_rmii_delay}, 638 #else 639 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 640 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 641 #endif 642 }, 643 { 644 {set_mac1_1g_delay, set_mac1_100m_delay, set_mac1_10m_delay}, 645 {set_mac2_1g_delay, set_mac2_100m_delay, set_mac2_10m_delay}, 646 #if defined(CONFIG_ASPEED_AST2600) 647 {set_mac3_1g_delay, set_mac3_100m_delay, set_mac3_10m_delay}, 648 {set_mac4_1g_delay, set_mac4_100m_delay, set_mac4_10m_delay}, 649 #else 650 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 651 {set_dummy_delay, set_dummy_delay, set_dummy_delay}, 652 #endif 653 } 654 }; 655 656 void mac_set_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d) 657 { 658 uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii; 659 uint32_t mac_idx = p_eng->run.mac_idx; 660 uint32_t speed_idx = p_eng->run.speed_idx; 661 662 set_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, rx_d, tx_d); 663 } 664 665 uint32_t mac_get_driving_strength(MAC_ENGINE *p_eng) 666 { 667 #ifdef CONFIG_ASPEED_AST2600 668 mac34_drv_t reg; 669 670 reg.w = readl(p_eng->io.mac34_drv_reg.addr); 671 /* ast2600 : only MAC#3 & MAC#4 have driving strength setting */ 672 if (p_eng->run.mac_idx == 2) { 673 return (reg.b.mac3_tx_drv); 674 } else if (p_eng->run.mac_idx == 3) { 675 return (reg.b.mac4_tx_drv); 676 } else { 677 return 0; 678 } 679 #else 680 mac12_drv_t reg; 681 682 reg.w = readl(p_eng->io.mac12_drv_reg.addr); 683 684 if (p_eng->run.mac_idx == 0) { 685 return (reg.b.mac1_tx_drv); 686 } else if (p_eng->run.mac_idx == 1) { 687 return (reg.b.mac2_tx_drv); 688 } else { 689 return 0; 690 } 691 #endif 692 } 693 void mac_set_driving_strength(MAC_ENGINE *p_eng, uint32_t strength) 694 { 695 #ifdef CONFIG_ASPEED_AST2600 696 mac34_drv_t reg; 697 698 if (strength > p_eng->io.mac34_drv_reg.drv_max) { 699 printf("invalid driving strength value\n"); 700 return; 701 } 702 703 /** 704 * read->modify->write for driving strength control register 705 * ast2600 : only MAC#3 & MAC#4 have driving strength setting 706 */ 707 reg.w = readl(p_eng->io.mac34_drv_reg.addr); 708 709 /* ast2600 : only MAC#3 & MAC#4 have driving strength setting */ 710 if (p_eng->run.mac_idx == 2) { 711 reg.b.mac3_tx_drv = strength; 712 } else if (p_eng->run.mac_idx == 3) { 713 reg.b.mac4_tx_drv = strength; 714 } 715 716 writel(reg.w, p_eng->io.mac34_drv_reg.addr); 717 #else 718 mac12_drv_t reg; 719 720 if (strength > p_eng->io.mac12_drv_reg.drv_max) { 721 printf("invalid driving strength value\n"); 722 return; 723 } 724 725 /* read->modify->write for driving strength control register */ 726 reg.w = readl(p_eng->io.mac12_drv_reg.addr); 727 if (p_eng->run.is_rgmii) { 728 if (p_eng->run.mac_idx == 0) { 729 reg.b.mac1_rgmii_tx_drv = 730 strength; 731 } else if (p_eng->run.mac_idx == 2) { 732 reg.b.mac2_rgmii_tx_drv = 733 strength; 734 } 735 } else { 736 if (p_eng->run.mac_idx == 0) { 737 reg.b.mac1_rmii_tx_drv = 738 strength; 739 } else if (p_eng->run.mac_idx == 1) { 740 reg.b.mac2_rmii_tx_drv = 741 strength; 742 } 743 } 744 writel(reg.w, p_eng->io.mac12_drv_reg.addr); 745 #endif 746 } 747 748 void mac_set_rmii_50m_output_enable(MAC_ENGINE *p_eng) 749 { 750 uint32_t addr; 751 mac_delay_1g_t value; 752 753 if (p_eng->run.mac_idx > 1) { 754 addr = p_eng->io.mac34_1g_delay.addr; 755 } else { 756 addr = p_eng->io.mac12_1g_delay.addr; 757 } 758 759 value.w = readl(addr); 760 if (p_eng->run.mac_idx & BIT(0)) { 761 value.b.rmii_50m_oe_2 = 1; 762 } else { 763 value.b.rmii_50m_oe_1 = 1; 764 } 765 writel(value.w, addr); 766 } 767 768 //------------------------------------------------------------ 769 int mac_set_scan_boundary(MAC_ENGINE *p_eng) 770 { 771 int32_t rx_cur, tx_cur; 772 int32_t rx_min, rx_max, tx_min, tx_max; 773 int32_t rx_scaling, tx_scaling; 774 775 nt_log_func_name(); 776 777 /* get current delay setting */ 778 mac_get_delay(p_eng, &rx_cur, &tx_cur); 779 780 /* get physical boundaries */ 781 mac_get_max_available_delay(p_eng, &rx_max, &tx_max); 782 mac_get_min_available_delay(p_eng, &rx_min, &tx_min); 783 784 if ((p_eng->run.is_rgmii) && (p_eng->arg.ctrl.b.inv_rgmii_rxclk)) { 785 rx_max = (rx_max > 0) ? 0 : rx_max; 786 } else { 787 rx_min = (rx_min < 0) ? 0 : rx_min; 788 } 789 790 if (p_eng->run.TM_IOTiming) { 791 if (p_eng->arg.ctrl.b.full_range) { 792 tx_scaling = 0; 793 rx_scaling = 0; 794 } else { 795 /* down-scaling to save test time */ 796 tx_scaling = TX_DELAY_SCALING; 797 rx_scaling = RX_DELAY_SCALING; 798 } 799 p_eng->io.rx_delay_scan.step = 1; 800 p_eng->io.tx_delay_scan.step = 1; 801 p_eng->io.rx_delay_scan.begin = rx_min >> rx_scaling; 802 p_eng->io.rx_delay_scan.end = rx_max >> rx_scaling; 803 p_eng->io.tx_delay_scan.begin = tx_min >> tx_scaling; 804 p_eng->io.tx_delay_scan.end = tx_max >> tx_scaling; 805 } else if (p_eng->run.delay_margin) { 806 p_eng->io.rx_delay_scan.step = 1; 807 p_eng->io.tx_delay_scan.step = 1; 808 p_eng->io.rx_delay_scan.begin = rx_cur - p_eng->run.delay_margin; 809 p_eng->io.rx_delay_scan.end = rx_cur + p_eng->run.delay_margin; 810 p_eng->io.tx_delay_scan.begin = tx_cur - p_eng->run.delay_margin; 811 p_eng->io.tx_delay_scan.end = tx_cur + p_eng->run.delay_margin; 812 } else { 813 p_eng->io.rx_delay_scan.step = 1; 814 p_eng->io.tx_delay_scan.step = 1; 815 p_eng->io.rx_delay_scan.begin = 0; 816 p_eng->io.rx_delay_scan.end = 0; 817 p_eng->io.tx_delay_scan.begin = 0; 818 p_eng->io.tx_delay_scan.end = 0; 819 } 820 821 /* backup current setting as the original for plotting result */ 822 p_eng->io.rx_delay_scan.orig = rx_cur; 823 p_eng->io.tx_delay_scan.orig = tx_cur; 824 825 /* check if setting is legal or not */ 826 if (p_eng->io.rx_delay_scan.begin < rx_min) 827 p_eng->io.rx_delay_scan.begin = rx_min; 828 829 if (p_eng->io.tx_delay_scan.begin < tx_min) 830 p_eng->io.tx_delay_scan.begin = tx_min; 831 832 if (p_eng->io.rx_delay_scan.end > rx_max) 833 p_eng->io.rx_delay_scan.end = rx_max; 834 835 if (p_eng->io.tx_delay_scan.end > tx_max) 836 p_eng->io.tx_delay_scan.end = tx_max; 837 838 if (p_eng->io.rx_delay_scan.begin > p_eng->io.rx_delay_scan.end) 839 p_eng->io.rx_delay_scan.begin = p_eng->io.rx_delay_scan.end; 840 841 if (p_eng->io.tx_delay_scan.begin > p_eng->io.tx_delay_scan.end) 842 p_eng->io.tx_delay_scan.begin = p_eng->io.tx_delay_scan.end; 843 844 if (p_eng->run.IO_MrgChk) { 845 if ((p_eng->io.rx_delay_scan.orig < 846 p_eng->io.rx_delay_scan.begin) || 847 (p_eng->io.rx_delay_scan.orig > 848 p_eng->io.rx_delay_scan.end)) { 849 printf("Warning: current delay is not in the " 850 "scan-range\n"); 851 printf("RX delay scan range:%d ~ %d, curr:%d\n", 852 p_eng->io.rx_delay_scan.begin, 853 p_eng->io.rx_delay_scan.end, 854 p_eng->io.rx_delay_scan.orig); 855 printf("TX delay scan range:%d ~ %d, curr:%d\n", 856 p_eng->io.tx_delay_scan.begin, 857 p_eng->io.tx_delay_scan.end, 858 p_eng->io.tx_delay_scan.orig); 859 } 860 } 861 862 return (0); 863 } 864 865 //------------------------------------------------------------ 866 // MAC 867 //------------------------------------------------------------ 868 void mac_set_addr(MAC_ENGINE *p_eng) 869 { 870 nt_log_func_name(); 871 872 uint32_t madr = p_eng->reg.mac_madr; 873 uint32_t ladr = p_eng->reg.mac_ladr; 874 875 if (((madr == 0x0000) && (ladr == 0x00000000)) || 876 ((madr == 0xffff) && (ladr == 0xffffffff))) { 877 /* FIXME: shall use random gen */ 878 madr = 0x0000000a; 879 ladr = 0xf7837dd4; 880 } 881 882 p_eng->inf.SA[0] = (madr >> 8) & 0xff; // MSB 883 p_eng->inf.SA[1] = (madr >> 0) & 0xff; 884 p_eng->inf.SA[2] = (ladr >> 24) & 0xff; 885 p_eng->inf.SA[3] = (ladr >> 16) & 0xff; 886 p_eng->inf.SA[4] = (ladr >> 8) & 0xff; 887 p_eng->inf.SA[5] = (ladr >> 0) & 0xff; // LSB 888 889 printf("mac address: "); 890 for (int i = 0; i < 6; i++) { 891 printf("%02x:", p_eng->inf.SA[i]); 892 } 893 printf("\n"); 894 } 895 896 void mac_set_interal_loopback(MAC_ENGINE *p_eng) 897 { 898 uint32_t reg = mac_reg_read(p_eng, 0x40); 899 mac_reg_write(p_eng, 0x40, reg | BIT(30)); 900 } 901 902 //------------------------------------------------------------ 903 void init_mac (MAC_ENGINE *eng) 904 { 905 nt_log_func_name(); 906 907 mac_cr_t maccr; 908 909 #ifdef Enable_MAC_SWRst 910 maccr.w = 0; 911 maccr.b.sw_rst = 1; 912 mac_reg_write(eng, 0x50, maccr.w); 913 914 do { 915 DELAY(Delay_MACRst); 916 maccr.w = mac_reg_read(eng, 0x50); 917 } while(maccr.b.sw_rst); 918 #endif 919 920 mac_reg_write(eng, 0x20, eng->run.tdes_base - ASPEED_DRAM_BASE); 921 mac_reg_write(eng, 0x24, eng->run.rdes_base - ASPEED_DRAM_BASE); 922 923 mac_reg_write(eng, 0x08, eng->reg.mac_madr); 924 mac_reg_write(eng, 0x0c, eng->reg.mac_ladr); 925 926 #ifdef MAC_030_def 927 mac_reg_write( eng, 0x30, MAC_030_def );//Int Thr/Cnt 928 #endif 929 #ifdef MAC_034_def 930 mac_reg_write( eng, 0x34, MAC_034_def );//Poll Cnt 931 #endif 932 #ifdef MAC_038_def 933 mac_reg_write( eng, 0x38, MAC_038_def ); 934 #endif 935 #ifdef MAC_048_def 936 mac_reg_write( eng, 0x48, MAC_048_def ); 937 #endif 938 #ifdef MAC_058_def 939 mac_reg_write( eng, 0x58, MAC_058_def ); 940 #endif 941 942 if ( eng->arg.run_mode == MODE_NCSI ) 943 mac_reg_write( eng, 0x4c, NCSI_RxDMA_PakSize ); 944 else 945 mac_reg_write( eng, 0x4c, DMA_PakSize ); 946 947 maccr.b.txdma_en = 1; 948 maccr.b.rxdma_en = 1; 949 maccr.b.txmac_en = 1; 950 maccr.b.rxmac_en = 1; 951 maccr.b.fulldup = 1; 952 maccr.b.crc_apd = 1; 953 954 if (eng->run.speed_sel[0]) { 955 maccr.b.gmac_mode = 1; 956 } else if (eng->run.speed_sel[1]) { 957 maccr.b.speed_100 = 1; 958 } 959 960 if (eng->arg.run_mode == MODE_NCSI) { 961 maccr.b.rx_broadpkt_en = 1; 962 maccr.b.speed_100 = 1; 963 } 964 else { 965 maccr.b.rx_alladr = 1; 966 #ifdef Enable_Runt 967 maccr.b.rx_runt = 1; 968 #endif 969 } 970 mac_reg_write(eng, 0x50, maccr.w); 971 DELAY(Delay_MACRst); 972 } // End void init_mac (MAC_ENGINE *eng) 973 974 //------------------------------------------------------------ 975 // Basic 976 //------------------------------------------------------------ 977 void FPri_RegValue (MAC_ENGINE *eng, uint8_t option) 978 { 979 nt_log_func_name(); 980 981 PRINTF( option, "[SRAM] Date:%08x\n", SRAM_RD( 0x88 ) ); 982 PRINTF( option, "[SRAM] 80:%08x %08x %08x %08x\n", SRAM_RD( 0x80 ), SRAM_RD( 0x84 ), SRAM_RD( 0x88 ), SRAM_RD( 0x8c ) ); 983 984 PRINTF( option, "[SCU] a0:%08x a4:%08x b8:%08x bc:%08x\n", SCU_RD( 0x0a0 ), SCU_RD( 0x0a4 ), SCU_RD( 0x0b8 ), SCU_RD( 0x0bc )); 985 986 PRINTF( option, "[SCU] 13c:%08x 140:%08x 144:%08x 1dc:%08x\n", SCU_RD( 0x13c ), SCU_RD( 0x140 ), SCU_RD( 0x144 ), SCU_RD( 0x1dc ) ); 987 PRINTF( option, "[WDT] 0c:%08x 2c:%08x 4c:%08x\n", eng->reg.WDT_00c, eng->reg.WDT_02c, eng->reg.WDT_04c ); 988 PRINTF( option, "[MAC] A0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xa0 ), mac_reg_read( eng, 0xa4 ), mac_reg_read( eng, 0xa8 ), mac_reg_read( eng, 0xac ) ); 989 PRINTF( option, "[MAC] B0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xb0 ), mac_reg_read( eng, 0xb4 ), mac_reg_read( eng, 0xb8 ), mac_reg_read( eng, 0xbc ) ); 990 PRINTF( option, "[MAC] C0|%08x %08x %08x\n", mac_reg_read( eng, 0xc0 ), mac_reg_read( eng, 0xc4 ), mac_reg_read( eng, 0xc8 ) ); 991 992 } // End void FPri_RegValue (MAC_ENGINE *eng, uint8_t *fp) 993 994 //------------------------------------------------------------ 995 void FPri_End (MAC_ENGINE *eng, uint8_t option) 996 { 997 nt_log_func_name(); 998 if ((0 == eng->run.is_rgmii) && (eng->phy.RMIICK_IOMode != 0) && 999 eng->run.IO_MrgChk && eng->flg.all_fail) { 1000 if ( eng->arg.ctrl.b.rmii_phy_in == 0 ) { 1001 PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the OUTPUT mode now.\n" ); 1002 PRINTF( option, " Maybe you can run the INPUT mode command \"mactest %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w | 0x80), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range ); 1003 } 1004 else { 1005 PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the INPUT mode now.\n" ); 1006 PRINTF( option, " Maybe you can run the OUTPUT mode command \"mactest %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w & 0x7f), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range ); 1007 } 1008 } 1009 1010 if (!eng->run.TM_RxDataEn) { 1011 } else if (eng->flg.error) { 1012 PRINTF(option, " \n----> fail !!!\n"); 1013 } 1014 1015 //------------------------------ 1016 //[Warning] PHY Address 1017 //------------------------------ 1018 if ( eng->arg.run_mode == MODE_DEDICATED ) { 1019 if ( eng->arg.phy_addr != eng->phy.Adr ) 1020 PRINTF( option, "\n[Warning] PHY Address change from %d to %d !!!\n", eng->arg.phy_addr, eng->phy.Adr ); 1021 } 1022 1023 //------------------------------ 1024 //[Warning] IO Strength 1025 //------------------------------ 1026 #ifdef CONFIG_ASPEED_AST2600 1027 if (eng->io.init_done && (eng->io.mac34_drv_reg.value.w != 0xf)) { 1028 PRINTF(option, 1029 "\n[Warning] [%08X] 0x%08x is not the suggestion value " 1030 "0xf.\n", 1031 eng->io.mac34_drv_reg.addr, 1032 eng->io.mac34_drv_reg.value.w); 1033 #else 1034 if (eng->io.init_done && eng->io.mac12_drv_reg.value.w) { 1035 PRINTF(option, 1036 "\n[Warning] [%08X] 0x%08x is not the suggestion value " 1037 "0.\n", 1038 eng->io.mac12_drv_reg.addr, 1039 eng->io.mac12_drv_reg.value.w); 1040 #endif 1041 PRINTF(option, " This change at this platform must " 1042 "been proven again by the ASPEED.\n"); 1043 } 1044 1045 //------------------------------ 1046 //[Warning] IO Timing 1047 //------------------------------ 1048 if ( eng->arg.run_mode == MODE_NCSI ) { 1049 PRINTF( option, "\n[Arg] %d %d %d %d %d %d %d {%d}\n", eng->arg.mac_idx, eng->arg.GPackageTolNum, eng->arg.GChannelTolNum, eng->arg.test_mode, eng->arg.delay_scan_range, eng->arg.ctrl.w, eng->arg.GARPNumCnt, TIME_OUT_NCSI ); 1050 1051 switch ( eng->ncsi_cap.PCI_DID_VID ) { 1052 case PCI_DID_VID_Intel_82574L : { PRINTF( option, "[NC]%08x %08x: Intel 82574L \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1053 case PCI_DID_VID_Intel_82575_10d6 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1054 case PCI_DID_VID_Intel_82575_10a7 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1055 case PCI_DID_VID_Intel_82575_10a9 : { PRINTF( option, "[NC]%08x %08x: Intel 82575 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1056 case PCI_DID_VID_Intel_82576_10c9 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1057 case PCI_DID_VID_Intel_82576_10e6 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1058 case PCI_DID_VID_Intel_82576_10e7 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1059 case PCI_DID_VID_Intel_82576_10e8 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1060 case PCI_DID_VID_Intel_82576_1518 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1061 case PCI_DID_VID_Intel_82576_1526 : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1062 case PCI_DID_VID_Intel_82576_150a : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1063 case PCI_DID_VID_Intel_82576_150d : { PRINTF( option, "[NC]%08x %08x: Intel 82576 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1064 case PCI_DID_VID_Intel_82599_10fb : { PRINTF( option, "[NC]%08x %08x: Intel 82599 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1065 case PCI_DID_VID_Intel_82599_1557 : { PRINTF( option, "[NC]%08x %08x: Intel 82599 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1066 case PCI_DID_VID_Intel_I210_1533 : { PRINTF( option, "[NC]%08x %08x: Intel I210 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1067 case PCI_DID_VID_Intel_I210_1537 : { PRINTF( option, "[NC]%08x %08x: Intel I210 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1068 case PCI_DID_VID_Intel_I350_1521 : { PRINTF( option, "[NC]%08x %08x: Intel I350 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1069 case PCI_DID_VID_Intel_I350_1523 : { PRINTF( option, "[NC]%08x %08x: Intel I350 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1070 case PCI_DID_VID_Intel_X540 : { PRINTF( option, "[NC]%08x %08x: Intel X540 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1071 case PCI_DID_VID_Intel_X550 : { PRINTF( option, "[NC]%08x %08x: Intel X550 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1072 case PCI_DID_VID_Intel_Broadwell_DE : { PRINTF( option, "[NC]%08x %08x: Intel Broadwell-DE \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1073 case PCI_DID_VID_Intel_X722_37d0 : { PRINTF( option, "[NC]%08x %08x: Intel X722 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1074 case PCI_DID_VID_Broadcom_BCM5718 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5718 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1075 case PCI_DID_VID_Broadcom_BCM5719 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5719 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1076 case PCI_DID_VID_Broadcom_BCM5720 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5720 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1077 case PCI_DID_VID_Broadcom_BCM5725 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5725 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1078 case PCI_DID_VID_Broadcom_BCM57810S : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57810S \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1079 case PCI_DID_VID_Broadcom_Cumulus : { PRINTF( option, "[NC]%08x %08x: Broadcom Cumulus \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1080 case PCI_DID_VID_Broadcom_BCM57302 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57302 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1081 case PCI_DID_VID_Broadcom_BCM957452 : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM957452 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1082 case PCI_DID_VID_Mellanox_ConnectX_3_1003 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1083 case PCI_DID_VID_Mellanox_ConnectX_3_1007 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1084 case PCI_DID_VID_Mellanox_ConnectX_4 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-4\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1085 default: 1086 switch ( eng->ncsi_cap.manufacturer_id ) { 1087 case ManufacturerID_Intel : { PRINTF( option, "[NC]%08x %08x: Intel \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1088 case ManufacturerID_Broadcom : { PRINTF( option, "[NC]%08x %08x: Broadcom \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1089 case ManufacturerID_Mellanox : { PRINTF( option, "[NC]%08x %08x: Mellanox \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1090 case ManufacturerID_Mellanox1: { PRINTF( option, "[NC]%08x %08x: Mellanox \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1091 case ManufacturerID_Emulex : { PRINTF( option, "[NC]%08x %08x: Emulex \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1092 default : { PRINTF( option, "[NC]%08x %08x \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; } 1093 } // End switch ( eng->ncsi_cap.manufacturer_id ) 1094 } // End switch ( eng->ncsi_cap.PCI_DID_VID ) 1095 } 1096 else { 1097 PRINTF(option, "[PHY] @addr %d: id = %04x_%04x (%s)\n", 1098 eng->phy.Adr, eng->phy.id1, eng->phy.id2, 1099 eng->phy.phy_name); 1100 } // End if ( eng->arg.run_mode == MODE_NCSI ) 1101 } // End void FPri_End (MAC_ENGINE *eng, uint8_t option) 1102 1103 //------------------------------------------------------------ 1104 void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option) 1105 { 1106 nt_log_func_name(); 1107 if ( eng->flg.print_en ) { 1108 if ( eng->flg.warn ) { 1109 if ( eng->flg.warn & Wrn_Flag_IOMarginOUF ) { 1110 PRINTF(option, "[Warning] IO timing testing " 1111 "range out of boundary\n"); 1112 1113 if (0 == eng->run.is_rgmii) { 1114 PRINTF( option, " (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx, 1115 eng->io.Dly_out_reg_idx, 1116 eng->run.delay_margin, 1117 eng->io.Dly_in_min, 1118 eng->io.Dly_in_max, 1119 eng->io.Dly_out_min ); 1120 } 1121 else { 1122 PRINTF( option, " (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx, 1123 eng->io.Dly_out_reg_idx, 1124 eng->run.delay_margin, 1125 eng->run.delay_margin, 1126 eng->io.Dly_in_min, 1127 eng->io.Dly_in_max, 1128 eng->io.Dly_out_min, 1129 eng->io.Dly_out_max ); 1130 } 1131 } // End if ( eng->flg.warn & Wrn_Flag_IOMarginOUF ) 1132 if ( eng->flg.warn & Wrn_Flag_RxErFloatting ) { 1133 PRINTF( option, "[Warning] NCSI RXER pin may be floatting to the MAC !!!\n" ); 1134 PRINTF( option, " Please contact with the ASPEED Inc. for more help.\n" ); 1135 } // End if ( eng->flg.warn & Wrn_Flag_RxErFloatting ) 1136 } // End if ( eng->flg.warn ) 1137 1138 if ( eng->flg.error ) { 1139 PRINTF( option, "\n\n" ); 1140 //PRINTF( option, "error: %x\n\n", eng->flg.error ); 1141 1142 if ( eng->flg.error & Err_Flag_PHY_Type ) { PRINTF( option, "[Err] Unidentifiable PHY \n" ); } 1143 if ( eng->flg.error & Err_Flag_MALLOC_FrmSize ) { PRINTF( option, "[Err] Malloc fail at frame size buffer \n" ); } 1144 if ( eng->flg.error & Err_Flag_MALLOC_LastWP ) { PRINTF( option, "[Err] Malloc fail at last WP buffer \n" ); } 1145 if ( eng->flg.error & Err_Flag_Check_Buf_Data ) { PRINTF( option, "[Err] Received data mismatch \n" ); } 1146 if ( eng->flg.error & Err_Flag_NCSI_Check_TxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Tx owner bit in NCSI packet \n" ); } 1147 if ( eng->flg.error & Err_Flag_NCSI_Check_RxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Rx owner bit in NCSI packet \n" ); } 1148 if ( eng->flg.error & Err_Flag_NCSI_Check_ARPOwnTimeOut) { PRINTF( option, "[Err] Time out of checking ARP owner bit in NCSI packet \n" ); } 1149 if ( eng->flg.error & Err_Flag_NCSI_No_PHY ) { PRINTF( option, "[Err] Can not find NCSI PHY \n" ); } 1150 if ( eng->flg.error & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[Err] NCSI Channel Number Mismatch \n" ); } 1151 if ( eng->flg.error & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[Err] NCSI Package Number Mismatch \n" ); } 1152 if ( eng->flg.error & Err_Flag_PHY_TimeOut_RW ) { PRINTF( option, "[Err] Time out of read/write PHY register \n" ); } 1153 if ( eng->flg.error & Err_Flag_PHY_TimeOut_Rst ) { PRINTF( option, "[Err] Time out of reset PHY register \n" ); } 1154 if ( eng->flg.error & Err_Flag_RXBUF_UNAVA ) { PRINTF( option, "[Err] MAC00h[2]:Receiving buffer unavailable \n" ); } 1155 if ( eng->flg.error & Err_Flag_RPKT_LOST ) { PRINTF( option, "[Err] MAC00h[3]:Received packet lost due to RX FIFO full \n" ); } 1156 if ( eng->flg.error & Err_Flag_NPTXBUF_UNAVA ) { PRINTF( option, "[Err] MAC00h[6]:Normal priority transmit buffer unavailable \n" ); } 1157 if ( eng->flg.error & Err_Flag_TPKT_LOST ) { PRINTF( option, "[Err] MAC00h[7]:Packets transmitted to Ethernet lost \n" ); } 1158 if ( eng->flg.error & Err_Flag_DMABufNum ) { PRINTF( option, "[Err] DMA Buffer is not enough \n" ); } 1159 if ( eng->flg.error & Err_Flag_IOMargin ) { PRINTF( option, "[Err] IO timing margin is not enough \n" ); } 1160 1161 if ( eng->flg.error & Err_Flag_MHCLK_Ratio ) { 1162 PRINTF( option, "[Err] Error setting of MAC AHB bus clock (SCU08[18:16]) \n" ); 1163 if ( eng->env.at_least_1g_valid ) 1164 { PRINTF( option, " SCU08[18:16] == 0x%01x is not the suggestion value 2.\n", eng->env.MHCLK_Ratio ); } 1165 else 1166 { PRINTF( option, " SCU08[18:16] == 0x%01x is not the suggestion value 4.\n", eng->env.MHCLK_Ratio ); } 1167 } // End if ( eng->flg.error & Err_Flag_MHCLK_Ratio ) 1168 1169 if ( eng->flg.error & Err_Flag_IOMarginOUF ) { 1170 PRINTF( option, "[Err] IO timing testing range out of boundary\n"); 1171 if (0 == eng->run.is_rgmii) { 1172 PRINTF( option, " (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx, 1173 eng->io.Dly_out_reg_idx, 1174 eng->run.delay_margin, 1175 eng->io.Dly_in_min, 1176 eng->io.Dly_in_max, 1177 eng->io.Dly_out_min ); 1178 } 1179 else { 1180 PRINTF( option, " (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx, 1181 eng->io.Dly_out_reg_idx, 1182 eng->run.delay_margin, 1183 eng->run.delay_margin, 1184 eng->io.Dly_in_min, 1185 eng->io.Dly_in_max, 1186 eng->io.Dly_out_min, 1187 eng->io.Dly_out_max ); 1188 } 1189 } // End if ( eng->flg.error & Err_Flag_IOMarginOUF ) 1190 1191 if ( eng->flg.error & Err_Flag_Check_Des ) { 1192 PRINTF( option, "[Err] Descriptor error\n"); 1193 if ( eng->flg.desc & Des_Flag_TxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Tx owner bit\n" ); } 1194 if ( eng->flg.desc & Des_Flag_RxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Rx owner bit\n" ); } 1195 if ( eng->flg.desc & Des_Flag_FrameLen ) { PRINTF( option, "[Des] Frame length mismatch \n" ); } 1196 if ( eng->flg.desc & Des_Flag_RxErr ) { PRINTF( option, "[Des] Input signal RxErr \n" ); } 1197 if ( eng->flg.desc & Des_Flag_CRC ) { PRINTF( option, "[Des] CRC error of frame \n" ); } 1198 if ( eng->flg.desc & Des_Flag_FTL ) { PRINTF( option, "[Des] Frame too long \n" ); } 1199 if ( eng->flg.desc & Des_Flag_Runt ) { PRINTF( option, "[Des] Runt packet \n" ); } 1200 if ( eng->flg.desc & Des_Flag_OddNibble ) { PRINTF( option, "[Des] Nibble bit happen \n" ); } 1201 if ( eng->flg.desc & Des_Flag_RxFIFOFull ) { PRINTF( option, "[Des] Rx FIFO full \n" ); } 1202 } // End if ( eng->flg.error & Err_Flag_Check_Des ) 1203 1204 if ( eng->flg.error & Err_Flag_MACMode ) { 1205 PRINTF( option, "[Err] MAC interface mode mismatch\n" ); 1206 for (int i = 0; i < 4; i++) { 1207 if (eng->env.is_1g_valid[i]) { 1208 PRINTF(option, 1209 "[MAC%d] is RGMII\n", i); 1210 } else { 1211 PRINTF(option, 1212 "[MAC%d] RMII\n", i); 1213 } 1214 } 1215 } // End if ( eng->flg.error & Err_Flag_MACMode ) 1216 1217 if ( eng->arg.run_mode == MODE_NCSI ) { 1218 if ( eng->flg.error & ERR_FLAG_NCSI_LINKFAIL ) { 1219 PRINTF( option, "[Err] NCSI packet retry number over flows when find channel\n" ); 1220 1221 if ( eng->flg.ncsi & NCSI_Flag_Get_Version_ID ) { PRINTF( option, "[NCSI] Time out when Get Version ID \n" ); } 1222 if ( eng->flg.ncsi & NCSI_Flag_Get_Capabilities ) { PRINTF( option, "[NCSI] Time out when Get Capabilities \n" ); } 1223 if ( eng->flg.ncsi & NCSI_Flag_Select_Active_Package ) { PRINTF( option, "[NCSI] Time out when Select Active Package \n" ); } 1224 if ( eng->flg.ncsi & NCSI_Flag_Enable_Set_MAC_Address ) { PRINTF( option, "[NCSI] Time out when Enable Set MAC Address \n" ); } 1225 if ( eng->flg.ncsi & NCSI_Flag_Enable_Broadcast_Filter ) { PRINTF( option, "[NCSI] Time out when Enable Broadcast Filter \n" ); } 1226 if ( eng->flg.ncsi & NCSI_Flag_Enable_Network_TX ) { PRINTF( option, "[NCSI] Time out when Enable Network TX \n" ); } 1227 if ( eng->flg.ncsi & NCSI_Flag_Enable_Channel ) { PRINTF( option, "[NCSI] Time out when Enable Channel \n" ); } 1228 if ( eng->flg.ncsi & NCSI_Flag_Disable_Network_TX ) { PRINTF( option, "[NCSI] Time out when Disable Network TX \n" ); } 1229 if ( eng->flg.ncsi & NCSI_Flag_Disable_Channel ) { PRINTF( option, "[NCSI] Time out when Disable Channel \n" ); } 1230 if ( eng->flg.ncsi & NCSI_Flag_Select_Package ) { PRINTF( option, "[NCSI] Time out when Select Package \n" ); } 1231 if ( eng->flg.ncsi & NCSI_Flag_Deselect_Package ) { PRINTF( option, "[NCSI] Time out when Deselect Package \n" ); } 1232 if ( eng->flg.ncsi & NCSI_Flag_Set_Link ) { PRINTF( option, "[NCSI] Time out when Set Link \n" ); } 1233 if ( eng->flg.ncsi & NCSI_Flag_Get_Controller_Packet_Statistics) { PRINTF( option, "[NCSI] Time out when Get Controller Packet Statistics\n" ); } 1234 } 1235 1236 if ( eng->flg.error & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[NCSI] Channel number expected: %d, real: %d\n", eng->arg.GChannelTolNum, eng->dat.number_chl ); } 1237 if ( eng->flg.error & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[NCSI] Peckage number expected: %d, real: %d\n", eng->arg.GPackageTolNum, eng->dat.number_pak ); } 1238 } // End if ( eng->arg.run_mode == MODE_NCSI ) 1239 } // End if ( eng->flg.error ) 1240 } // End if ( eng->flg.print_en ) 1241 } // End void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option) 1242 1243 //------------------------------------------------------------ 1244 1245 //------------------------------------------------------------ 1246 int FindErr (MAC_ENGINE *p_eng, int value) 1247 { 1248 p_eng->flg.error = p_eng->flg.error | value; 1249 1250 if (DBG_PRINT_ERR_FLAG) 1251 printf("flags: error = %08x\n", p_eng->flg.error); 1252 1253 return (1); 1254 } 1255 1256 //------------------------------------------------------------ 1257 int FindErr_Des (MAC_ENGINE *p_eng, int value) 1258 { 1259 p_eng->flg.error = p_eng->flg.error | Err_Flag_Check_Des; 1260 p_eng->flg.desc = p_eng->flg.desc | value; 1261 if (DBG_PRINT_ERR_FLAG) 1262 printf("flags: error = %08x, desc = %08x\n", p_eng->flg.error, p_eng->flg.desc); 1263 1264 return (1); 1265 } 1266 1267 //------------------------------------------------------------ 1268 // Get and Check status of Interrupt 1269 //------------------------------------------------------------ 1270 int check_int (MAC_ENGINE *eng, char *type ) 1271 { 1272 nt_log_func_name(); 1273 1274 uint32_t mac_00; 1275 1276 mac_00 = mac_reg_read(eng, 0x00); 1277 #ifdef CheckRxbufUNAVA 1278 if (mac_00 & BIT(2)) { 1279 PRINTF( FP_LOG, "[%sIntStatus] Receiving buffer unavailable : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1280 FindErr( eng, Err_Flag_RXBUF_UNAVA ); 1281 } 1282 #endif 1283 1284 #ifdef CheckRPktLost 1285 if (mac_00 & BIT(3)) { 1286 PRINTF( FP_LOG, "[%sIntStatus] Received packet lost due to RX FIFO full : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1287 FindErr( eng, Err_Flag_RPKT_LOST ); 1288 } 1289 #endif 1290 1291 #ifdef CheckNPTxbufUNAVA 1292 if (mac_00 & BIT(6) ) { 1293 PRINTF( FP_LOG, "[%sIntStatus] Normal priority transmit buffer unavailable: %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1294 FindErr( eng, Err_Flag_NPTXBUF_UNAVA ); 1295 } 1296 #endif 1297 1298 #ifdef CheckTPktLost 1299 if (mac_00 & BIT(7)) { 1300 PRINTF( FP_LOG, "[%sIntStatus] Packets transmitted to Ethernet lost : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1301 FindErr( eng, Err_Flag_TPKT_LOST ); 1302 } 1303 #endif 1304 1305 if ( eng->flg.error ) 1306 return(1); 1307 else 1308 return(0); 1309 } // End int check_int (MAC_ENGINE *eng, char *type) 1310 1311 1312 //------------------------------------------------------------ 1313 // Buffer 1314 //------------------------------------------------------------ 1315 void setup_framesize (MAC_ENGINE *eng) 1316 { 1317 int32_t des_num; 1318 1319 nt_log_func_name(); 1320 1321 //------------------------------ 1322 // Fill Frame Size out descriptor area 1323 //------------------------------ 1324 if (0) { 1325 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1326 if ( RAND_SIZE_SIMPLE ) 1327 switch( rand() % 5 ) { 1328 case 0 : eng->dat.FRAME_LEN[ des_num ] = 0x4e ; break; 1329 case 1 : eng->dat.FRAME_LEN[ des_num ] = 0x4ba; break; 1330 default: eng->dat.FRAME_LEN[ des_num ] = 0x5ea; break; 1331 } 1332 else 1333 // eng->dat.FRAME_LEN[ des_num ] = ( rand() + RAND_SIZE_MIN ) % ( RAND_SIZE_MAX + 1 ); 1334 eng->dat.FRAME_LEN[ des_num ] = RAND_SIZE_MIN + ( rand() % ( RAND_SIZE_MAX - RAND_SIZE_MIN + 1 ) ); 1335 1336 if ( DbgPrn_FRAME_LEN ) 1337 PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1338 } 1339 } 1340 else { 1341 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1342 #ifdef SelectSimpleLength 1343 if ( des_num % FRAME_SELH_PERD ) 1344 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH; 1345 else 1346 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL; 1347 #else 1348 if ( eng->run.tm_tx_only ) { 1349 if ( eng->run.TM_IEEE ) 1350 eng->dat.FRAME_LEN[ des_num ] = 1514; 1351 else 1352 eng->dat.FRAME_LEN[ des_num ] = 60; 1353 } 1354 else { 1355 #ifdef SelectLengthInc 1356 eng->dat.FRAME_LEN[ des_num ] = 1514 - ( des_num % 1455 ); 1357 #else 1358 if ( des_num % FRAME_SELH_PERD ) 1359 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH; 1360 else 1361 eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL; 1362 #endif 1363 } // End if ( eng->run.tm_tx_only ) 1364 #endif 1365 if ( DbgPrn_FRAME_LEN ) 1366 PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1367 1368 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1369 } // End if ( ENABLE_RAND_SIZE ) 1370 1371 // Calculate average of frame size 1372 #ifdef Enable_ShowBW 1373 eng->dat.Total_frame_len = 0; 1374 1375 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) 1376 eng->dat.Total_frame_len += eng->dat.FRAME_LEN[ des_num ]; 1377 #endif 1378 1379 //------------------------------ 1380 // Write Plane 1381 //------------------------------ 1382 switch( ZeroCopy_OFFSET & 0x3 ) { 1383 case 0: eng->dat.wp_fir = 0xffffffff; break; 1384 case 1: eng->dat.wp_fir = 0xffffff00; break; 1385 case 2: eng->dat.wp_fir = 0xffff0000; break; 1386 case 3: eng->dat.wp_fir = 0xff000000; break; 1387 } 1388 1389 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) 1390 switch( ( ZeroCopy_OFFSET + eng->dat.FRAME_LEN[ des_num ] - 1 ) & 0x3 ) { 1391 case 0: eng->dat.wp_lst[ des_num ] = 0x000000ff; break; 1392 case 1: eng->dat.wp_lst[ des_num ] = 0x0000ffff; break; 1393 case 2: eng->dat.wp_lst[ des_num ] = 0x00ffffff; break; 1394 case 3: eng->dat.wp_lst[ des_num ] = 0xffffffff; break; 1395 } 1396 } // End void setup_framesize (void) 1397 1398 //------------------------------------------------------------ 1399 void setup_arp(MAC_ENGINE *eng) 1400 { 1401 1402 nt_log_func_name(); 1403 1404 memcpy(eng->dat.ARP_data, ARP_org_data, sizeof(ARP_org_data)); 1405 1406 eng->dat.ARP_data[1] &= ~GENMASK(31, 16); 1407 eng->dat.ARP_data[1] |= (eng->inf.SA[1] << 24) | (eng->inf.SA[0] << 16); 1408 eng->dat.ARP_data[2] = (eng->inf.SA[5] << 24) | (eng->inf.SA[4] << 16) | 1409 (eng->inf.SA[3] << 8) | (eng->inf.SA[2]); 1410 eng->dat.ARP_data[5] &= ~GENMASK(31, 16); 1411 eng->dat.ARP_data[5] |= (eng->inf.SA[1] << 24) | (eng->inf.SA[0] << 16); 1412 eng->dat.ARP_data[6] = (eng->inf.SA[5] << 24) | (eng->inf.SA[4] << 16) | 1413 (eng->inf.SA[3] << 8) | (eng->inf.SA[2]); 1414 } 1415 1416 //------------------------------------------------------------ 1417 void setup_buf (MAC_ENGINE *eng) 1418 { 1419 int32_t des_num_max; 1420 int32_t des_num; 1421 int i; 1422 uint32_t adr; 1423 uint32_t adr_srt; 1424 uint32_t adr_end; 1425 uint32_t Current_framelen; 1426 uint32_t gdata = 0; 1427 #ifdef SelectSimpleDA 1428 int cnt; 1429 uint32_t len; 1430 #endif 1431 1432 nt_log_func_name(); 1433 1434 // It need be multiple of 4 1435 eng->dat.DMA_Base_Setup = DMA_BASE & 0xfffffffc; 1436 adr_srt = eng->dat.DMA_Base_Setup; 1437 1438 if (eng->run.tm_tx_only) { 1439 if (eng->run.TM_IEEE) { 1440 for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) { 1441 if ( DbgPrn_BufAdr ) 1442 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1443 Write_Mem_Dat_DD(adr_srt, 0xffffffff); 1444 Write_Mem_Dat_DD(adr_srt + 4, 1445 eng->dat.ARP_data[1]); 1446 Write_Mem_Dat_DD(adr_srt + 8, 1447 eng->dat.ARP_data[2]); 1448 1449 for (adr = (adr_srt + 12); 1450 adr < (adr_srt + DMA_PakSize); adr += 4) { 1451 switch (eng->arg.test_mode) { 1452 case 4: 1453 gdata = rand() | (rand() << 16); 1454 break; 1455 case 5: 1456 gdata = eng->arg.user_def_val; 1457 break; 1458 } 1459 Write_Mem_Dat_DD(adr, gdata); 1460 } 1461 adr_srt += DMA_PakSize; 1462 } 1463 } else { 1464 printf("----->[ARP] 60 bytes\n"); 1465 for (i = 0; i < 16; i++) 1466 printf(" [Tx%02d] %08x %08x\n", i, eng->dat.ARP_data[i], SWAP_4B( eng->dat.ARP_data[i] ) ); 1467 1468 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1469 if ( DbgPrn_BufAdr ) 1470 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1471 1472 for (i = 0; i < 16; i++) 1473 Write_Mem_Dat_DD( adr_srt + ( i << 2 ), eng->dat.ARP_data[i] ); 1474 1475 1476 adr_srt += DMA_PakSize; 1477 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1478 } // End if ( eng->run.TM_IEEE ) 1479 } else { 1480 if ( eng->arg.ctrl.b.single_packet ) 1481 des_num_max = 1; 1482 else 1483 des_num_max = eng->dat.Des_Num; 1484 1485 for (des_num = 0; des_num < des_num_max; des_num++) { 1486 if (DbgPrn_BufAdr) 1487 printf("[loop[%d]:%4d][des:%4d][setup_buf ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt); 1488 #ifdef SelectSimpleData 1489 #ifdef SimpleData_Fix 1490 switch( des_num % SimpleData_FixNum ) { 1491 case 0 : gdata = SimpleData_FixVal00; break; 1492 case 1 : gdata = SimpleData_FixVal01; break; 1493 case 2 : gdata = SimpleData_FixVal02; break; 1494 case 3 : gdata = SimpleData_FixVal03; break; 1495 case 4 : gdata = SimpleData_FixVal04; break; 1496 case 5 : gdata = SimpleData_FixVal05; break; 1497 case 6 : gdata = SimpleData_FixVal06; break; 1498 case 7 : gdata = SimpleData_FixVal07; break; 1499 case 8 : gdata = SimpleData_FixVal08; break; 1500 case 9 : gdata = SimpleData_FixVal09; break; 1501 case 10 : gdata = SimpleData_FixVal10; break; 1502 default : gdata = SimpleData_FixVal11; break; 1503 } 1504 #else 1505 gdata = 0x11111111 * ((des_num + SEED_START) % 256); 1506 #endif 1507 #else 1508 gdata = DATA_SEED( des_num + SEED_START ); 1509 #endif 1510 Current_framelen = eng->dat.FRAME_LEN[ des_num ]; 1511 1512 if ( DbgPrn_FRAME_LEN ) 1513 PRINTF( FP_LOG, "[setup_buf ] Current_framelen:%08x[Des:%d][loop[%d]:%d]\n", Current_framelen, des_num, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1514 #ifdef SelectSimpleDA 1515 cnt = 0; 1516 len = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) | 1517 ( ( Current_framelen - 14 ) >> 8 ); 1518 #endif 1519 adr_end = adr_srt + DMA_PakSize; 1520 for ( adr = adr_srt; adr < adr_end; adr += 4 ) { 1521 #ifdef SelectSimpleDA 1522 cnt++; 1523 if ( cnt == 1 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat0 ); 1524 else if ( cnt == 2 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat1 ); 1525 else if ( cnt == 3 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat2 ); 1526 else if ( cnt == 4 ) Write_Mem_Dat_DD( adr, len | (len << 16) ); 1527 else 1528 #endif 1529 Write_Mem_Dat_DD( adr, gdata ); 1530 #ifdef SelectSimpleData 1531 gdata = gdata ^ SimpleData_XORVal; 1532 #else 1533 gdata += DATA_IncVal; 1534 #endif 1535 } 1536 adr_srt += DMA_PakSize; 1537 } // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) 1538 } // End if ( eng->run.tm_tx_only ) 1539 } // End void setup_buf (MAC_ENGINE *eng) 1540 1541 //------------------------------------------------------------ 1542 // Check data of one packet 1543 //------------------------------------------------------------ 1544 char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number) 1545 { 1546 int32_t number_dat; 1547 int index; 1548 uint32_t rdata; 1549 uint32_t wp_lst_cur; 1550 uint32_t adr_las; 1551 uint32_t adr; 1552 uint32_t adr_srt; 1553 uint32_t adr_end; 1554 #ifdef SelectSimpleDA 1555 int cnt; 1556 uint32_t len; 1557 uint32_t gdata_bak; 1558 #endif 1559 uint32_t gdata; 1560 1561 uint32_t wp; 1562 1563 nt_log_func_name(); 1564 1565 if (eng->arg.ctrl.b.single_packet) 1566 number_dat = 0; 1567 else 1568 number_dat = number; 1569 1570 wp_lst_cur = eng->dat.wp_lst[ number ]; 1571 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[ number_dat ]; 1572 1573 if ( DbgPrn_FRAME_LEN ) 1574 PRINTF( FP_LOG, "[check_Data ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN_Cur, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1575 1576 adr_srt = datbase; 1577 adr_end = adr_srt + PktByteSize; 1578 1579 #if defined(SelectSimpleData) 1580 #ifdef SimpleData_Fix 1581 switch( number_dat % SimpleData_FixNum ) { 1582 case 0 : gdata = SimpleData_FixVal00; break; 1583 case 1 : gdata = SimpleData_FixVal01; break; 1584 case 2 : gdata = SimpleData_FixVal02; break; 1585 case 3 : gdata = SimpleData_FixVal03; break; 1586 case 4 : gdata = SimpleData_FixVal04; break; 1587 case 5 : gdata = SimpleData_FixVal05; break; 1588 case 6 : gdata = SimpleData_FixVal06; break; 1589 case 7 : gdata = SimpleData_FixVal07; break; 1590 case 8 : gdata = SimpleData_FixVal08; break; 1591 case 9 : gdata = SimpleData_FixVal09; break; 1592 case 10 : gdata = SimpleData_FixVal10; break; 1593 default : gdata = SimpleData_FixVal11; break; 1594 } 1595 #else 1596 gdata = 0x11111111 * (( number_dat + SEED_START ) % 256 ); 1597 #endif 1598 #else 1599 gdata = DATA_SEED( number_dat + SEED_START ); 1600 #endif 1601 1602 //printf("check_buf: %08x - %08x [%08x]\n", adr_srt, adr_end, datbase); 1603 wp = eng->dat.wp_fir; 1604 adr_las = adr_end - 4; 1605 #ifdef SelectSimpleDA 1606 cnt = 0; 1607 len = ((( eng->dat.FRAME_LEN_Cur-14 ) & 0xff ) << 8 ) | 1608 ( ( eng->dat.FRAME_LEN_Cur-14 ) >> 8 ); 1609 #endif 1610 1611 if ( DbgPrn_Bufdat ) 1612 PRINTF( FP_LOG, " Inf:%08x ~ %08x(%08x) %08x [Des:%d][loop[%d]:%d]\n", adr_srt, adr_end, adr_las, gdata, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1613 1614 for ( adr = adr_srt; adr < adr_end; adr+=4 ) { 1615 #ifdef SelectSimpleDA 1616 cnt++; 1617 if ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; } 1618 else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; } 1619 else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; } 1620 else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16); } 1621 #endif 1622 rdata = Read_Mem_Dat_DD( adr ); 1623 if ( adr == adr_las ) 1624 wp = wp & wp_lst_cur; 1625 1626 if ( ( rdata & wp ) != ( gdata & wp ) ) { 1627 PRINTF( FP_LOG, "\nError: Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1628 for ( index = 0; index < 6; index++ ) 1629 PRINTF( FP_LOG, "Rep : Adr:%08x (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, Read_Mem_Dat_DD( adr ), gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1630 1631 if (DbgPrn_DumpMACCnt) 1632 dump_mac_ROreg(eng); 1633 1634 return( FindErr( eng, Err_Flag_Check_Buf_Data ) ); 1635 } // End if ( (rdata & wp) != (gdata & wp) ) 1636 if ( DbgPrn_BufdatDetail ) 1637 PRINTF( FP_LOG, " Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1638 1639 #ifdef SelectSimpleDA 1640 if ( cnt <= 4 ) 1641 gdata = gdata_bak; 1642 #endif 1643 1644 #if defined(SelectSimpleData) 1645 gdata = gdata ^ SimpleData_XORVal; 1646 #else 1647 gdata += DATA_IncVal; 1648 #endif 1649 1650 wp = 0xffffffff; 1651 } 1652 return(0); 1653 } // End char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number) 1654 1655 //------------------------------------------------------------ 1656 char check_buf (MAC_ENGINE *eng, int loopcnt) 1657 { 1658 int32_t des_num; 1659 uint32_t desadr; 1660 #ifdef CHECK_RX_DATA 1661 uint32_t datbase; 1662 #endif 1663 nt_log_func_name(); 1664 1665 desadr = eng->run.rdes_base + (16 * eng->dat.Des_Num) - 4; 1666 for (des_num = eng->dat.Des_Num - 1; des_num >= 0; des_num--) { 1667 #ifdef CHECK_RX_DATA 1668 datbase = AT_BUF_MEMRW(Read_Mem_Des_DD(desadr) & 0xfffffffc); 1669 if (check_Data(eng, datbase, des_num)) { 1670 check_int(eng, ""); 1671 return (1); 1672 } 1673 if (check_int(eng, "")) 1674 return 1; 1675 #endif 1676 desadr -= 16; 1677 } 1678 if (check_int(eng, "")) 1679 return (1); 1680 1681 #if defined(Delay_CheckData_LoopNum) && defined(Delay_CheckData) 1682 if ((loopcnt % Delay_CheckData_LoopNum) == 0) 1683 DELAY(Delay_CheckData); 1684 #endif 1685 return (0); 1686 } // End char check_buf (MAC_ENGINE *eng, int loopcnt) 1687 1688 //------------------------------------------------------------ 1689 // Descriptor 1690 //------------------------------------------------------------ 1691 void setup_txdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase) 1692 { 1693 uint32_t bufadr; 1694 uint32_t bufadrgap; 1695 uint32_t desval = 0; 1696 int32_t des_num; 1697 1698 nt_log_func_name(); 1699 1700 bufadr = bufbase; 1701 if (eng->arg.ctrl.b.single_packet) 1702 bufadrgap = 0; 1703 else 1704 bufadrgap = DMA_PakSize; 1705 1706 if (eng->run.TM_TxDataEn) { 1707 for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) { 1708 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1709 desval = TDES_IniVal; 1710 Write_Mem_Des_DD(desadr + 0x04, 0); 1711 Write_Mem_Des_DD(desadr + 0x08, 0); 1712 Write_Mem_Des_DD(desadr + 0x0C, bufadr); 1713 Write_Mem_Des_DD(desadr, desval); 1714 1715 if (DbgPrn_FRAME_LEN) 1716 PRINTF( 1717 FP_LOG, 1718 "[setup_txdes ] " 1719 "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", 1720 eng->dat.FRAME_LEN_Cur, des_num, 1721 eng->run.loop_of_cnt, eng->run.loop_cnt); 1722 1723 if (DbgPrn_BufAdr) 1724 printf("[loop[%d]:%4d][des:%4d][setup_txdes] " 1725 "%08x [%08x]\n", 1726 eng->run.loop_of_cnt, eng->run.loop_cnt, 1727 des_num, desadr, bufadr); 1728 1729 desadr += 16; 1730 bufadr += bufadrgap; 1731 } 1732 barrier(); 1733 Write_Mem_Des_DD(desadr - 0x10, desval | EOR_IniVal); 1734 } else { 1735 Write_Mem_Des_DD(desadr, 0); 1736 } 1737 } 1738 1739 //------------------------------------------------------------ 1740 void setup_rxdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase) 1741 { 1742 uint32_t bufadr; 1743 uint32_t desval; 1744 int32_t des_num; 1745 1746 nt_log_func_name(); 1747 1748 bufadr = bufbase; 1749 desval = RDES_IniVal; 1750 if ( eng->run.TM_RxDataEn ) { 1751 for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) { 1752 Write_Mem_Des_DD(desadr + 0x04, 0 ); 1753 Write_Mem_Des_DD(desadr + 0x08, 0 ); 1754 Write_Mem_Des_DD(desadr + 0x0C, bufadr); 1755 Write_Mem_Des_DD(desadr + 0x00, desval); 1756 1757 if ( DbgPrn_BufAdr ) 1758 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x [%08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, desadr, bufadr); 1759 1760 desadr += 16; 1761 bufadr += DMA_PakSize; 1762 } 1763 barrier(); 1764 Write_Mem_Des_DD( desadr - 0x10, desval | EOR_IniVal ); 1765 } 1766 else { 1767 Write_Mem_Des_DD( desadr, 0x80000000 ); 1768 } // End if ( eng->run.TM_RxDataEn ) 1769 } // End void setup_rxdes (uint32_t desadr, uint32_t bufbase) 1770 1771 //------------------------------------------------------------ 1772 // First setting TX and RX information 1773 //------------------------------------------------------------ 1774 void setup_des (MAC_ENGINE *eng, uint32_t bufnum) 1775 { 1776 if (DbgPrn_BufAdr) { 1777 printf("setup_des: %d\n", bufnum); 1778 debug_pause(); 1779 } 1780 1781 eng->dat.DMA_Base_Tx = 1782 ZeroCopy_OFFSET + eng->dat.DMA_Base_Setup; 1783 eng->dat.DMA_Base_Rx = ZeroCopy_OFFSET + GET_DMA_BASE(eng, 0); 1784 1785 setup_txdes(eng, eng->run.tdes_base, 1786 AT_MEMRW_BUF(eng->dat.DMA_Base_Tx)); 1787 setup_rxdes(eng, eng->run.rdes_base, 1788 AT_MEMRW_BUF(eng->dat.DMA_Base_Rx)); 1789 } // End void setup_des (uint32_t bufnum) 1790 1791 //------------------------------------------------------------ 1792 // Move buffer point of TX and RX descriptor to next DMA buffer 1793 //------------------------------------------------------------ 1794 void setup_des_loop (MAC_ENGINE *eng, uint32_t bufnum) 1795 { 1796 int32_t des_num; 1797 uint32_t H_rx_desadr; 1798 uint32_t H_tx_desadr; 1799 uint32_t H_tx_bufadr; 1800 uint32_t H_rx_bufadr; 1801 1802 nt_log_func_name(); 1803 1804 if (eng->run.TM_RxDataEn) { 1805 H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx); 1806 H_rx_desadr = eng->run.rdes_base; 1807 for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) { 1808 Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr); 1809 Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal); 1810 if (DbgPrn_BufAdr) 1811 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] " 1812 "%08x [%08x]\n", 1813 eng->run.loop_of_cnt, eng->run.loop_cnt, 1814 des_num, H_rx_desadr, H_rx_bufadr); 1815 1816 H_rx_bufadr += DMA_PakSize; 1817 H_rx_desadr += 16; 1818 } 1819 Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr); 1820 Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal | EOR_IniVal); 1821 if (DbgPrn_BufAdr) 1822 printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x " 1823 "[%08x]\n", 1824 eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, 1825 H_rx_desadr, H_rx_bufadr); 1826 } 1827 1828 if (eng->run.TM_TxDataEn) { 1829 H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx); 1830 H_tx_desadr = eng->run.tdes_base; 1831 for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) { 1832 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1833 Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr); 1834 Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal); 1835 if (DbgPrn_BufAdr) 1836 printf("[loop[%d]:%4d][des:%4d][setup_txdes] " 1837 "%08x [%08x]\n", 1838 eng->run.loop_of_cnt, eng->run.loop_cnt, 1839 des_num, H_tx_desadr, H_tx_bufadr); 1840 1841 H_tx_bufadr += DMA_PakSize; 1842 H_tx_desadr += 16; 1843 } 1844 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num]; 1845 Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr); 1846 Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal | EOR_IniVal); 1847 if (DbgPrn_BufAdr) 1848 printf("[loop[%d]:%4d][des:%4d][setup_txdes] %08x " 1849 "[%08x]\n", 1850 eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, 1851 H_tx_desadr, H_tx_bufadr); 1852 } 1853 } // End void setup_des_loop (uint32_t bufnum) 1854 1855 //------------------------------------------------------------ 1856 char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1857 { 1858 int timeout = 0; 1859 1860 eng->dat.TxDes0DW = Read_Mem_Des_DD(adr); 1861 1862 while (HWOwnTx(eng->dat.TxDes0DW)) { 1863 // we will run again, if transfer has not been completed. 1864 if ((eng->run.tm_tx_only || eng->run.TM_RxDataEn) && 1865 (++timeout > eng->run.timeout_th)) { 1866 PRINTF(FP_LOG, 1867 "[%sTxDesOwn] Address %08x = %08x " 1868 "[Des:%d][loop[%d]:%d]\n", 1869 type, adr, eng->dat.TxDes0DW, desnum, 1870 eng->run.loop_of_cnt, eng->run.loop_cnt); 1871 return (FindErr_Des(eng, Des_Flag_TxOwnTimeOut)); 1872 } 1873 1874 #ifdef Delay_ChkTxOwn 1875 DELAY(Delay_ChkTxOwn); 1876 #endif 1877 eng->dat.TxDes0DW = Read_Mem_Des_DD(adr); 1878 } 1879 1880 return(0); 1881 } // End char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1882 1883 //------------------------------------------------------------ 1884 char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1885 { 1886 #ifdef CheckRxOwn 1887 int timeout = 0; 1888 1889 eng->dat.RxDes0DW = Read_Mem_Des_DD(adr); 1890 1891 while (HWOwnRx(eng->dat.RxDes0DW)) { 1892 // we will run again, if transfer has not been completed. 1893 if (eng->run.TM_TxDataEn && (++timeout > eng->run.timeout_th)) { 1894 #if 0 1895 printf("[%sRxDesOwn] Address %08x = %08x " 1896 "[Des:%d][loop[%d]:%d]\n", 1897 type, adr, eng->dat.RxDes0DW, desnum, 1898 eng->run.loop_of_cnt, eng->run.loop_cnt); 1899 #endif 1900 FindErr_Des(eng, Des_Flag_RxOwnTimeOut); 1901 return (2); 1902 } 1903 1904 #ifdef Delay_ChkRxOwn 1905 DELAY(Delay_ChkRxOwn); 1906 #endif 1907 eng->dat.RxDes0DW = Read_Mem_Des_DD(adr); 1908 }; 1909 1910 #ifdef CheckRxLen 1911 if ( DbgPrn_FRAME_LEN ) 1912 PRINTF( FP_LOG, "[%sRxDes ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", type, ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1913 1914 if ( ( eng->dat.RxDes0DW & 0x3fff ) != ( eng->dat.FRAME_LEN_Cur + 4 ) ) { 1915 eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 ); 1916 PRINTF( FP_LOG, "[%sRxDes] Error Frame Length %08x:%08x %08x(%4d/%4d) [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, ( eng->dat.RxDes0DW & 0x3fff ), ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1917 FindErr_Des( eng, Des_Flag_FrameLen ); 1918 } 1919 #endif // End CheckRxLen 1920 1921 if ( eng->dat.RxDes0DW & RXDES_EM_ALL ) { 1922 eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 ); 1923 #ifdef CheckRxErr 1924 if ( eng->dat.RxDes0DW & RXDES_EM_RXERR ) { 1925 PRINTF( FP_LOG, "[%sRxDes] Error RxErr %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1926 FindErr_Des( eng, Des_Flag_RxErr ); 1927 } 1928 #endif // End CheckRxErr 1929 1930 #ifdef CheckCRC 1931 if ( eng->dat.RxDes0DW & RXDES_EM_CRC ) { 1932 PRINTF( FP_LOG, "[%sRxDes] Error CRC %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1933 FindErr_Des( eng, Des_Flag_CRC ); 1934 } 1935 #endif // End CheckCRC 1936 1937 #ifdef CheckFTL 1938 if ( eng->dat.RxDes0DW & RXDES_EM_FTL ) { 1939 PRINTF( FP_LOG, "[%sRxDes] Error FTL %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1940 FindErr_Des( eng, Des_Flag_FTL ); 1941 } 1942 #endif // End CheckFTL 1943 1944 #ifdef CheckRunt 1945 if ( eng->dat.RxDes0DW & RXDES_EM_RUNT) { 1946 PRINTF( FP_LOG, "[%sRxDes] Error Runt %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1947 FindErr_Des( eng, Des_Flag_Runt ); 1948 } 1949 #endif // End CheckRunt 1950 1951 #ifdef CheckOddNibble 1952 if ( eng->dat.RxDes0DW & RXDES_EM_ODD_NB ) { 1953 PRINTF( FP_LOG, "[%sRxDes] Odd Nibble %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1954 FindErr_Des( eng, Des_Flag_OddNibble ); 1955 } 1956 #endif // End CheckOddNibble 1957 1958 #ifdef CheckRxFIFOFull 1959 if ( eng->dat.RxDes0DW & RXDES_EM_FIFO_FULL ) { 1960 PRINTF( FP_LOG, "[%sRxDes] Error Rx FIFO Full %08x:%08x %08x [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt ); 1961 FindErr_Des( eng, Des_Flag_RxFIFOFull ); 1962 } 1963 #endif // End CheckRxFIFOFull 1964 } 1965 1966 #endif // End CheckRxOwn 1967 1968 if ( eng->flg.error ) 1969 return(1); 1970 else 1971 return(0); 1972 } // End char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum) 1973 1974 //------------------------------------------------------------ 1975 char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint) 1976 { 1977 int32_t desnum; 1978 int8_t desnum_last; 1979 uint32_t H_rx_desadr; 1980 uint32_t H_tx_desadr; 1981 uint32_t H_tx_bufadr; 1982 uint32_t H_rx_bufadr; 1983 #ifdef Delay_DesGap 1984 uint32_t dly_cnt = 0; 1985 uint32_t dly_max = Delay_CntMaxIncVal; 1986 #endif 1987 int ret; 1988 1989 nt_log_func_name(); 1990 1991 /* Fire the engine to send and recvice */ 1992 mac_reg_write(eng, 0x1c, 0x00000001); // Rx Poll 1993 mac_reg_write(eng, 0x18, 0x00000001); // Tx Poll 1994 1995 #ifndef SelectSimpleDes 1996 /* base of the descriptors */ 1997 H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx); 1998 H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx); 1999 #endif 2000 H_rx_desadr = eng->run.rdes_base; 2001 H_tx_desadr = eng->run.tdes_base; 2002 2003 #ifdef Delay_DES 2004 DELAY(Delay_DES); 2005 #endif 2006 2007 for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) { 2008 desnum_last = (desnum == (eng->dat.Des_Num - 1)) ? 1 : 0; 2009 if ( DbgPrn_BufAdr ) { 2010 if ( checkpoint ) 2011 printf("[loop[%d]:%4d][des:%4d][check_des ] %08x %08x [%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ) ); 2012 else 2013 printf("[loop[%d]:%4d][des:%4d][check_des ] %08x %08x [%08x %08x]->[%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ), H_tx_bufadr, H_rx_bufadr ); 2014 } 2015 2016 //[Delay]-------------------- 2017 #ifdef Delay_DesGap 2018 // if ( dly_cnt++ > 3 ) { 2019 if ( dly_cnt > Delay_CntMax ) { 2020 // switch ( rand() % 12 ) { 2021 // case 1 : dly_max = 00000; break; 2022 // case 3 : dly_max = 20000; break; 2023 // case 5 : dly_max = 40000; break; 2024 // case 7 : dly_max = 60000; break; 2025 // defaule: dly_max = 70000; break; 2026 // } 2027 // 2028 // dly_max += ( rand() % 4 ) * 14321; 2029 // 2030 // while (dly_cnt < dly_max) { 2031 // dly_cnt++; 2032 // } 2033 DELAY( Delay_DesGap ); 2034 dly_cnt = 0; 2035 } 2036 else { 2037 dly_cnt++; 2038 // timeout = 0; 2039 // while (timeout < 50000) {timeout++;}; 2040 } 2041 #endif // End Delay_DesGap 2042 2043 //[Check Owner Bit]-------------------- 2044 eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[desnum]; 2045 if (DbgPrn_FRAME_LEN) 2046 PRINTF(FP_LOG, 2047 "[check_des ] " 2048 "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]%d\n", 2049 eng->dat.FRAME_LEN_Cur, desnum, 2050 eng->run.loop_of_cnt, eng->run.loop_cnt, 2051 checkpoint); 2052 2053 // Check the description of Tx and Rx 2054 if (eng->run.TM_TxDataEn) { 2055 ret = check_des_header_Tx(eng, "", H_tx_desadr, desnum); 2056 if (ret) { 2057 eng->flg.n_desc_fail = desnum; 2058 return ret; 2059 } 2060 } 2061 if (eng->run.TM_RxDataEn) { 2062 ret = check_des_header_Rx(eng, "", H_rx_desadr, desnum); 2063 if (ret) { 2064 eng->flg.n_desc_fail = desnum; 2065 return ret; 2066 2067 } 2068 } 2069 2070 #ifndef SelectSimpleDes 2071 if (!checkpoint) { 2072 // Setting buffer address to description of Tx and Rx on next stage 2073 if ( eng->run.TM_RxDataEn ) { 2074 Write_Mem_Des_DD( H_rx_desadr + 0x0C, H_rx_bufadr ); 2075 if ( desnum_last ) 2076 Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal ); 2077 else 2078 Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal ); 2079 2080 readl(H_rx_desadr); 2081 mac_reg_write(eng, 0x1c, 0x00000000); //Rx Poll 2082 H_rx_bufadr += DMA_PakSize; 2083 } 2084 if ( eng->run.TM_TxDataEn ) { 2085 Write_Mem_Des_DD( H_tx_desadr + 0x0C, H_tx_bufadr ); 2086 if ( desnum_last ) 2087 Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal ); 2088 else 2089 Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal ); 2090 2091 readl(H_tx_desadr); 2092 mac_reg_write(eng, 0x18, 0x00000000); //Tx Poll 2093 H_tx_bufadr += DMA_PakSize; 2094 } 2095 } 2096 #endif // End SelectSimpleDes 2097 2098 H_rx_desadr += 16; 2099 H_tx_desadr += 16; 2100 } // End for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) 2101 2102 return(0); 2103 } // End char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint) 2104 //#endif 2105 2106 //------------------------------------------------------------ 2107 // Print 2108 //----------------------------------------------------------- 2109 void PrintIO_Header (MAC_ENGINE *eng, uint8_t option) 2110 { 2111 int32_t rx_d, step, tmp; 2112 2113 if (eng->run.TM_IOStrength) { 2114 if (eng->io.drv_upper_bond > 1) { 2115 #ifdef CONFIG_ASPEED_AST2600 2116 PRINTF(option, "<IO Strength register: [%08x] 0x%08x>", 2117 eng->io.mac34_drv_reg.addr, 2118 eng->io.mac34_drv_reg.value.w); 2119 #else 2120 PRINTF(option, "<IO Strength register: [%08x] 0x%08x>", 2121 eng->io.mac12_drv_reg.addr, 2122 eng->io.mac12_drv_reg.value.w); 2123 #endif 2124 } 2125 } 2126 2127 if ( eng->run.speed_sel[ 0 ] ) { PRINTF( option, "\n[1G ]========================================>\n" ); } 2128 else if ( eng->run.speed_sel[ 1 ] ) { PRINTF( option, "\n[100M]========================================>\n" ); } 2129 else { PRINTF( option, "\n[10M ]========================================>\n" ); } 2130 2131 if ( !(option == FP_LOG) ) { 2132 step = eng->io.rx_delay_scan.step; 2133 2134 PRINTF(option, "\n "); 2135 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2136 2137 if (rx_d < 0) { 2138 PRINTF(option, "-" ); 2139 } else { 2140 PRINTF(option, "+" ); 2141 } 2142 } 2143 2144 PRINTF(option, "\n "); 2145 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2146 tmp = (abs(rx_d) >> 4) & 0xf; 2147 if (tmp == 0) { 2148 PRINTF(option, "0" ); 2149 } else { 2150 PRINTF(option, "%1x", tmp); 2151 } 2152 } 2153 2154 PRINTF(option, "\n "); 2155 for (rx_d = eng->io.rx_delay_scan.begin; 2156 rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2157 PRINTF(option, "%1x", (uint32_t)abs(rx_d) & 0xf); 2158 } 2159 2160 PRINTF(option, "\n "); 2161 for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) { 2162 if (eng->io.rx_delay_scan.orig == rx_d) { 2163 PRINTF(option, "|" ); 2164 } else { 2165 PRINTF(option, " " ); 2166 } 2167 } 2168 PRINTF( option, "\n"); 2169 } 2170 } 2171 2172 //------------------------------------------------------------ 2173 void PrintIO_LineS(MAC_ENGINE *p_eng, uint8_t option) 2174 { 2175 if (p_eng->io.tx_delay_scan.orig == p_eng->io.Dly_out_selval) { 2176 PRINTF( option, "%02x:-", p_eng->io.Dly_out_selval); 2177 } else { 2178 PRINTF( option, "%02x: ", p_eng->io.Dly_out_selval); 2179 } 2180 } // End void PrintIO_LineS (MAC_ENGINE *eng, uint8_t option) 2181 2182 //------------------------------------------------------------ 2183 void PrintIO_Line(MAC_ENGINE *p_eng, uint8_t option) 2184 { 2185 if ((p_eng->io.Dly_in_selval == p_eng->io.rx_delay_scan.orig) && 2186 (p_eng->io.Dly_out_selval == p_eng->io.tx_delay_scan.orig)) { 2187 if (1 == p_eng->io.result) { 2188 PRINTF(option, "X"); 2189 } else if (2 == p_eng->io.result) { 2190 PRINTF(option, "*"); 2191 } else { 2192 PRINTF(option, "O"); 2193 } 2194 } else { 2195 if (1 == p_eng->io.result) { 2196 PRINTF(option, "x"); 2197 } else if (2 == p_eng->io.result) { 2198 PRINTF(option, "."); 2199 } else { 2200 PRINTF(option, "o"); 2201 } 2202 } 2203 } 2204 2205 //------------------------------------------------------------ 2206 // main 2207 //------------------------------------------------------------ 2208 2209 //------------------------------------------------------------ 2210 void TestingSetup (MAC_ENGINE *eng) 2211 { 2212 nt_log_func_name(); 2213 2214 //[Setup]-------------------- 2215 setup_framesize( eng ); 2216 setup_buf( eng ); 2217 } 2218 2219 //------------------------------------------------------------ 2220 // Return 1 ==> fail 2221 // Return 0 ==> PASS 2222 //------------------------------------------------------------ 2223 char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum) 2224 { 2225 char checkprd; 2226 char looplast; 2227 char checken; 2228 int ret; 2229 2230 nt_log_func_name(); 2231 2232 if (DbgPrn_DumpMACCnt) 2233 dump_mac_ROreg(eng); 2234 2235 //[Setup]-------------------- 2236 eng->run.loop_cnt = 0; 2237 checkprd = 0; 2238 checken = 0; 2239 looplast = 0; 2240 2241 2242 setup_des(eng, 0); 2243 2244 if ( eng->run.TM_WaitStart ) { 2245 printf("Press any key to start...\n"); 2246 GET_CAHR(); 2247 } 2248 2249 2250 while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) { 2251 looplast = !eng->arg.loop_inf && ( eng->run.loop_cnt == eng->run.loop_max - 1 ); 2252 2253 #ifdef CheckRxBuf 2254 if (!eng->run.tm_tx_only) 2255 checkprd = ((eng->run.loop_cnt % loop_checknum) == (loop_checknum - 1)); 2256 checken = looplast | checkprd; 2257 #endif 2258 2259 if (DbgPrn_BufAdr) { 2260 printf("for start ======> [%d]%d/%d(%d) looplast:%d " 2261 "checkprd:%d checken:%d\n", 2262 eng->run.loop_of_cnt, eng->run.loop_cnt, 2263 eng->run.loop_max, eng->arg.loop_inf, 2264 looplast, checkprd, checken); 2265 debug_pause(); 2266 } 2267 2268 2269 if (eng->run.TM_RxDataEn) 2270 eng->dat.DMA_Base_Tx = eng->dat.DMA_Base_Rx; 2271 2272 eng->dat.DMA_Base_Rx = 2273 ZeroCopy_OFFSET + GET_DMA_BASE(eng, eng->run.loop_cnt + 1); 2274 //[Check DES]-------------------- 2275 ret = check_des(eng, eng->run.loop_cnt, checken); 2276 if (ret) { 2277 //descriptor error 2278 eng->dat.Des_Num = eng->flg.n_desc_fail + 1; 2279 #ifdef CheckRxBuf 2280 if (checkprd) 2281 check_buf(eng, loop_checknum); 2282 else 2283 check_buf(eng, (eng->run.loop_max % loop_checknum)); 2284 eng->dat.Des_Num = eng->dat.Des_Num_Org; 2285 #endif 2286 2287 if (DbgPrn_DumpMACCnt) 2288 dump_mac_ROreg(eng); 2289 2290 return ret; 2291 } 2292 2293 //[Check Buf]-------------------- 2294 if (eng->run.TM_RxDataEn && checken) { 2295 if (checkprd) { 2296 #ifdef Enable_ShowBW 2297 printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused); 2298 PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused ); 2299 #endif 2300 2301 #ifdef CheckRxBuf 2302 if (check_buf(eng, loop_checknum)) 2303 return(1); 2304 #endif 2305 } else { 2306 #ifdef Enable_ShowBW 2307 printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused); 2308 PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused ); 2309 #endif 2310 2311 #ifdef CheckRxBuf 2312 if (check_buf(eng, (eng->run.loop_max % loop_checknum))) 2313 return(1); 2314 #endif 2315 } // End if ( checkprd ) 2316 2317 #ifndef SelectSimpleDes 2318 if (!looplast) 2319 setup_des_loop(eng, eng->run.loop_cnt); 2320 #endif 2321 2322 #ifdef Enable_ShowBW 2323 timeold = clock(); 2324 #endif 2325 } // End if ( eng->run.TM_RxDataEn && checken ) 2326 2327 #ifdef SelectSimpleDes 2328 if (!looplast) 2329 setup_des_loop(eng, eng->run.loop_cnt); 2330 #endif 2331 2332 if ( eng->arg.loop_inf ) 2333 printf("===============> Loop[%d]: %d \r", eng->run.loop_of_cnt, eng->run.loop_cnt); 2334 else if ( eng->arg.test_mode == 0 ) { 2335 if ( !( DbgPrn_BufAdr || eng->run.delay_margin ) ) 2336 printf(" [%d]%d \r", eng->run.loop_of_cnt, eng->run.loop_cnt); 2337 } 2338 2339 if (DbgPrn_BufAdr) { 2340 printf("for end ======> [%d]%d/%d(%d)\n", 2341 eng->run.loop_of_cnt, eng->run.loop_cnt, 2342 eng->run.loop_max, eng->arg.loop_inf); 2343 debug_pause(); 2344 } 2345 2346 if (eng->run.loop_cnt >= 0x7fffffff) { 2347 debug("loop counter wrapped around\n"); 2348 eng->run.loop_cnt = 0; 2349 eng->run.loop_of_cnt++; 2350 } else 2351 eng->run.loop_cnt++; 2352 } // End while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) 2353 2354 eng->flg.all_fail = 0; 2355 return(0); 2356 } // End char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum) 2357