1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #ifndef COMMINF_H 7 #define COMMINF_H 8 9 #include "swfunc.h" 10 11 #include "mac.h" 12 13 //--------------------------------------------------------- 14 // Print Message 15 //--------------------------------------------------------- 16 // for function 17 #define FP_LOG 0 18 #define FP_IO 1 19 #define STD_OUT 2 20 21 #define PRINTF(i, ...) \ 22 do { \ 23 if (i == STD_OUT) { \ 24 fprintf(stdout, __VA_ARGS__); \ 25 break; \ 26 } \ 27 if ((display_lantest_log_msg != 0) && (i == FP_LOG)) { \ 28 fprintf(stdout, "[Log]: "); \ 29 fprintf(stdout, __VA_ARGS__); \ 30 } \ 31 } while (0); 32 33 //--------------------------------------------------------- 34 // Function 35 //--------------------------------------------------------- 36 #define SWAP_4B( x ) \ 37 ( ( ( ( x ) & 0xff000000 ) >> 24) \ 38 | ( ( ( x ) & 0x00ff0000 ) >> 8) \ 39 | ( ( ( x ) & 0x0000ff00 ) << 8) \ 40 | ( ( ( x ) & 0x000000ff ) << 24) \ 41 ) 42 #define SWAP_2B( x ) \ 43 ( ( ( ( x ) & 0xff00 ) >> 8) \ 44 | ( ( ( x ) & 0x00ff ) << 8) \ 45 ) 46 47 #define SWAP_2B_BEDN( x ) ( SWAP_2B ( x ) ) 48 #define SWAP_2B_LEDN( x ) ( x ) 49 #define SWAP_4B_BEDN( x ) ( SWAP_4B ( x ) ) 50 #define SWAP_4B_LEDN( x ) ( x ) 51 52 #define SWAP_4B_BEDN_NCSI( x ) ( SWAP_4B( x ) ) 53 #define SWAP_4B_LEDN_NCSI( x ) ( x ) 54 55 #if defined(ENABLE_BIG_ENDIAN_MEM) 56 #define SWAP_4B_LEDN_MEM( x ) ( SWAP_4B( x ) ) 57 #else 58 #define SWAP_4B_LEDN_MEM( x ) ( x ) 59 #endif 60 #if defined(ENABLE_BIG_ENDIAN_REG) 61 #define SWAP_4B_LEDN_REG( x ) ( SWAP_4B( x ) ) 62 #else 63 #define SWAP_4B_LEDN_REG( x ) ( x ) 64 #endif 65 66 #define DELAY( x ) udelay( ( x ) * 1000 ) 67 #define GET_CAHR getc 68 69 //--------------------------------------------------------- 70 // Default argument 71 //--------------------------------------------------------- 72 #define DEF_GUSER_DEF_PACKET_VAL 0xaaaaaaaa //0xff00ff00, 0xf0f0f0f0, 0xcccccccc, 0x55aa55aa, 0x5a5a5a5a, 0x66666666 73 #define DEF_GIOTIMINGBUND 2 74 #define DEF_GPHY_ADR 0 75 #define DEF_GTESTMODE 0 //[0]0: no burst mode, 1: 0xff, 2: 0x55, 3: random, 4: ARP, 5: ARP, 6: IO timing, 7: IO timing+IO Strength 76 #define DEF_GLOOP_MAX 1 77 #define DEF_GCTRL 0 78 79 #define SET_1GBPS BIT(0) 80 #define SET_100MBPS BIT(1) 81 #define SET_10MBPS BIT(2) 82 #define SET_1G_100M_10MBPS (SET_1GBPS | SET_100MBPS | SET_10MBPS) 83 #define SET_100M_10MBPS (SET_100MBPS | SET_10MBPS) 84 85 #define DEF_GSPEED SET_1G_100M_10MBPS 86 #define DEF_GARPNUMCNT 0 87 88 /* MAC information */ 89 90 /* old interface - deprecated */ 91 #define MDC_CYC_THLD 0x3f 92 #define MDIO_WR_CODE_OLD BIT(27) 93 #define MDIO_RD_CODE_OLD BIT(26) 94 95 #define MDIO_SET_PHY_ADDR_OLD(addr) ((addr) << 16) 96 #define MDIO_SET_REG_ADDR_OLD(reg) ((reg) << 21) 97 98 #ifdef CONFIG_ASPEED_AST2600 99 #define MDIO_FIRE_BUSY BIT(31) 100 #define MDIO_WR_CODE (MDIO_FIRE_BUSY | BIT(28) | (0x1 << 26)) 101 #define MDIO_RD_CODE (MDIO_FIRE_BUSY | BIT(28) | (0x2 << 26)) 102 #define MDIO_SET_WR_DATA(x) ((x) << 0) 103 #define MDIO_GET_WR_DATA(x) ((x) & GENMASK(15, 0)) 104 #define MDIO_SET_PHY_ADDR(addr) ((addr) << 21) 105 #define MDIO_SET_REG_ADDR(reg) ((reg) << 16) 106 #else 107 #define MDIO_FIRE_BUSY BIT(15) 108 #define MDIO_WR_CODE (MDIO_FIRE_BUSY | BIT(12) | (0x1 << 10)) 109 #define MDIO_RD_CODE (MDIO_FIRE_BUSY | BIT(12) | (0x2 << 10)) 110 #define MDIO_SET_WR_DATA(x) ((x) << 16) 111 #define MDIO_GET_WR_DATA(x) (((x) & GENMASK(31, 16)) >> 16) 112 #define MDIO_SET_PHY_ADDR(addr) ((addr) << 5) 113 #define MDIO_SET_REG_ADDR(reg) ((reg) << 0) 114 #endif 115 116 #define MAC_048_def 0x000002F1 /* default 0xf1 */ 117 118 //--------------------------------------------------------- 119 // Data information 120 //--------------------------------------------------------- 121 #define ZeroCopy_OFFSET (( eng->run.tm_tx_only ) ? 0 : 2) 122 123 // --------------------------------- DRAM_MapAdr = tdes_base 124 // | TX descriptor ring | 125 // ------------------------- DRAM_MapAdr + 0x040000 = rdes_base 126 // | RX descriptor ring | 127 // ------------------------- 128 // | Reserved | 129 // ------------------------- 130 // | Reserved | 131 // --------------------------------- DRAM_MapAdr + 0x100000 = DMA_BASE ------------------------- 132 // | #1 | \ | #1 Tx | 133 // DMA buffer | | DMA_BufSize | LOOP = 0 | 134 // ( Tx/Rx ) ------------------------- / -------------------------------------------------- 135 // | #2 | | #2 Rx | #2 Tx | 136 // | | | LOOP = 0 | LOOP = 1 | 137 // ------------------------- -------------------------------------------------- 138 // | #3 | | #3 Rx | 139 // | | | LOOP = 1 | 140 // ------------------------- ------------------------- 141 // | #4 | .......... 142 // | | 143 // ------------------------- 144 // | #5 | 145 // | | 146 // ------------------------- 147 // | #6 | 148 // | | 149 // ------------------------- 150 // . 151 // . 152 // ------------------------- 153 // | #n, n = DMA_BufNum | 154 // | | 155 // --------------------------------- 156 157 #define BUF_SIZE 0x04000000 158 #define TDES_SIZE 0x00040000 159 #define RDES_SIZE 0x00040000 160 #define RESV_SIZE 0x00000000 /* reserved */ 161 162 #define TDES_IniVal (0xb0000000 + eng->dat.FRAME_LEN_Cur) 163 #define RDES_IniVal (0x00000fff) 164 #define EOR_IniVal (0x40000000) 165 #define HWOwnTx(dat) (dat & 0x80000000) 166 #define HWOwnRx(dat) ((dat & 0x80000000) == 0) 167 #define HWEOR(dat) (dat & 0x40000000) 168 169 #define AT_MEMRW_BUF(x) ((x) - ASPEED_DRAM_BASE) 170 #define AT_BUF_MEMRW(x) ((x) + ASPEED_DRAM_BASE) 171 172 //--------------------------------------------------------- 173 // Error Flag Bits 174 //--------------------------------------------------------- 175 #define Err_Flag_MACMode ( 1 << 0 ) // MAC interface mode mismatch 176 #define Err_Flag_PHY_Type ( 1 << 1 ) // Unidentifiable PHY 177 #define Err_Flag_MALLOC_FrmSize ( 1 << 2 ) // Malloc fail at frame size buffer 178 #define Err_Flag_MALLOC_LastWP ( 1 << 3 ) // Malloc fail at last WP buffer 179 #define Err_Flag_Check_Buf_Data ( 1 << 4 ) // Received data mismatch 180 #define Err_Flag_Check_Des ( 1 << 5 ) // Descriptor error 181 #define ERR_FLAG_NCSI_LINKFAIL (1 << 6) // NCSI packet retry number over flows 182 #define Err_Flag_NCSI_Check_TxOwnTimeOut ( 1 << 7 ) // Time out of checking Tx owner bit in NCSI packet 183 #define Err_Flag_NCSI_Check_RxOwnTimeOut ( 1 << 8 ) // Time out of checking Rx owner bit in NCSI packet 184 #define Err_Flag_NCSI_Check_ARPOwnTimeOut ( 1 << 9 ) // Time out of checking ARP owner bit in NCSI packet 185 #define Err_Flag_NCSI_No_PHY ( 1 << 10 ) // Can not find NCSI PHY 186 #define Err_Flag_NCSI_Channel_Num ( 1 << 11 ) // NCSI Channel Number Mismatch 187 #define Err_Flag_NCSI_Package_Num ( 1 << 12 ) // NCSI Package Number Mismatch 188 #define Err_Flag_PHY_TimeOut_RW ( 1 << 13 ) // Time out of read/write PHY register 189 #define Err_Flag_PHY_TimeOut_Rst ( 1 << 14 ) // Time out of reset PHY register 190 #define Err_Flag_RXBUF_UNAVA ( 1 << 15 ) // MAC00h[2]:Receiving buffer unavailable 191 #define Err_Flag_RPKT_LOST ( 1 << 16 ) // MAC00h[3]:Received packet lost due to RX FIFO full 192 #define Err_Flag_NPTXBUF_UNAVA ( 1 << 17 ) // MAC00h[6]:Normal priority transmit buffer unavailable 193 #define Err_Flag_TPKT_LOST ( 1 << 18 ) // MAC00h[7]:Packets transmitted to Ethernet lost 194 #define Err_Flag_DMABufNum ( 1 << 19 ) // DMA Buffer is not enough 195 #define Err_Flag_IOMargin ( 1 << 20 ) // IO timing margin is not enough 196 #define Err_Flag_IOMarginOUF ( 1 << 21 ) // IO timing testing out of boundary 197 #define Err_Flag_MHCLK_Ratio ( 1 << 22 ) // Error setting of MAC AHB bus clock (SCU08[18:16]) 198 199 #define Wrn_Flag_IOMarginOUF ( 1 << 0 ) // IO timing testing out of boundary 200 #define Wrn_Flag_RxErFloatting ( 1 << 1 ) // NCSI RXER pin may be floatting to the MAC 201 //#define Wrn_Flag_RMIICK_IOMode ( 1 << 2 ) // The PHY's RMII refreence clock input/output mode 202 203 #define PHY_Flag_RMIICK_IOMode_RTL8201E ( 1 << 0 ) 204 #define PHY_Flag_RMIICK_IOMode_RTL8201F ( 1 << 1 ) 205 206 #define Des_Flag_TxOwnTimeOut ( 1 << 0 ) // Time out of checking Tx owner bit 207 #define Des_Flag_RxOwnTimeOut ( 1 << 1 ) // Time out of checking Rx owner bit 208 #define Des_Flag_FrameLen ( 1 << 2 ) // Frame length mismatch 209 #define Des_Flag_RxErr ( 1 << 3 ) // Input signal RxErr 210 #define Des_Flag_CRC ( 1 << 4 ) // CRC error of frame 211 #define Des_Flag_FTL ( 1 << 5 ) // Frame too long 212 #define Des_Flag_Runt ( 1 << 6 ) // Runt packet 213 #define Des_Flag_OddNibble ( 1 << 7 ) // Nibble bit happen 214 #define Des_Flag_RxFIFOFull ( 1 << 8 ) // Rx FIFO full 215 216 #define NCSI_Flag_Get_Version_ID ( 1 << 0 ) // Time out when Get Version ID 217 #define NCSI_Flag_Get_Capabilities ( 1 << 1 ) // Time out when Get Capabilities 218 #define NCSI_Flag_Select_Active_Package ( 1 << 2 ) // Time out when Select Active Package 219 #define NCSI_Flag_Enable_Set_MAC_Address ( 1 << 3 ) // Time out when Enable Set MAC Address 220 #define NCSI_Flag_Enable_Broadcast_Filter ( 1 << 4 ) // Time out when Enable Broadcast Filter 221 #define NCSI_Flag_Enable_Network_TX ( 1 << 5 ) // Time out when Enable Network TX 222 #define NCSI_Flag_Enable_Channel ( 1 << 6 ) // Time out when Enable Channel 223 #define NCSI_Flag_Disable_Network_TX ( 1 << 7 ) // Time out when Disable Network TX 224 #define NCSI_Flag_Disable_Channel ( 1 << 8 ) // Time out when Disable Channel 225 #define NCSI_Flag_Select_Package ( 1 << 9 ) // Time out when Select Package 226 #define NCSI_Flag_Deselect_Package ( 1 << 10 ) // Time out when Deselect Package 227 #define NCSI_Flag_Set_Link ( 1 << 11 ) // Time out when Set Link 228 #define NCSI_Flag_Get_Controller_Packet_Statistics ( 1 << 12 ) // Time out when Get Controller Packet Statistics 229 #define NCSI_Flag_Reset_Channel ( 1 << 13 ) // Time out when Reset Channel 230 231 //--------------------------------------------------------- 232 // DMA Buffer information 233 //--------------------------------------------------------- 234 #define DMA_BUF_SIZE (56 * 1024 * 1024) 235 extern uint8_t dma_buf[DMA_BUF_SIZE]; 236 237 #define DMA_BASE ((uint32_t)(&dma_buf[0])) 238 /* The size of one LAN packet */ 239 #define DMA_PakSize (2 * 1024) 240 241 #ifdef SelectSimpleBoundary 242 #define DMA_BufSize (((((p_eng->dat.Des_Num + 15) * DMA_PakSize) >> 2) << 2)) 243 #else 244 #define DMA_BufSize \ 245 (4 + ((((p_eng->dat.Des_Num + 15) * DMA_PakSize) >> 2) << 2)) 246 #endif 247 #define DMA_BufNum (DMA_BUF_SIZE / (p_eng->dat.DMABuf_Size)) 248 249 /* get DMA buffer address according to the loop counter */ 250 #define GET_DMA_BASE(p_eng, x) \ 251 (DMA_BASE + ((((x) % p_eng->dat.DMABuf_Num)) * p_eng->dat.DMABuf_Size)) 252 253 #define SEED_START 8 254 #define DATA_SEED(seed) ( ( seed ) | (( seed + 1 ) << 16 ) ) 255 #define DATA_IncVal 0x00020001 256 #define PktByteSize ( ( ( ( ZeroCopy_OFFSET + eng->dat.FRAME_LEN_Cur - 1 ) >> 2 ) + 1) << 2 ) 257 258 //--------------------------------------------------------- 259 // Delay (ms) 260 //--------------------------------------------------------- 261 //#define Delay_DesGap 1 //off 262 //#define Delay_CntMax 40 263 //#define Delay_CntMax 1000 264 //#define Delay_CntMax 8465 265 //#define Delay_CntMaxIncVal 50000 266 #define Delay_CntMaxIncVal 47500 267 268 269 //#define Delay_ChkRxOwn 1 270 //#define Delay_ChkTxOwn 1 271 272 #define Delay_PHYRst 100 273 //#define Delay_PHYRd 5 274 #define Delay_PHYRd 1 //20150423 275 276 #define Delay_MACRst 1 277 #define Delay_MACDump 1 278 279 //#define Delay_DES 1 280 281 //--------------------------------------------------------- 282 // Time Out 283 //--------------------------------------------------------- 284 #define TIME_OUT_Des_1G 10000 //400 285 #define TIME_OUT_Des_100M 20000 //4000 286 #define TIME_OUT_Des_10M 50000 //20000 287 #define TIME_OUT_NCSI 100000 //40000 288 #define TIME_OUT_PHY_RW 2000000 //100000 289 #define TIME_OUT_PHY_Rst 20000 //1000 290 291 //--------------------------------------------------------- 292 // Chip memory MAP 293 //--------------------------------------------------------- 294 typedef union { 295 uint32_t w; 296 struct { 297 uint32_t txdma_en : 1; /* bit[0] */ 298 uint32_t rxdma_en : 1; /* bit[1] */ 299 uint32_t txmac_en : 1; /* bit[2] */ 300 uint32_t rxmac_en : 1; /* bit[3] */ 301 uint32_t rm_vlan : 1; /* bit[4] */ 302 uint32_t hptxr_en : 1; /* bit[5] */ 303 uint32_t phy_link_sts_dtct : 1; /* bit[6] */ 304 uint32_t enrx_in_halftx : 1; /* bit[7] */ 305 uint32_t fulldup : 1; /* bit[8] */ 306 uint32_t gmac_mode : 1; /* bit[9] */ 307 uint32_t crc_apd : 1; /* bit[10] */ 308 #ifdef CONFIG_ASPEED_AST2600 309 uint32_t reserved_1 : 1; /* bit[11] */ 310 #else 311 uint32_t phy_link_lvl_dtct : 1; /* bit[11] */ 312 #endif 313 uint32_t rx_runt : 1; /* bit[12] */ 314 uint32_t jumbo_lf : 1; /* bit[13] */ 315 uint32_t rx_alladr : 1; /* bit[14] */ 316 uint32_t rx_ht_en : 1; /* bit[15] */ 317 uint32_t rx_multipkt_en : 1; /* bit[16] */ 318 uint32_t rx_broadpkt_en : 1; /* bit[17] */ 319 uint32_t discard_crcerr : 1; /* bit[18] */ 320 uint32_t speed_100 : 1; /* bit[19] */ 321 uint32_t reserved_0 : 11; /* bit[30:20] */ 322 uint32_t sw_rst : 1; /* bit[31] */ 323 }b; 324 } mac_cr_t; 325 // ======================================================== 326 // For ncsi.c 327 328 #define DEF_GPACKAGE2NUM 1 // Default value 329 #define DEF_GCHANNEL2NUM 1 // Default value 330 331 //--------------------------------------------------------- 332 // Variable 333 //--------------------------------------------------------- 334 //NC-SI Command Packet 335 typedef struct { 336 //Ethernet Header 337 unsigned char DA[6]; // Destination Address 338 unsigned char SA[6]; // Source Address 339 uint16_t EtherType; // DMTF NC-SI, it should be 0x88F8 340 //NC-SI Control Packet 341 unsigned char MC_ID; // Management Controller should set this field to 0x00 342 unsigned char Header_Revision; // For NC-SI 1.0 spec, this field has to set 0x01 343 unsigned char Reserved_1; // Reserved has to set to 0x00 344 unsigned char IID; // Instance ID 345 unsigned char Command; 346 // unsigned char Channel_ID; 347 unsigned char ChID; 348 uint16_t Payload_Length; // Payload Length = 12 bits, 4 bits are reserved 349 uint32_t Reserved_2; 350 uint32_t Reserved_3; 351 352 uint16_t Reserved_4; 353 uint16_t Reserved_5; 354 uint16_t Response_Code; 355 uint16_t Reason_Code; 356 unsigned char Payload_Data[64]; 357 #if !defined(SLT_UBOOT) 358 } NCSI_Command_Packet; 359 #else 360 } __attribute__ ((__packed__)) NCSI_Command_Packet; 361 #endif 362 363 //NC-SI Response Packet 364 typedef struct { 365 unsigned char DA[6]; 366 unsigned char SA[6]; 367 uint16_t EtherType; //DMTF NC-SI 368 //NC-SI Control Packet 369 unsigned char MC_ID; //Management Controller should set this field to 0x00 370 unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01 371 unsigned char Reserved_1; //Reserved has to set to 0x00 372 unsigned char IID; //Instance ID 373 unsigned char Command; 374 // unsigned char Channel_ID; 375 unsigned char ChID; 376 uint16_t Payload_Length; //Payload Length = 12 bits, 4 bits are reserved 377 uint16_t Reserved_2; 378 uint16_t Reserved_3; 379 uint16_t Reserved_4; 380 uint16_t Reserved_5; 381 382 uint16_t Response_Code; 383 uint16_t Reason_Code; 384 unsigned char Payload_Data[64]; 385 #if !defined(SLT_UBOOT) 386 } NCSI_Response_Packet; 387 #else 388 } __attribute__ ((__packed__)) NCSI_Response_Packet; 389 #endif 390 391 typedef struct { 392 unsigned char All_ID ; 393 unsigned char Package_ID ; 394 unsigned char Channel_ID ; 395 uint32_t Capabilities_Flags ; 396 uint32_t Broadcast_Packet_Filter_Capabilities ; 397 uint32_t Multicast_Packet_Filter_Capabilities ; 398 uint32_t Buffering_Capabilities ; 399 uint32_t AEN_Control_Support ; 400 unsigned char VLAN_Filter_Count ; 401 unsigned char Mixed_Filter_Count ; 402 unsigned char Multicast_Filter_Count ; 403 unsigned char Unicast_Filter_Count ; 404 unsigned char VLAN_Mode_Support ; 405 unsigned char Channel_Count ; 406 uint32_t PCI_DID_VID ; 407 uint32_t manufacturer_id ; 408 } NCSI_Capability; 409 410 typedef struct { 411 mac_cr_t maccr; 412 uint32_t mac_madr; 413 uint32_t mac_ladr; 414 uint32_t mac_fear; 415 416 uint32_t WDT_00c ; 417 uint32_t WDT_02c ; 418 uint32_t WDT_04c ; 419 420 int8_t SCU_oldvld; 421 } mac_reg_t; 422 typedef struct { 423 uint8_t ast2600; 424 uint8_t ast2500; 425 uint8_t mac_num; 426 uint8_t is_new_mdio_reg[4]; 427 428 uint8_t is_1g_valid[4]; 429 uint8_t at_least_1g_valid; 430 uint8_t MHCLK_Ratio; 431 } mac_env_t; 432 433 typedef union { 434 uint32_t w; 435 struct { 436 uint32_t skip_phy_init : 1; /* bit[0] */ 437 uint32_t skip_phy_deinit: 1; /* bit[1] */ 438 uint32_t skip_phy_id_check : 1; /* bit[2] */ 439 uint32_t reserved_0 : 1; /* bit[3] */ 440 uint32_t phy_int_loopback : 1; /* bit[4] */ 441 uint32_t mac_int_loopback : 1; /* bit[5] */ 442 uint32_t phy_rx_delay_en: 1; /* bit[6] */ 443 uint32_t phy_tx_delay_en: 1; /* bit[7] */ 444 uint32_t rmii_50m_out : 1; /* bit[8] */ 445 uint32_t rmii_phy_in : 1; /* bit[9] */ 446 uint32_t inv_rgmii_rxclk: 1; /* bit[10] */ 447 uint32_t reserved_2 : 1; /* bit[11] */ 448 uint32_t single_packet : 1; /* bit[12] */ 449 uint32_t full_range : 1; /* bit[13] */ 450 uint32_t reserved_3 : 2; /* bit[15:14] */ 451 uint32_t print_ncsi : 1; /* bit[16] */ 452 uint32_t skip_rx_err : 1; /* bit[17] */ 453 } b; 454 } mac_arg_ctrl_t; 455 typedef struct { 456 uint32_t run_mode; /* select dedicated or NCSI */ 457 uint32_t mac_idx; /* argv[1] */ 458 uint32_t mdio_idx; 459 uint32_t run_speed; /* argv[2] for dedicated */ 460 mac_arg_ctrl_t ctrl; /* argv[3] for dedicated 461 argv[6] for ncsi */ 462 uint32_t loop_max; /* argv[4] for dedicated */ 463 uint32_t loop_inf; /* argv[4] for dedicated */ 464 465 uint32_t GPackageTolNum; /* argv[2] for ncsi */ 466 uint32_t GChannelTolNum; /* argv[3] for ncsi */ 467 468 uint32_t test_mode; /* argv[5] for dedicated 469 argv[4] for ncsi */ 470 471 uint32_t phy_addr; /* argv[6] for dedicated */ 472 uint32_t delay_scan_range; /* argv[7] for dedicated 473 argv[5] for ncsi */ 474 uint32_t ieee_sel; /* argv[7] for dedicated */ 475 476 uint32_t GARPNumCnt; /* argv[7] for ncsi */ 477 uint32_t user_def_val; /* argv[8] for dedicated */ 478 } mac_arg_t; 479 typedef struct { 480 uint32_t mac_idx; 481 uint32_t mac_base; 482 uint32_t mdio_idx; 483 uint32_t mdio_base; 484 uint32_t is_rgmii; 485 uint32_t ieee_sel; /* derived from delay_scan_range */ 486 487 uint32_t tdes_base; 488 uint32_t rdes_base; 489 490 uint32_t ncsi_tdes_base; 491 uint32_t ncsi_rdes_base; 492 493 uint32_t LOOP_CheckNum ; 494 uint32_t CheckBuf_MBSize ; 495 uint32_t timeout_th; /* time out threshold (varies with run-speed) */ 496 497 uint32_t loop_max; 498 uint32_t loop_of_cnt; 499 uint32_t loop_cnt; 500 uint32_t speed_idx; 501 int NCSI_RxTimeOutScale ; 502 503 uint8_t speed_cfg[3]; 504 uint8_t speed_sel[3]; 505 506 /* test mode */ 507 uint8_t delay_margin; 508 uint8_t tm_tx_only; 509 int8_t TM_IEEE ;//test_mode 510 int8_t TM_IOTiming ;//test_mode 511 int8_t TM_IOStrength ;//test_mode 512 int8_t TM_TxDataEn ;//test_mode 513 int8_t TM_RxDataEn ;//test_mode 514 int8_t TM_WaitStart ;//test_mode 515 int8_t TM_DefaultPHY ;//test_mode 516 int8_t TM_NCSI_DiSChannel ;//test_mode 517 518 int8_t IO_MrgChk ; 519 520 521 } MAC_Running; 522 523 typedef struct { 524 uint8_t SA[6]; 525 } MAC_Information; 526 527 typedef struct { 528 uint32_t mdio_base; 529 uint32_t loopback; 530 uint8_t phy_name[64]; 531 int8_t default_phy ; 532 int8_t Adr ; 533 534 uint16_t id2 ; 535 uint16_t id1 ; 536 537 uint32_t PHY_00h ; 538 uint32_t PHY_06h ; 539 uint32_t PHY_09h ; 540 uint32_t PHY_0eh ; 541 uint32_t PHY_10h ; 542 uint32_t PHY_11h ; 543 uint32_t PHY_12h ; 544 uint32_t PHY_14h ; 545 uint32_t PHY_15h ; 546 uint32_t PHY_18h ; 547 uint32_t PHY_19h ; 548 uint32_t PHY_1ch ; 549 uint32_t PHY_1eh ; 550 uint32_t PHY_1fh ; 551 uint32_t PHY_06hA[7] ; 552 553 uint32_t RMIICK_IOMode ; 554 } MAC_PHY; 555 556 #ifdef CONFIG_ASPEED_AST2600 557 typedef union { 558 uint32_t w; 559 struct { 560 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 561 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 562 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 563 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 564 uint32_t rx_clk_inv_1 : 1; /* bit[24] */ 565 uint32_t rx_clk_inv_2 : 1; /* bit[25] */ 566 uint32_t rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 567 uint32_t rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 568 uint32_t rgmiick_pad_dir : 1; /* bit[28] */ 569 uint32_t rmii_50m_oe_1 : 1; /* bit[29] */ 570 uint32_t rmii_50m_oe_2 : 1; /* bit[30] */ 571 uint32_t rgmii_125m_o_sel : 1; /* bit[31] */ 572 }b; 573 } mac_delay_1g_t; 574 575 typedef union { 576 uint32_t w; 577 struct { 578 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 579 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 580 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 581 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 582 uint32_t rx_clk_inv_1 : 1; /* bit[24] */ 583 uint32_t rx_clk_inv_2 : 1; /* bit[25] */ 584 uint32_t reserved_0 : 6; /* bit[31:26] */ 585 }b; 586 } mac_delay_100_10_t; 587 #else 588 typedef union { 589 uint32_t w; 590 struct { 591 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 592 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 593 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 594 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 595 uint32_t rmii_tx_data_at_falling_1 : 1; /* bit[24] */ 596 uint32_t rmii_tx_data_at_falling_2 : 1; /* bit[25] */ 597 uint32_t reserved : 3; /* bit[28:26] */ 598 uint32_t rmii_50m_oe_1 : 1; /* bit[29] */ 599 uint32_t rmii_50m_oe_2 : 1; /* bit[30] */ 600 uint32_t rgmii_125m_o_sel : 1; /* bit[31] */ 601 }b; 602 } mac_delay_1g_t; 603 604 typedef union { 605 uint32_t w; 606 struct { 607 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 608 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 609 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 610 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 611 uint32_t enable : 1; /* bit[24] */ 612 uint32_t reserved_0 : 7; /* bit[31:25] */ 613 }b; 614 } mac_delay_100_10_t; 615 #endif 616 617 typedef struct mac_delay_1g_reg_s { 618 uint32_t addr; 619 int32_t tx_min; 620 int32_t tx_max; 621 int32_t rx_min; 622 int32_t rx_max; 623 int32_t rmii_tx_min; 624 int32_t rmii_tx_max; 625 int32_t rmii_rx_min; 626 int32_t rmii_rx_max; 627 mac_delay_1g_t value; /* backup register value */ 628 } mac_delay_1g_reg_t; 629 630 typedef struct mac_delay_100_10_reg_s { 631 uint32_t addr; 632 int32_t tx_min; 633 int32_t tx_max; 634 int32_t rx_min; 635 int32_t rx_max; 636 mac_delay_100_10_t value; 637 } mac_delay_100_10_reg_t; 638 639 #ifdef CONFIG_ASPEED_AST2600 640 typedef union { 641 uint32_t w; 642 struct { 643 uint32_t mac3_tx_drv : 2; /* bit[1:0] */ 644 uint32_t mac4_tx_drv : 2; /* bit[3:2] */ 645 uint32_t reserved_0 : 28; /* bit[31:4] */ 646 }b; 647 } mac34_drv_t; 648 typedef struct mac34_drv_reg_s { 649 uint32_t addr; 650 uint32_t drv_max; 651 mac34_drv_t value; 652 } mac34_drv_reg_t; 653 654 #else 655 typedef union { 656 uint32_t w; 657 struct { 658 uint32_t reserved_0 : 8; /* bit[7:0] */ 659 uint32_t mac1_rmii_tx_drv : 1; /* bit[8] */ 660 uint32_t mac1_rgmii_tx_drv : 1; /* bit[9] */ 661 uint32_t mac2_rmii_tx_drv : 1; /* bit[10] */ 662 uint32_t mac2_rgmii_tx_drv : 1; /* bit[11] */ 663 uint32_t reserved_1 : 20; /* bit[31:12] */ 664 }b; 665 } mac12_drv_t; 666 667 typedef struct mac12_drv_reg_s { 668 uint32_t addr; 669 uint32_t drv_max; 670 mac12_drv_t value; 671 } mac12_drv_reg_t; 672 #endif 673 674 typedef struct delay_scan_s { 675 int8_t begin; 676 int8_t end; 677 int8_t step; 678 int8_t orig; 679 } delay_scan_t; 680 typedef struct { 681 /* driving strength */ 682 #ifdef CONFIG_ASPEED_AST2600 683 mac34_drv_reg_t mac34_drv_reg; 684 #else 685 mac12_drv_reg_t mac12_drv_reg; 686 #endif 687 uint32_t drv_upper_bond; 688 uint32_t drv_lower_bond; 689 uint32_t drv_curr; 690 691 mac_delay_1g_reg_t mac12_1g_delay; 692 mac_delay_1g_reg_t mac34_1g_delay; 693 mac_delay_100_10_reg_t mac12_100m_delay; 694 mac_delay_100_10_reg_t mac34_100m_delay; 695 mac_delay_100_10_reg_t mac12_10m_delay; 696 mac_delay_100_10_reg_t mac34_10m_delay; 697 698 delay_scan_t tx_delay_scan; 699 delay_scan_t rx_delay_scan; 700 701 uint8_t Dly_in_reg_idx; 702 int8_t Dly_in_min ; 703 uint8_t Dly_in_max ; 704 uint8_t Dly_out_reg_idx ; 705 int8_t Dly_out_min ; 706 uint8_t Dly_out_max ; 707 708 uint8_t Dly_in ; 709 uint8_t Dly_in_selval ; 710 uint8_t Dly_out ; 711 uint8_t Dly_out_selval ; 712 int8_t result; 713 int8_t result_history[128][64]; 714 uint32_t init_done; 715 } MAC_IO; 716 typedef struct { 717 #ifdef Enable_ShowBW 718 double Total_frame_len ;//__attribute__ ((aligned (8))); 719 #endif 720 uint32_t Des_Num ; 721 uint32_t Des_Num_Org ; 722 uint32_t DMABuf_Size ; 723 uint32_t DMABuf_Num ; 724 725 uint32_t *FRAME_LEN ; 726 uint32_t FRAME_LEN_Cur ; 727 uint32_t *wp_lst ; 728 uint32_t wp_fir ; 729 730 uint32_t DMA_Base_Setup ; 731 uint32_t DMA_Base_Tx ; 732 uint32_t DMA_Base_Rx ; 733 734 uint32_t ARP_data[16] ; 735 uint32_t TxDes0DW ; 736 uint32_t RxDes0DW ; 737 uint32_t RxDes3DW ; 738 739 uint8_t number_chl ; 740 uint8_t number_pak ; 741 char NCSI_RxEr ; 742 uint32_t NCSI_TxDWBUF[512] ; 743 uint32_t NCSI_RxDWBUF[512] ; 744 char NCSI_CommandStr[512] ; 745 unsigned char *NCSI_TxByteBUF ; 746 unsigned char *NCSI_RxByteBUF ; 747 unsigned char NCSI_Payload_Data[16] ; 748 uint32_t Payload_Checksum_NCSI ; 749 } MAC_Data; 750 751 typedef struct { 752 uint32_t warn; 753 uint32_t error; 754 uint32_t desc; 755 uint32_t ncsi; 756 uint32_t error_backup; 757 uint32_t ncsi_backup; 758 uint32_t n_desc_fail; 759 uint8_t print_en; 760 uint8_t all_fail; 761 } MAC_Flag; 762 763 typedef struct { 764 mac_reg_t reg; 765 mac_env_t env; 766 mac_arg_t arg; 767 MAC_Running run; 768 MAC_Information inf; 769 MAC_PHY phy; 770 MAC_IO io; 771 MAC_Data dat; 772 MAC_Flag flg; 773 NCSI_Command_Packet ncsi_req; 774 NCSI_Response_Packet ncsi_rsp; 775 NCSI_Capability ncsi_cap; 776 } MAC_ENGINE; 777 typedef void (* PHY_SETTING) (MAC_ENGINE *); 778 typedef struct { 779 PHY_SETTING fp_set; 780 PHY_SETTING fp_clr; 781 } PHY_ENGINE; 782 783 #undef GLOBAL 784 #ifdef NCSI_C 785 #define GLOBAL 786 #else 787 #define GLOBAL extern 788 #endif 789 790 GLOBAL char phy_ncsi (MAC_ENGINE *eng); 791 792 // ======================================================== 793 // For mactest 794 795 #undef GLOBAL 796 #ifdef MACTEST_C 797 #define GLOBAL 798 #else 799 #define GLOBAL extern 800 #endif 801 802 #define MODE_DEDICATED 0x01 803 #define MODE_NCSI 0x02 804 805 GLOBAL uint8_t *mmiobase; 806 GLOBAL uint32_t ulPCIBaseAddress; 807 GLOBAL uint32_t ulMMIOBaseAddress; 808 809 GLOBAL uint8_t display_lantest_log_msg; 810 811 // ======================================================== 812 // For mac.c 813 #undef GLOBAL 814 #ifdef MAC_C 815 #define GLOBAL 816 #else 817 #define GLOBAL extern 818 #endif 819 820 #if defined(MAC_C) 821 static const char version_name[] = VER_NAME; 822 static const uint8_t IOValue_Array_A0[16] = {8,1, 10,3, 12,5, 14,7, 0,9, 2,11, 4,13, 6,15}; // AST2300-A0 823 #endif 824 825 GLOBAL void debug_pause (void); 826 GLOBAL uint32_t Read_Mem_Dat_NCSI_DD (uint32_t addr); 827 GLOBAL uint32_t Read_Mem_Des_NCSI_DD (uint32_t addr); 828 829 830 831 832 833 834 835 GLOBAL void Write_Mem_Dat_NCSI_DD (uint32_t addr, uint32_t data); 836 GLOBAL void Write_Mem_Des_NCSI_DD (uint32_t addr, uint32_t data); 837 838 839 GLOBAL void Write_Reg_TIMER_DD (uint32_t addr, uint32_t data); 840 841 842 843 844 845 846 GLOBAL void PrintTest (MAC_ENGINE *eng); 847 GLOBAL void PrintIOTimingBund (MAC_ENGINE *eng); 848 849 850 851 GLOBAL void PrintPHYAdr (MAC_ENGINE *eng); 852 853 854 855 856 857 GLOBAL void setup_arp (MAC_ENGINE *eng); 858 GLOBAL void TestingSetup (MAC_ENGINE *eng); 859 860 861 862 GLOBAL void init_mac (MAC_ENGINE *eng); 863 GLOBAL char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum); 864 865 GLOBAL void init_phy (MAC_ENGINE *eng, PHY_ENGINE *phyeng); 866 867 868 GLOBAL void phy_select (MAC_ENGINE *eng, PHY_ENGINE *phyeng); 869 GLOBAL void recov_phy (MAC_ENGINE *eng, PHY_ENGINE *phyeng); 870 GLOBAL int FindErr (MAC_ENGINE *eng, int value); 871 GLOBAL int FindErr_Des (MAC_ENGINE *eng, int value); 872 GLOBAL void PrintIO_Header (MAC_ENGINE *eng, uint8_t option); 873 874 875 876 GLOBAL void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option); 877 878 GLOBAL void init_hwtimer( void ); 879 GLOBAL void delay_hwtimer(uint16_t msec); 880 881 // ======================================================== 882 // For PHYGPIO.c 883 #undef GLOBAL 884 #ifdef PHYGPIO_C 885 #define GLOBAL 886 #else 887 #define GLOBAL extern 888 #endif 889 890 891 // ======================================================== 892 // For PHYSPECIAL.c 893 #undef GLOBAL 894 #ifdef PHYMISC_C 895 #define GLOBAL 896 #else 897 #define GLOBAL extern 898 #endif 899 900 901 #endif // End COMMINF_H 902