1 /* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11 12 #ifndef COMMINF_H 13 #define COMMINF_H 14 15 #include "swfunc.h" 16 17 #include "mac.h" 18 19 //--------------------------------------------------------- 20 // Print Message 21 //--------------------------------------------------------- 22 // for function 23 #define FP_LOG 0 24 #define FP_IO 1 25 #define STD_OUT 2 26 27 #define PRINTF(i, ...) \ 28 do { \ 29 if (i == STD_OUT) { \ 30 fprintf(stdout, __VA_ARGS__); \ 31 break; \ 32 } \ 33 if ((display_lantest_log_msg != 0) && (i == FP_LOG)) { \ 34 fprintf(stdout, "[Log]: "); \ 35 fprintf(stdout, __VA_ARGS__); \ 36 } \ 37 } while (0); 38 39 //--------------------------------------------------------- 40 // Function 41 //--------------------------------------------------------- 42 #define SWAP_4B( x ) \ 43 ( ( ( ( x ) & 0xff000000 ) >> 24) \ 44 | ( ( ( x ) & 0x00ff0000 ) >> 8) \ 45 | ( ( ( x ) & 0x0000ff00 ) << 8) \ 46 | ( ( ( x ) & 0x000000ff ) << 24) \ 47 ) 48 #define SWAP_2B( x ) \ 49 ( ( ( ( x ) & 0xff00 ) >> 8) \ 50 | ( ( ( x ) & 0x00ff ) << 8) \ 51 ) 52 53 #define SWAP_2B_BEDN( x ) ( SWAP_2B ( x ) ) 54 #define SWAP_2B_LEDN( x ) ( x ) 55 #define SWAP_4B_BEDN( x ) ( SWAP_4B ( x ) ) 56 #define SWAP_4B_LEDN( x ) ( x ) 57 58 #define SWAP_4B_BEDN_NCSI( x ) ( SWAP_4B( x ) ) 59 #define SWAP_4B_LEDN_NCSI( x ) ( x ) 60 61 #if defined(ENABLE_BIG_ENDIAN_MEM) 62 #define SWAP_4B_LEDN_MEM( x ) ( SWAP_4B( x ) ) 63 #else 64 #define SWAP_4B_LEDN_MEM( x ) ( x ) 65 #endif 66 #if defined(ENABLE_BIG_ENDIAN_REG) 67 #define SWAP_4B_LEDN_REG( x ) ( SWAP_4B( x ) ) 68 #else 69 #define SWAP_4B_LEDN_REG( x ) ( x ) 70 #endif 71 72 #define DELAY( x ) udelay( ( x ) * 1000 ) 73 #define GET_CAHR getc 74 75 //--------------------------------------------------------- 76 // Default argument 77 //--------------------------------------------------------- 78 #define DEF_GUSER_DEF_PACKET_VAL 0xaaaaaaaa //0xff00ff00, 0xf0f0f0f0, 0xcccccccc, 0x55aa55aa, 0x5a5a5a5a, 0x66666666 79 #define DEF_GIOTIMINGBUND 2 80 #define DEF_GPHY_ADR 0 81 #define DEF_GTESTMODE 0 //[0]0: no burst mode, 1: 0xff, 2: 0x55, 3: random, 4: ARP, 5: ARP, 6: IO timing, 7: IO timing+IO Strength 82 #define DEF_GLOOP_MAX 1 83 #define DEF_GCTRL 0 84 85 #define SET_1GBPS BIT(0) 86 #define SET_100MBPS BIT(1) 87 #define SET_10MBPS BIT(2) 88 #define SET_1G_100M_10MBPS (SET_1GBPS | SET_100MBPS | SET_10MBPS) 89 #define SET_100M_10MBPS (SET_100MBPS | SET_10MBPS) 90 91 #define DEF_GSPEED SET_1G_100M_10MBPS 92 #define DEF_GARPNUMCNT 0 93 94 //--------------------------------------------------------- 95 // MAC information 96 //--------------------------------------------------------- 97 98 #define MDC_Thres 0x3f 99 #define MAC_PHYWr 0x08000000 100 #define MAC_PHYRd 0x04000000 101 102 #ifdef CONFIG_ASPEED_AST2600 103 #define MAC_PHYWr_New (BIT(31) | BIT(28) | (0x1 << 26)) /* 0x94000000 */ 104 #define MAC_PHYRd_New (BIT(31) | BIT(28) | (0x2 << 26)) /* 0x98000000 */ 105 #define MAC_PHYBusy_New BIT(31) 106 #else 107 #define MAC_PHYWr_New 0x00009400 108 #define MAC_PHYRd_New 0x00009800 109 #define MAC_PHYBusy_New 0x00008000 110 #endif 111 112 #define MAC_048_def 0x000002F1 //default 0xf1 113 //#define MAC_058_def 0x00000040 //0x000001c0 114 115 //--------------------------------------------------------- 116 // Data information 117 //--------------------------------------------------------- 118 #define ZeroCopy_OFFSET (( eng->run.tm_tx_only ) ? 0 : 2) 119 120 // --------------------------------- DRAM_MapAdr = tdes_base 121 // | TX descriptor ring | 122 // ------------------------- DRAM_MapAdr + 0x040000 = rdes_base 123 // | RX descriptor ring | 124 // ------------------------- 125 // | Reserved | 126 // ------------------------- 127 // | Reserved | 128 // --------------------------------- DRAM_MapAdr + 0x100000 = DMA_BASE ------------------------- 129 // | #1 | \ | #1 Tx | 130 // DMA buffer | | DMA_BufSize | LOOP = 0 | 131 // ( Tx/Rx ) ------------------------- / -------------------------------------------------- 132 // | #2 | | #2 Rx | #2 Tx | 133 // | | | LOOP = 0 | LOOP = 1 | 134 // ------------------------- -------------------------------------------------- 135 // | #3 | | #3 Rx | 136 // | | | LOOP = 1 | 137 // ------------------------- ------------------------- 138 // | #4 | .......... 139 // | | 140 // ------------------------- 141 // | #5 | 142 // | | 143 // ------------------------- 144 // | #6 | 145 // | | 146 // ------------------------- 147 // . 148 // . 149 // ------------------------- 150 // | #n, n = DMA_BufNum | 151 // | | 152 // --------------------------------- 153 154 #define BUF_SIZE 0x04000000 155 #define TDES_SIZE 0x00040000 156 #define RDES_SIZE 0x00040000 157 #define RESV_SIZE 0x00000000 /* reserved */ 158 159 #define TDES_IniVal (0xb0000000 + eng->dat.FRAME_LEN_Cur) 160 #define RDES_IniVal (0x00000fff) 161 #define EOR_IniVal (0x40000000) 162 #define HWOwnTx(dat) (dat & 0x80000000) 163 #define HWOwnRx(dat) ((dat & 0x80000000) == 0) 164 #define HWEOR(dat) (dat & 0x40000000) 165 166 #define AT_MEMRW_BUF(x) ((x) - ASPEED_DRAM_BASE) 167 #define AT_BUF_MEMRW(x) ((x) + ASPEED_DRAM_BASE) 168 169 //--------------------------------------------------------- 170 // Error Flag Bits 171 //--------------------------------------------------------- 172 #define Err_Flag_MACMode ( 1 << 0 ) // MAC interface mode mismatch 173 #define Err_Flag_PHY_Type ( 1 << 1 ) // Unidentifiable PHY 174 #define Err_Flag_MALLOC_FrmSize ( 1 << 2 ) // Malloc fail at frame size buffer 175 #define Err_Flag_MALLOC_LastWP ( 1 << 3 ) // Malloc fail at last WP buffer 176 #define Err_Flag_Check_Buf_Data ( 1 << 4 ) // Received data mismatch 177 #define Err_Flag_Check_Des ( 1 << 5 ) // Descriptor error 178 #define ERR_FLAG_NCSI_LINKFAIL (1 << 6) // NCSI packet retry number over flows 179 #define Err_Flag_NCSI_Check_TxOwnTimeOut ( 1 << 7 ) // Time out of checking Tx owner bit in NCSI packet 180 #define Err_Flag_NCSI_Check_RxOwnTimeOut ( 1 << 8 ) // Time out of checking Rx owner bit in NCSI packet 181 #define Err_Flag_NCSI_Check_ARPOwnTimeOut ( 1 << 9 ) // Time out of checking ARP owner bit in NCSI packet 182 #define Err_Flag_NCSI_No_PHY ( 1 << 10 ) // Can not find NCSI PHY 183 #define Err_Flag_NCSI_Channel_Num ( 1 << 11 ) // NCSI Channel Number Mismatch 184 #define Err_Flag_NCSI_Package_Num ( 1 << 12 ) // NCSI Package Number Mismatch 185 #define Err_Flag_PHY_TimeOut_RW ( 1 << 13 ) // Time out of read/write PHY register 186 #define Err_Flag_PHY_TimeOut_Rst ( 1 << 14 ) // Time out of reset PHY register 187 #define Err_Flag_RXBUF_UNAVA ( 1 << 15 ) // MAC00h[2]:Receiving buffer unavailable 188 #define Err_Flag_RPKT_LOST ( 1 << 16 ) // MAC00h[3]:Received packet lost due to RX FIFO full 189 #define Err_Flag_NPTXBUF_UNAVA ( 1 << 17 ) // MAC00h[6]:Normal priority transmit buffer unavailable 190 #define Err_Flag_TPKT_LOST ( 1 << 18 ) // MAC00h[7]:Packets transmitted to Ethernet lost 191 #define Err_Flag_DMABufNum ( 1 << 19 ) // DMA Buffer is not enough 192 #define Err_Flag_IOMargin ( 1 << 20 ) // IO timing margin is not enough 193 #define Err_Flag_IOMarginOUF ( 1 << 21 ) // IO timing testing out of boundary 194 #define Err_Flag_MHCLK_Ratio ( 1 << 22 ) // Error setting of MAC AHB bus clock (SCU08[18:16]) 195 196 #define Wrn_Flag_IOMarginOUF ( 1 << 0 ) // IO timing testing out of boundary 197 #define Wrn_Flag_RxErFloatting ( 1 << 1 ) // NCSI RXER pin may be floatting to the MAC 198 //#define Wrn_Flag_RMIICK_IOMode ( 1 << 2 ) // The PHY's RMII refreence clock input/output mode 199 200 #define PHY_Flag_RMIICK_IOMode_RTL8201E ( 1 << 0 ) 201 #define PHY_Flag_RMIICK_IOMode_RTL8201F ( 1 << 1 ) 202 203 #define Des_Flag_TxOwnTimeOut ( 1 << 0 ) // Time out of checking Tx owner bit 204 #define Des_Flag_RxOwnTimeOut ( 1 << 1 ) // Time out of checking Rx owner bit 205 #define Des_Flag_FrameLen ( 1 << 2 ) // Frame length mismatch 206 #define Des_Flag_RxErr ( 1 << 3 ) // Input signal RxErr 207 #define Des_Flag_CRC ( 1 << 4 ) // CRC error of frame 208 #define Des_Flag_FTL ( 1 << 5 ) // Frame too long 209 #define Des_Flag_Runt ( 1 << 6 ) // Runt packet 210 #define Des_Flag_OddNibble ( 1 << 7 ) // Nibble bit happen 211 #define Des_Flag_RxFIFOFull ( 1 << 8 ) // Rx FIFO full 212 213 #define NCSI_Flag_Get_Version_ID ( 1 << 0 ) // Time out when Get Version ID 214 #define NCSI_Flag_Get_Capabilities ( 1 << 1 ) // Time out when Get Capabilities 215 #define NCSI_Flag_Select_Active_Package ( 1 << 2 ) // Time out when Select Active Package 216 #define NCSI_Flag_Enable_Set_MAC_Address ( 1 << 3 ) // Time out when Enable Set MAC Address 217 #define NCSI_Flag_Enable_Broadcast_Filter ( 1 << 4 ) // Time out when Enable Broadcast Filter 218 #define NCSI_Flag_Enable_Network_TX ( 1 << 5 ) // Time out when Enable Network TX 219 #define NCSI_Flag_Enable_Channel ( 1 << 6 ) // Time out when Enable Channel 220 #define NCSI_Flag_Disable_Network_TX ( 1 << 7 ) // Time out when Disable Network TX 221 #define NCSI_Flag_Disable_Channel ( 1 << 8 ) // Time out when Disable Channel 222 #define NCSI_Flag_Select_Package ( 1 << 9 ) // Time out when Select Package 223 #define NCSI_Flag_Deselect_Package ( 1 << 10 ) // Time out when Deselect Package 224 #define NCSI_Flag_Set_Link ( 1 << 11 ) // Time out when Set Link 225 #define NCSI_Flag_Get_Controller_Packet_Statistics ( 1 << 12 ) // Time out when Get Controller Packet Statistics 226 #define NCSI_Flag_Reset_Channel ( 1 << 13 ) // Time out when Reset Channel 227 228 //--------------------------------------------------------- 229 // DMA Buffer information 230 //--------------------------------------------------------- 231 #define DMA_BUF_SIZE (56 * 1024 * 1024) 232 extern uint8_t dma_buf[DMA_BUF_SIZE]; 233 234 #define DMA_BASE ((uint32_t)(&dma_buf[0])) 235 /* The size of one LAN packet */ 236 #define DMA_PakSize (2 * 1024) 237 238 #ifdef SelectSimpleBoundary 239 #define DMA_BufSize (((((p_eng->dat.Des_Num + 15) * DMA_PakSize) >> 2) << 2)) 240 #else 241 #define DMA_BufSize \ 242 (4 + ((((p_eng->dat.Des_Num + 15) * DMA_PakSize) >> 2) << 2)) 243 #endif 244 #define DMA_BufNum (DMA_BUF_SIZE / (p_eng->dat.DMABuf_Size)) 245 246 /* get DMA buffer address according to the loop counter */ 247 #define GET_DMA_BASE(p_eng, x) \ 248 (DMA_BASE + ((((x) % p_eng->dat.DMABuf_Num)) * p_eng->dat.DMABuf_Size)) 249 250 #define SEED_START 8 251 #define DATA_SEED(seed) ( ( seed ) | (( seed + 1 ) << 16 ) ) 252 #define DATA_IncVal 0x00020001 253 #define PktByteSize ( ( ( ( ZeroCopy_OFFSET + eng->dat.FRAME_LEN_Cur - 1 ) >> 2 ) + 1) << 2 ) 254 255 //--------------------------------------------------------- 256 // Delay (ms) 257 //--------------------------------------------------------- 258 //#define Delay_DesGap 1 //off 259 //#define Delay_CntMax 40 260 //#define Delay_CntMax 1000 261 //#define Delay_CntMax 8465 262 //#define Delay_CntMaxIncVal 50000 263 #define Delay_CntMaxIncVal 47500 264 265 266 //#define Delay_ChkRxOwn 1 267 //#define Delay_ChkTxOwn 1 268 269 #define Delay_PHYRst 100 270 //#define Delay_PHYRd 5 271 #define Delay_PHYRd 1 //20150423 272 273 #define Delay_MACRst 1 274 #define Delay_MACDump 1 275 276 //#define Delay_DES 1 277 278 //--------------------------------------------------------- 279 // Time Out 280 //--------------------------------------------------------- 281 #define TIME_OUT_Des_1G 10000 //400 282 #define TIME_OUT_Des_100M 20000 //4000 283 #define TIME_OUT_Des_10M 50000 //20000 284 #define TIME_OUT_NCSI 100000 //40000 285 #define TIME_OUT_PHY_RW 2000000 //100000 286 #define TIME_OUT_PHY_Rst 20000 //1000 287 288 //--------------------------------------------------------- 289 // Chip memory MAP 290 //--------------------------------------------------------- 291 typedef union { 292 uint32_t w; 293 struct { 294 uint32_t txdma_en : 1; /* bit[0] */ 295 uint32_t rxdma_en : 1; /* bit[1] */ 296 uint32_t txmac_en : 1; /* bit[2] */ 297 uint32_t rxmac_en : 1; /* bit[3] */ 298 uint32_t rm_vlan : 1; /* bit[4] */ 299 uint32_t hptxr_en : 1; /* bit[5] */ 300 uint32_t phy_link_sts_dtct : 1; /* bit[6] */ 301 uint32_t enrx_in_halftx : 1; /* bit[7] */ 302 uint32_t fulldup : 1; /* bit[8] */ 303 uint32_t gmac_mode : 1; /* bit[9] */ 304 uint32_t crc_apd : 1; /* bit[10] */ 305 #ifdef CONFIG_ASPEED_AST2600 306 uint32_t reserved_1 : 1; /* bit[11] */ 307 #else 308 uint32_t phy_link_lvl_dtct : 1; /* bit[11] */ 309 #endif 310 uint32_t rx_runt : 1; /* bit[12] */ 311 uint32_t jumbo_lf : 1; /* bit[13] */ 312 uint32_t rx_alladr : 1; /* bit[14] */ 313 uint32_t rx_ht_en : 1; /* bit[15] */ 314 uint32_t rx_multipkt_en : 1; /* bit[16] */ 315 uint32_t rx_broadpkt_en : 1; /* bit[17] */ 316 uint32_t discard_crcerr : 1; /* bit[18] */ 317 uint32_t speed_100 : 1; /* bit[19] */ 318 uint32_t reserved_0 : 11; /* bit[30:20] */ 319 uint32_t sw_rst : 1; /* bit[31] */ 320 }b; 321 } mac_cr_t; 322 // ======================================================== 323 // For ncsi.c 324 325 #define DEF_GPACKAGE2NUM 1 // Default value 326 #define DEF_GCHANNEL2NUM 1 // Default value 327 328 //--------------------------------------------------------- 329 // Variable 330 //--------------------------------------------------------- 331 //NC-SI Command Packet 332 typedef struct { 333 //Ethernet Header 334 unsigned char DA[6]; // Destination Address 335 unsigned char SA[6]; // Source Address 336 uint16_t EtherType; // DMTF NC-SI, it should be 0x88F8 337 //NC-SI Control Packet 338 unsigned char MC_ID; // Management Controller should set this field to 0x00 339 unsigned char Header_Revision; // For NC-SI 1.0 spec, this field has to set 0x01 340 unsigned char Reserved_1; // Reserved has to set to 0x00 341 unsigned char IID; // Instance ID 342 unsigned char Command; 343 // unsigned char Channel_ID; 344 unsigned char ChID; 345 uint16_t Payload_Length; // Payload Length = 12 bits, 4 bits are reserved 346 uint32_t Reserved_2; 347 uint32_t Reserved_3; 348 349 uint16_t Reserved_4; 350 uint16_t Reserved_5; 351 uint16_t Response_Code; 352 uint16_t Reason_Code; 353 unsigned char Payload_Data[64]; 354 #if !defined(SLT_UBOOT) 355 } NCSI_Command_Packet; 356 #else 357 } __attribute__ ((__packed__)) NCSI_Command_Packet; 358 #endif 359 360 //NC-SI Response Packet 361 typedef struct { 362 unsigned char DA[6]; 363 unsigned char SA[6]; 364 uint16_t EtherType; //DMTF NC-SI 365 //NC-SI Control Packet 366 unsigned char MC_ID; //Management Controller should set this field to 0x00 367 unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01 368 unsigned char Reserved_1; //Reserved has to set to 0x00 369 unsigned char IID; //Instance ID 370 unsigned char Command; 371 // unsigned char Channel_ID; 372 unsigned char ChID; 373 uint16_t Payload_Length; //Payload Length = 12 bits, 4 bits are reserved 374 uint16_t Reserved_2; 375 uint16_t Reserved_3; 376 uint16_t Reserved_4; 377 uint16_t Reserved_5; 378 379 uint16_t Response_Code; 380 uint16_t Reason_Code; 381 unsigned char Payload_Data[64]; 382 #if !defined(SLT_UBOOT) 383 } NCSI_Response_Packet; 384 #else 385 } __attribute__ ((__packed__)) NCSI_Response_Packet; 386 #endif 387 388 typedef struct { 389 unsigned char All_ID ; 390 unsigned char Package_ID ; 391 unsigned char Channel_ID ; 392 uint32_t Capabilities_Flags ; 393 uint32_t Broadcast_Packet_Filter_Capabilities ; 394 uint32_t Multicast_Packet_Filter_Capabilities ; 395 uint32_t Buffering_Capabilities ; 396 uint32_t AEN_Control_Support ; 397 unsigned char VLAN_Filter_Count ; 398 unsigned char Mixed_Filter_Count ; 399 unsigned char Multicast_Filter_Count ; 400 unsigned char Unicast_Filter_Count ; 401 unsigned char VLAN_Mode_Support ; 402 unsigned char Channel_Count ; 403 uint32_t PCI_DID_VID ; 404 uint32_t manufacturer_id ; 405 } NCSI_Capability; 406 407 typedef struct { 408 mac_cr_t maccr; 409 uint32_t mac_madr; 410 uint32_t mac_ladr; 411 uint32_t mac_fear; 412 413 uint32_t WDT_00c ; 414 uint32_t WDT_02c ; 415 uint32_t WDT_04c ; 416 417 int8_t SCU_oldvld; 418 } mac_reg_t; 419 typedef struct { 420 uint8_t ast2600; 421 uint8_t ast2500; 422 uint8_t mac_num; 423 uint8_t is_new_mdio_reg[4]; 424 425 uint8_t is_1g_valid[4]; 426 uint8_t at_least_1g_valid; 427 uint8_t MHCLK_Ratio; 428 } mac_env_t; 429 430 typedef union { 431 uint32_t w; 432 struct { 433 uint32_t skip_phy_init : 1; /* bit[0] */ 434 uint32_t skip_phy_deinit: 1; /* bit[1] */ 435 uint32_t skip_phy_id_check : 1; /* bit[2] */ 436 uint32_t reserved_0 : 1; /* bit[3] */ 437 uint32_t phy_int_loopback : 1; /* bit[4] */ 438 uint32_t mac_int_loopback : 1; /* bit[5] */ 439 uint32_t phy_rx_delay_en: 1; /* bit[6] */ 440 uint32_t phy_tx_delay_en: 1; /* bit[7] */ 441 uint32_t rmii_50m_out : 1; /* bit[8] */ 442 uint32_t rmii_phy_in : 1; /* bit[9] */ 443 uint32_t inv_rgmii_rxclk: 1; /* bit[10] */ 444 uint32_t reserved_2 : 1; /* bit[11] */ 445 uint32_t single_packet : 1; /* bit[12] */ 446 uint32_t full_range : 1; /* bit[13] */ 447 uint32_t reserved_3 : 2; /* bit[15:14] */ 448 uint32_t print_ncsi : 1; /* bit[16] */ 449 uint32_t skip_rx_err : 1; /* bit[17] */ 450 } b; 451 } mac_arg_ctrl_t; 452 typedef struct { 453 uint32_t run_mode; /* select dedicated or NCSI */ 454 uint32_t mac_idx; /* argv[1] */ 455 uint32_t mdio_idx; 456 uint32_t run_speed; /* argv[2] for dedicated */ 457 mac_arg_ctrl_t ctrl; /* argv[3] for dedicated 458 argv[6] for ncsi */ 459 uint32_t loop_max; /* argv[4] for dedicated */ 460 uint32_t loop_inf; /* argv[4] for dedicated */ 461 462 uint32_t GPackageTolNum; /* argv[2] for ncsi */ 463 uint32_t GChannelTolNum; /* argv[3] for ncsi */ 464 465 uint32_t test_mode; /* argv[5] for dedicated 466 argv[4] for ncsi */ 467 468 uint32_t phy_addr; /* argv[6] for dedicated */ 469 uint32_t delay_scan_range; /* argv[7] for dedicated 470 argv[5] for ncsi */ 471 uint32_t ieee_sel; /* argv[7] for dedicated */ 472 473 uint32_t GARPNumCnt; /* argv[7] for ncsi */ 474 uint32_t user_def_val; /* argv[8] for dedicated */ 475 } mac_arg_t; 476 typedef struct { 477 uint32_t mac_idx; 478 uint32_t mac_base; 479 uint32_t mdio_idx; 480 uint32_t mdio_base; 481 uint32_t is_rgmii; 482 uint32_t ieee_sel; /* derived from delay_scan_range */ 483 484 uint32_t tdes_base; 485 uint32_t rdes_base; 486 487 uint32_t ncsi_tdes_base; 488 uint32_t ncsi_rdes_base; 489 490 uint32_t LOOP_CheckNum ; 491 uint32_t CheckBuf_MBSize ; 492 uint32_t timeout_th; /* time out threshold (varies with run-speed) */ 493 494 uint32_t loop_max; 495 uint32_t loop_of_cnt; 496 uint32_t loop_cnt; 497 uint32_t speed_idx; 498 int NCSI_RxTimeOutScale ; 499 500 uint8_t speed_cfg[3]; 501 uint8_t speed_sel[3]; 502 503 /* test mode */ 504 uint8_t delay_margin; 505 uint8_t tm_tx_only; 506 int8_t TM_IEEE ;//test_mode 507 int8_t TM_IOTiming ;//test_mode 508 int8_t TM_IOStrength ;//test_mode 509 int8_t TM_TxDataEn ;//test_mode 510 int8_t TM_RxDataEn ;//test_mode 511 int8_t TM_WaitStart ;//test_mode 512 int8_t TM_DefaultPHY ;//test_mode 513 int8_t TM_NCSI_DiSChannel ;//test_mode 514 515 int8_t IO_MrgChk ; 516 517 518 } MAC_Running; 519 520 typedef struct { 521 uint8_t SA[6]; 522 } MAC_Information; 523 524 typedef struct { 525 uint32_t mdio_base; 526 uint32_t loopback; 527 uint8_t phy_name[64]; 528 int8_t default_phy ; 529 int8_t Adr ; 530 531 uint16_t id2 ; 532 uint16_t id1 ; 533 534 uint32_t PHY_00h ; 535 uint32_t PHY_06h ; 536 uint32_t PHY_09h ; 537 uint32_t PHY_0eh ; 538 uint32_t PHY_10h ; 539 uint32_t PHY_11h ; 540 uint32_t PHY_12h ; 541 uint32_t PHY_14h ; 542 uint32_t PHY_15h ; 543 uint32_t PHY_18h ; 544 uint32_t PHY_19h ; 545 uint32_t PHY_1ch ; 546 uint32_t PHY_1eh ; 547 uint32_t PHY_1fh ; 548 uint32_t PHY_06hA[7] ; 549 550 uint32_t RMIICK_IOMode ; 551 } MAC_PHY; 552 553 #ifdef CONFIG_ASPEED_AST2600 554 typedef union { 555 uint32_t w; 556 struct { 557 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 558 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 559 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 560 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 561 uint32_t rx_clk_inv_1 : 1; /* bit[24] */ 562 uint32_t rx_clk_inv_2 : 1; /* bit[25] */ 563 uint32_t rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 564 uint32_t rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 565 uint32_t rgmiick_pad_dir : 1; /* bit[28] */ 566 uint32_t rmii_50m_oe_1 : 1; /* bit[29] */ 567 uint32_t rmii_50m_oe_2 : 1; /* bit[30] */ 568 uint32_t rgmii_125m_o_sel : 1; /* bit[31] */ 569 }b; 570 } mac_delay_1g_t; 571 572 typedef union { 573 uint32_t w; 574 struct { 575 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 576 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 577 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 578 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 579 uint32_t rx_clk_inv_1 : 1; /* bit[24] */ 580 uint32_t rx_clk_inv_2 : 1; /* bit[25] */ 581 uint32_t reserved_0 : 6; /* bit[31:26] */ 582 }b; 583 } mac_delay_100_10_t; 584 #else 585 typedef union { 586 uint32_t w; 587 struct { 588 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 589 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 590 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 591 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 592 uint32_t rmii_tx_data_at_falling_1 : 1; /* bit[24] */ 593 uint32_t rmii_tx_data_at_falling_2 : 1; /* bit[25] */ 594 uint32_t reserved : 3; /* bit[28:26] */ 595 uint32_t rmii_50m_oe_1 : 1; /* bit[29] */ 596 uint32_t rmii_50m_oe_2 : 1; /* bit[30] */ 597 uint32_t rgmii_125m_o_sel : 1; /* bit[31] */ 598 }b; 599 } mac_delay_1g_t; 600 601 typedef union { 602 uint32_t w; 603 struct { 604 uint32_t tx_delay_1 : 6; /* bit[5:0] */ 605 uint32_t tx_delay_2 : 6; /* bit[11:6] */ 606 uint32_t rx_delay_1 : 6; /* bit[17:12] */ 607 uint32_t rx_delay_2 : 6; /* bit[23:18] */ 608 uint32_t enable : 1; /* bit[24] */ 609 uint32_t reserved_0 : 7; /* bit[31:25] */ 610 }b; 611 } mac_delay_100_10_t; 612 #endif 613 614 typedef struct mac_delay_1g_reg_s { 615 uint32_t addr; 616 int32_t tx_min; 617 int32_t tx_max; 618 int32_t rx_min; 619 int32_t rx_max; 620 int32_t rmii_tx_min; 621 int32_t rmii_tx_max; 622 int32_t rmii_rx_min; 623 int32_t rmii_rx_max; 624 mac_delay_1g_t value; /* backup register value */ 625 } mac_delay_1g_reg_t; 626 627 typedef struct mac_delay_100_10_reg_s { 628 uint32_t addr; 629 int32_t tx_min; 630 int32_t tx_max; 631 int32_t rx_min; 632 int32_t rx_max; 633 mac_delay_100_10_t value; 634 } mac_delay_100_10_reg_t; 635 636 #ifdef CONFIG_ASPEED_AST2600 637 typedef union { 638 uint32_t w; 639 struct { 640 uint32_t mac3_tx_drv : 2; /* bit[1:0] */ 641 uint32_t mac4_tx_drv : 2; /* bit[3:2] */ 642 uint32_t reserved_0 : 28; /* bit[31:4] */ 643 }b; 644 } mac34_drv_t; 645 typedef struct mac34_drv_reg_s { 646 uint32_t addr; 647 uint32_t drv_max; 648 mac34_drv_t value; 649 } mac34_drv_reg_t; 650 651 #else 652 typedef union { 653 uint32_t w; 654 struct { 655 uint32_t reserved_0 : 8; /* bit[7:0] */ 656 uint32_t mac1_rmii_tx_drv : 1; /* bit[8] */ 657 uint32_t mac1_rgmii_tx_drv : 1; /* bit[9] */ 658 uint32_t mac2_rmii_tx_drv : 1; /* bit[10] */ 659 uint32_t mac2_rgmii_tx_drv : 1; /* bit[11] */ 660 uint32_t reserved_1 : 20; /* bit[31:12] */ 661 }b; 662 } mac12_drv_t; 663 664 typedef struct mac12_drv_reg_s { 665 uint32_t addr; 666 uint32_t drv_max; 667 mac12_drv_t value; 668 } mac12_drv_reg_t; 669 #endif 670 671 typedef struct delay_scan_s { 672 int8_t begin; 673 int8_t end; 674 int8_t step; 675 int8_t orig; 676 } delay_scan_t; 677 typedef struct { 678 /* driving strength */ 679 #ifdef CONFIG_ASPEED_AST2600 680 mac34_drv_reg_t mac34_drv_reg; 681 #else 682 mac12_drv_reg_t mac12_drv_reg; 683 #endif 684 uint32_t drv_upper_bond; 685 uint32_t drv_lower_bond; 686 uint32_t drv_curr; 687 688 mac_delay_1g_reg_t mac12_1g_delay; 689 mac_delay_1g_reg_t mac34_1g_delay; 690 mac_delay_100_10_reg_t mac12_100m_delay; 691 mac_delay_100_10_reg_t mac34_100m_delay; 692 mac_delay_100_10_reg_t mac12_10m_delay; 693 mac_delay_100_10_reg_t mac34_10m_delay; 694 695 delay_scan_t tx_delay_scan; 696 delay_scan_t rx_delay_scan; 697 698 uint8_t Dly_in_reg_idx; 699 int8_t Dly_in_min ; 700 uint8_t Dly_in_max ; 701 uint8_t Dly_out_reg_idx ; 702 int8_t Dly_out_min ; 703 uint8_t Dly_out_max ; 704 705 uint8_t Dly_in ; 706 uint8_t Dly_in_selval ; 707 uint8_t Dly_out ; 708 uint8_t Dly_out_selval ; 709 int8_t result; 710 int8_t result_history[128][64]; 711 uint32_t init_done; 712 } MAC_IO; 713 typedef struct { 714 #ifdef Enable_ShowBW 715 double Total_frame_len ;//__attribute__ ((aligned (8))); 716 #endif 717 uint32_t Des_Num ; 718 uint32_t Des_Num_Org ; 719 uint32_t DMABuf_Size ; 720 uint32_t DMABuf_Num ; 721 722 uint32_t *FRAME_LEN ; 723 uint32_t FRAME_LEN_Cur ; 724 uint32_t *wp_lst ; 725 uint32_t wp_fir ; 726 727 uint32_t DMA_Base_Setup ; 728 uint32_t DMA_Base_Tx ; 729 uint32_t DMA_Base_Rx ; 730 731 uint32_t ARP_data[16] ; 732 uint32_t TxDes0DW ; 733 uint32_t RxDes0DW ; 734 uint32_t RxDes3DW ; 735 736 uint8_t number_chl ; 737 uint8_t number_pak ; 738 char NCSI_RxEr ; 739 uint32_t NCSI_TxDWBUF[512] ; 740 uint32_t NCSI_RxDWBUF[512] ; 741 char NCSI_CommandStr[512] ; 742 unsigned char *NCSI_TxByteBUF ; 743 unsigned char *NCSI_RxByteBUF ; 744 unsigned char NCSI_Payload_Data[16] ; 745 uint32_t Payload_Checksum_NCSI ; 746 } MAC_Data; 747 748 typedef struct { 749 uint32_t warn; 750 uint32_t error; 751 uint32_t desc; 752 uint32_t ncsi; 753 uint32_t error_backup; 754 uint32_t ncsi_backup; 755 uint32_t n_desc_fail; 756 uint8_t print_en; 757 uint8_t all_fail; 758 } MAC_Flag; 759 760 typedef struct { 761 mac_reg_t reg; 762 mac_env_t env; 763 mac_arg_t arg; 764 MAC_Running run; 765 MAC_Information inf; 766 MAC_PHY phy; 767 MAC_IO io; 768 MAC_Data dat; 769 MAC_Flag flg; 770 NCSI_Command_Packet ncsi_req; 771 NCSI_Response_Packet ncsi_rsp; 772 NCSI_Capability ncsi_cap; 773 } MAC_ENGINE; 774 typedef void (* PHY_SETTING) (MAC_ENGINE *); 775 typedef struct { 776 PHY_SETTING fp_set; 777 PHY_SETTING fp_clr; 778 } PHY_ENGINE; 779 780 #undef GLOBAL 781 #ifdef NCSI_C 782 #define GLOBAL 783 #else 784 #define GLOBAL extern 785 #endif 786 787 GLOBAL char phy_ncsi (MAC_ENGINE *eng); 788 789 // ======================================================== 790 // For mactest 791 792 #undef GLOBAL 793 #ifdef MACTEST_C 794 #define GLOBAL 795 #else 796 #define GLOBAL extern 797 #endif 798 799 #define MODE_DEDICATED 0x01 800 #define MODE_NCSI 0x02 801 802 GLOBAL uint8_t *mmiobase; 803 GLOBAL uint32_t ulPCIBaseAddress; 804 GLOBAL uint32_t ulMMIOBaseAddress; 805 806 GLOBAL uint8_t display_lantest_log_msg; 807 808 // ======================================================== 809 // For mac.c 810 #undef GLOBAL 811 #ifdef MAC_C 812 #define GLOBAL 813 #else 814 #define GLOBAL extern 815 #endif 816 817 #if defined(MAC_C) 818 static const char version_name[] = VER_NAME; 819 static const uint8_t IOValue_Array_A0[16] = {8,1, 10,3, 12,5, 14,7, 0,9, 2,11, 4,13, 6,15}; // AST2300-A0 820 #endif 821 822 GLOBAL void debug_pause (void); 823 GLOBAL uint32_t Read_Mem_Dat_NCSI_DD (uint32_t addr); 824 GLOBAL uint32_t Read_Mem_Des_NCSI_DD (uint32_t addr); 825 826 827 828 829 830 831 832 GLOBAL void Write_Mem_Dat_NCSI_DD (uint32_t addr, uint32_t data); 833 GLOBAL void Write_Mem_Des_NCSI_DD (uint32_t addr, uint32_t data); 834 835 836 GLOBAL void Write_Reg_TIMER_DD (uint32_t addr, uint32_t data); 837 838 839 840 841 842 843 GLOBAL void PrintTest (MAC_ENGINE *eng); 844 GLOBAL void PrintIOTimingBund (MAC_ENGINE *eng); 845 846 847 848 GLOBAL void PrintPHYAdr (MAC_ENGINE *eng); 849 850 851 852 853 854 GLOBAL void setup_arp (MAC_ENGINE *eng); 855 GLOBAL void TestingSetup (MAC_ENGINE *eng); 856 857 858 859 GLOBAL void init_mac (MAC_ENGINE *eng); 860 GLOBAL char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum); 861 862 GLOBAL void init_phy (MAC_ENGINE *eng, PHY_ENGINE *phyeng); 863 864 865 GLOBAL void phy_select (MAC_ENGINE *eng, PHY_ENGINE *phyeng); 866 GLOBAL void recov_phy (MAC_ENGINE *eng, PHY_ENGINE *phyeng); 867 GLOBAL int FindErr (MAC_ENGINE *eng, int value); 868 GLOBAL int FindErr_Des (MAC_ENGINE *eng, int value); 869 GLOBAL void PrintIO_Header (MAC_ENGINE *eng, uint8_t option); 870 871 872 873 GLOBAL void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option); 874 875 GLOBAL void init_hwtimer( void ); 876 GLOBAL void delay_hwtimer(uint16_t msec); 877 878 // ======================================================== 879 // For PHYGPIO.c 880 #undef GLOBAL 881 #ifdef PHYGPIO_C 882 #define GLOBAL 883 #else 884 #define GLOBAL extern 885 #endif 886 887 888 // ======================================================== 889 // For PHYSPECIAL.c 890 #undef GLOBAL 891 #ifdef PHYMISC_C 892 #define GLOBAL 893 #else 894 #define GLOBAL extern 895 #endif 896 897 898 #endif // End COMMINF_H 899