1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <exports.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <reset.h> 12 #include <fdtdec.h> 13 #include <asm/io.h> 14 15 #include "dptest.h" 16 17 /* Version info*/ 18 #define MAINVER 0 19 #define SUBVER 3 20 #define TEMPVER 2 21 22 #define YEAR 2022 23 #define MONTH 07 24 #define DAY 11 25 26 /* Compile define */ 27 /* #define RE_DRIVER */ 28 /* #define INTERNAL */ 29 30 /* Debug define */ 31 #define DBG_Print 32 33 #define DBG_ERR 0x00000001 /* DBG_ERROR */ 34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */ 35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */ 36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */ 37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */ 38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */ 39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */ 40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */ 41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */ 42 /* #define DBG_AUX_W 0x00002000 *//*DBG_AUX_W_VALUE */ 43 44 int DBG_LEVEL = 0x00000040; /* Information and stage */ 45 /* int DBG_LEVEL = 0x0000107F; *//*Fully */ 46 /* int DBG_LEVEL = 0x00000001; *//*Error */ 47 48 #ifdef DBG_Print 49 #define DBG(Level, format, args...) if ((Level) & DBG_LEVEL) printf(format, ##args) 50 #else 51 #define DBG(Level, format, args...) 52 #endif 53 54 int PHY_Cfg_N; 55 int PHY_Cfg; 56 int PHY_Cfg_1; 57 int TX_SSCG_Cfg; 58 int DP_Rate; 59 int Deemphasis_Level; 60 int Deemphasis_Level_1; 61 int Deemphasis_Show; 62 int Deemphasis_RD; 63 int Swing_Level; 64 int SSCG; 65 int SSC_SHIFT; 66 int Current_Item; 67 int GFlag; 68 uchar EDID[256]; 69 70 int I2C_PORT;/* I2c port */ 71 int I2C_BASE; 72 int I2C_BUFF; 73 uchar RD_VAL; 74 75 /* Record DP Sink status */ 76 uchar bEn_Frame; 77 uchar Link_Aux_RD_Val; 78 uchar CR_EQ_Keep; 79 int Deemlevel[3] = {DP_DEEMP_2, DP_DEEMP_0, DP_DEEMP_1}; 80 uchar Auto_Link_Rate; 81 uchar Auto_Lane_Count; 82 /* uchar Patch_Normal_Behavior; */ 83 84 static int 85 do_ast_dptest(cmd_tbl_t *cmdtp, int flags, int argc, char *const argv[]) 86 { 87 char received = 0; 88 char execute_test = 0; 89 int flag = 0, i; 90 char *Temp = NULL; 91 92 /* Default setting */ 93 DP_Rate = DP_RATE_1_62; 94 95 Deemphasis_Show = DP_DEEMP_0; 96 Deemphasis_Level = DP_DEEMP_0; 97 Deemphasis_Level_1 = DP_DEEMP_2; 98 Swing_Level = 2; 99 SSCG = DP_SSCG_ON; 100 SSC_SHIFT = 1; 101 102 /* Obtain the argc / argv */ 103 for (i = 1; i < argc; i++) { 104 if (argv[i][0] == '-') { 105 switch (argv[i][1]) { 106 case 'D': 107 case 'd': 108 Temp = (char *)&argv[i][2]; 109 DBG_LEVEL = (int)(strtoul(Temp, NULL, 16)); 110 DBG_LEVEL |= DBG_ERR; /* Add must print. */ 111 printf("DBG_LEVEL change into 0x%x\n", DBG_LEVEL); 112 break; 113 case 'R': 114 case 'r': 115 Temp = (char *)&argv[i][2]; 116 I2C_PORT = (int)(strtoul(Temp, NULL, 16)); 117 printf("I2C_PORT change into 0x%x\n", I2C_PORT); 118 break; 119 default: 120 I2C_PORT = 0x0; 121 break; 122 } 123 } 124 } 125 126 printf("ASPEED DP Physical Layer Test Tool V %d.%d.%d\n", MAINVER, SUBVER, TEMPVER); 127 #ifdef INTERNAL 128 printf("Internal Version\n"); 129 #endif 130 131 printf("Build Date: %d.%d.%d\n\n", YEAR, MONTH, DAY); 132 133 printf("PLEASE REFER USER MANUAL BEFORE TEST!!\n\n"); 134 135 /* DP TX MCU reset */ 136 DPTX_MCU_Reset(); 137 printf("DP TX MCU Initial Done!\n"); 138 139 /* DP phy set */ 140 DPPHY_Set(); 141 printf("DP Physcial Config Done!\n"); 142 143 printf("Commands as below:\n"); 144 printf("0: Change SSC on/off\n"); 145 printf("1: Set data rate 1.62\n"); 146 printf("2: Set data rate 2.7\n"); 147 #ifdef INTERNAL 148 printf("3: DE_LVL = 1, DE_LVL_1 = 2\n"); 149 printf("4: DE_LVL = 0, DE_LVL_1 = 0\n"); 150 printf("5: DE_LVL = 2, DE_LVL_1 = 1\n"); 151 #endif 152 printf("!: Show configs\n\n"); 153 154 printf("TestItems as below:\n"); 155 printf("x: auto test\n"); 156 printf("a: PRBS7\n"); 157 printf("g: D10.2\n"); 158 printf("Press ESC key to leave test ...\n\n"); 159 160 // While for auto testing 161 while (1) { 162 if (tstc()) { 163 received = getc(); 164 165 /* printf("Press %d\n",received); */ 166 167 /* Set parameters path */ 168 if (received >= '1' && received <= '9') { 169 switch (received) { 170 /* Press "1" : Set DP_Rate as 1.62 */ 171 case '1': 172 DP_Rate = DP_RATE_1_62; 173 PRINT_RATE_1_62; 174 break; 175 /* Press "2" : Set DP_Rate as 2.701 */ 176 case '2': 177 DP_Rate = DP_RATE_2_70; 178 PRINT_RATE_2_70; 179 break; 180 /* Press "3" : Set DP_Rate as 5.40 */ 181 /* case '3': */ 182 /* DP_Rate = DP_RATE_5_40; */ 183 /* PRINT_RATE_5_40 */ 184 /* break; */ 185 #ifdef INTERNAL 186 /* Press "3" : Set Deemphasis_Level as 1 / Deemphasis_Level_1 as 2 */ 187 case '3': 188 Deemphasis_Level = DP_DEEMP_1; 189 Deemphasis_Level_1 = DP_DEEMP_2; 190 Deemphasis_Show = DP_DEEMP_0; 191 Deemphasis_RD = Deemphasis_Show; 192 PRINT_DEEMP_0; 193 break; 194 /* Press "4" : Set Deemphasis_Level as 0 / Deemphasis_Level_1 as 0 */ 195 case '4': 196 Deemphasis_Level = DP_DEEMP_0; 197 Deemphasis_Level_1 = DP_DEEMP_0; 198 Deemphasis_Show = DP_DEEMP_1; 199 Deemphasis_RD = Deemphasis_Show; 200 PRINT_DEEMP_1; 201 break; 202 /* Press "5" : Set Deemphasis_Level as 2 / Deemphasis_Level_1 as 1 */ 203 case '5': 204 Deemphasis_Level = DP_DEEMP_2; 205 Deemphasis_Level_1 = DP_DEEMP_1; 206 Deemphasis_Show = DP_DEEMP_2; 207 Deemphasis_RD = Deemphasis_Show; 208 PRINT_DEEMP_2; 209 break; 210 #endif 211 case '6': 212 SSC_SHIFT = 2; 213 break; 214 case '7': 215 SSC_SHIFT = 3; 216 break; 217 default: 218 break; 219 } 220 221 if (execute_test) 222 printf("The parameter is applied next measure!\n"); 223 224 } else if (received == '!') /* show config */ { 225 if (execute_test) 226 printf("Measurement is executed!\n"); 227 else 228 printf("Measurement is stopped!\n"); 229 230 DPPHYTX_Show_Cfg(); 231 } else if (received == '0') /* change sscfg */ { 232 if (SSCG == DP_SSCG_ON) { 233 SSCG = DP_SSCG_OFF; 234 PRINT_SSCG_OFF; 235 } else { 236 SSCG = DP_SSCG_ON; 237 PRINT_SSCG_ON; 238 } 239 240 /* SSCG could be applied without reset device. */ 241 if (execute_test) { 242 printf("Apply SSCG into current measurement !\n\n"); 243 TX_SSCG_Cfg = DP_TX_RDY_TEST; 244 /* TX_SSCG_Cfg |= SSCG; */ 245 TX_SSCG_Cfg |= DP_SSCG_ON; 246 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 247 } 248 } else { 249 /* Check the ESC key */ 250 if (received == 27) { 251 execute_test = 0; 252 DPTX_MCU_Reset(); 253 printf("'ESC' is pressed!\n"); 254 break; 255 } 256 257 /* If the test is execute, reset it */ 258 if (execute_test) { 259 execute_test = 0; 260 DPTX_MCU_Reset(); 261 262 printf("Stop current measurement !\n\n\n\n\n\n"); 263 } 264 265 /* Clear flag */ 266 flag = 0; 267 268 Current_Item = received; 269 270 switch (received) { 271 case 'a': 272 flag = (F_EMPHASIS_NULL | F_PAT_PRBS7); 273 break; 274 275 case 'g': /* D10.2 */ 276 flag = (F_EMPHASIS_1 | F_PAT_D10_2); 277 break; 278 279 #ifdef INTERNAL 280 case 'b': 281 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 282 break; 283 284 case 'c': 285 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT); 286 break; 287 288 case 'd': /* Non-Transition Voltage Range Measurement - PLTPAT */ 289 flag = (F_EMPHASIS | F_PAT_PLTPAT); 290 break; 291 292 case 'e': /* Pre-Emphasis Level Test and Pre-Emphasis Level Delta Test- PRBS7 */ 293 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 294 break; 295 296 case 'f': /* Non-Transition Voltage Range Measurement - PRBS7 */ 297 flag = (F_EMPHASIS | F_PAT_PRBS7); 298 break; 299 300 case 'h': 301 printf("Change the Swing value from request\n"); 302 flag = (F_EMPHASIS_1 | F_PAT_PRBS7 | F_SHOW_SWING); 303 break; 304 305 case 'i': 306 printf("Change the Swing value from request\n"); 307 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT | DP_TX_HIGH_SPEED | F_SHOW_SWING); 308 break; 309 310 case 'j': 311 flag = F_PAT_AUX; 312 break; 313 #endif 314 case 'x': /* Auto hand shaking with DPR-100 */ 315 flag = F_EXE_AUTO; 316 break; 317 318 default: 319 printf("Non - define command!\n"); 320 break; 321 } 322 323 // Execute testing 324 if (flag) { 325 execute_test = 1; 326 GFlag = flag; 327 328 if (flag & F_PAT_AUX) { 329 printf("######################################\n"); 330 printf("#Current DP TX setting is shown below#\n"); 331 printf("######################################\n\n"); 332 333 DPPHYTX_Show_Item(Current_Item); 334 Apply_AUX_Mesument(flag); 335 } else if (flag & F_EXE_AUTO) { 336 printf("#########################\n"); 337 printf("#Enter DP TX Auto Test!!#\n"); 338 printf("#########################\n\n"); 339 340 Apply_Auto_Preset(0x1); 341 Apply_Auto_Mesument(); 342 Apply_Auto_Preset(0x0); 343 344 printf("#########################\n"); 345 printf("#Leave DP TX Auto Test!!#\n"); 346 printf("#########################\n\n"); 347 } else { 348 DPPHYTX_Show_Cfg(); 349 Apply_Main_Mesument(flag); 350 } 351 } 352 } 353 } 354 mdelay(200); 355 }; 356 357 printf("\n\n"); 358 return 0; 359 } 360 361 /* Temp for cording here */ 362 void Apply_Auto_Preset(char Init) 363 { 364 /* Fill some nessary register value for auto test */ 365 if (Init) { 366 /* Enable MCU received interrupt */ 367 writel(0x00e80000, DP_TX_INT_CLEAR); 368 369 /* Set HPD irq time interval */ 370 writel(0x04e300fb, DP_TX_IRQ_CFG); 371 372 /* Set HPD event time interval */ 373 writel(0x000007d1, DP_TX_EVENT_CFG); 374 } else { 375 /* Recover */ 376 writel(0x0, DP_TX_INT_CLEAR); 377 writel(0x0, DP_TX_IRQ_CFG); 378 writel(0x0, DP_TX_EVENT_CFG); 379 } 380 } 381 382 /* READ EDID */ 383 void Read_EDID_128(char Offset) 384 { 385 char AUX_Data[16] = {0}; 386 uchar Length = 1; 387 uchar Status = 0; 388 uchar i, j; 389 390 DBG(DBG_A_EDID, "R EDID Offset %d\n", Offset); 391 392 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 393 394 AUX_Data[0] = Offset; 395 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 396 397 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 398 399 Length = 16; 400 401 // Read 128 bytes block 402 for (i = 0; i < 8; i++) { 403 do { 404 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 405 DBG(DBG_A_EDID, "EDID read %d!\n", i); 406 407 udelay(100); 408 } while (Status == 0x20); 409 410 /* copy from temp into EDID */ 411 for (j = 0; j < 16; j++) 412 EDID[Offset + i * 16 + j] = AUX_Data[j]; 413 } 414 415 Length = 1; 416 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 417 } 418 419 void Apply_EDID_Reading(void) 420 { 421 char AUX_Data[16] = {0}; 422 uchar Length = 1; 423 uchar Status = 0; 424 425 DBG(DBG_STAGE, "Apply EDID Reading!\n"); 426 427 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 428 429 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 430 431 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 432 433 /* Check read EDID header */ 434 Length = 4; 435 do { 436 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 437 438 udelay(100); 439 } while (Status == 0x20); 440 441 DBG(DBG_A_EDID, "EDID First 4 is 0x%X_0x%X_0x%X_0x%X\n", AUX_Data[0], AUX_Data[1], AUX_Data[2], AUX_Data[3]); 442 443 Length = 1; 444 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 445 446 DBG(DBG_A_EDID, "Read 128!\n"); 447 Read_EDID_128(0x0); 448 449 /* If the extension bit is set, then read back next block */ 450 if (EDID[0x7E] == 0x1) { 451 DBG(DBG_A_EDID, "Read 256!\n"); 452 Read_EDID_128(0x80); 453 } 454 } 455 456 /* LINK TRAIN */ 457 uchar Adjust_CR_EQ_Train(int TrainPat, uchar ADJStatus) 458 { 459 char AUX_Data[16] = {0}; 460 uchar Ret = 0; 461 uchar Length = 1; 462 uchar Status = 0; 463 uchar AUX_R_Level = 0; 464 uchar AUX_W_Level = 0; 465 uchar DE_Level = 0x0; 466 uchar CR_Status = 0; 467 int value = 0; 468 uchar bFirst = 1; 469 uchar tempkeep = 0; 470 471 /* Set the main link pattern with TPS1 / TPS2 for Lanex_CR_Done */ 472 value = ((readl(DP_TX_MAIN_PAT) & ~(0x30000000)) | TrainPat); 473 writel(value, DP_TX_MAIN_PAT); 474 DBG(DBG_A_SUB, "1.A_C_E Set Link Pattern\n"); 475 476 /* AST phy 0xE4 Bit28 (0x1000000) / DP 0x102 Bit0 : TPS1 */ 477 /* AST phy 0xE4 Bit29 (0x2000000) / DP 0x102 Bit1 : TPS2 */ 478 if (TrainPat == 0x10000000) 479 AUX_Data[0] = 0x21; 480 else 481 AUX_Data[0] = 0x22; 482 483 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 484 DBG(DBG_A_SUB, "2.A_C_E W 0x102 set 0x%x\n", AUX_Data[0]); 485 486 /* First */ 487 if (bFirst) { 488 Length = 4; 489 490 AUX_Data[0] = CR_EQ_Keep; 491 AUX_Data[1] = CR_EQ_Keep; 492 AUX_Data[2] = CR_EQ_Keep; 493 AUX_Data[3] = CR_EQ_Keep; 494 tempkeep = CR_EQ_Keep; 495 496 do { 497 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 498 DBG(DBG_A_SUB, "3.A_C_E W 0x103 - 0x106 set\n"); 499 } while (Status == 0x20); 500 501 Length = 6; 502 503 udelay(1200); 504 505 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 506 DBG(DBG_A_SUB, "4.A_C_E R 0x200 - 0x205 read back\n"); 507 508 if ((AUX_Data[2] & ADJStatus) == ADJStatus) { 509 CR_EQ_Keep = tempkeep; 510 return Ret; 511 } 512 513 bFirst = 0; 514 } 515 516 /* loop for CR_lock */ 517 do { 518 Length = 1; 519 520 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 521 DBG(DBG_A_SUB, "5.A_C_E R 0x206 read back\n"); 522 AUX_R_Level = AUX_Data[0]; 523 524 AUX_R(AUX_CMD_R, 0x207, (int *)(&AUX_Data), &Length, &Status); 525 DBG(DBG_A_SUB, "6.A_C_E R 0x207 read back\n"); 526 527 /* Update SW Level */ 528 switch (AUX_R_Level & 0x33) { 529 case 0x00: 530 AUX_W_Level = 00; 531 break; 532 case 0x11: 533 AUX_W_Level = 01; 534 break; 535 default: 536 AUX_W_Level = 06; 537 break; 538 } 539 540 /* Update SW Level */ 541 switch (AUX_R_Level & 0xCC) { 542 case 0x00: 543 /* AUX_W_Level |= 00; */ 544 DE_Level = 0; 545 break; 546 case 0x44: 547 AUX_W_Level |= 0x08; 548 DE_Level = 1; 549 break; 550 default: 551 AUX_W_Level |= 0x30; 552 DE_Level = 2; 553 break; 554 } 555 556 /* Set the de-emphsis value */ 557 value = ((readl(DP_TX_PHY_CFG) & ~(0x33000000)) | Deemlevel[DE_Level]); 558 writel(value, DP_TX_PHY_CFG); 559 DBG(DBG_A_SUB, "6.A_C_E Set Phy config %d\n", DE_Level); 560 561 DBG(DBG_A_SUB, "Link AUX_W_Level is 0x%x\n", AUX_W_Level); 562 563 Length = 4; 564 565 AUX_Data[0] = AUX_W_Level; 566 AUX_Data[1] = AUX_W_Level; 567 AUX_Data[2] = AUX_W_Level; 568 AUX_Data[3] = AUX_W_Level; 569 tempkeep = AUX_W_Level; 570 571 do { 572 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 573 DBG(DBG_A_SUB, "7.A_C_E W 0x103 - 0x106 set\n"); 574 } while (Status == 0x20); 575 576 udelay(1380); 577 578 Length = 6; 579 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 580 DBG(DBG_A_SUB, "8.A_C_E R 0x200 - 0x205 read back\n"); 581 582 CR_Status = AUX_Data[2] & ADJStatus; 583 584 /* Decrease speed because the deemphasis level reach max value */ 585 if (AUX_W_Level == 0x36) { 586 Ret = 1; 587 break; 588 } 589 590 } while (CR_Status != ADJStatus); 591 592 CR_EQ_Keep = tempkeep; 593 594 return Ret; 595 } 596 597 uchar Link_Train_Flow(char Link_Level) 598 { 599 char AUX_Data[16] = {0}; 600 uchar Length = 1; 601 uchar Status = 0; 602 uchar Ret = 0; 603 int value = 0; 604 605 DBG(DBG_STAGE, "Link train flow! Level : %d\n", Link_Level); 606 607 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 608 DBG(DBG_A_SUB, "1.Link R 0x101 read back\n"); 609 610 /* Normal / Test case */ 611 if (Auto_Lane_Count) 612 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 613 else 614 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 615 616 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 617 DBG(DBG_A_SUB, "2.Link W 0x101 clear\n"); 618 619 /* Set different clock bit rate */ 620 value = ((readl(DP_TX_MAIN_SET) & ~(0x300)) | (Link_Level << 8)); 621 writel(value, DP_TX_MAIN_SET); 622 623 switch (Link_Level) { 624 case 0x1: /* 2.7 */ 625 AUX_Data[0] = 0x0a; 626 break; 627 628 default: /* 1.62 */ 629 AUX_Data[0] = 0x06; 630 break; 631 } 632 633 AUX_W(AUX_CMD_W, 0x100, (int *)(&AUX_Data), &Length, &Status); 634 DBG(DBG_A_SUB, "3.Link W 0x100 set\n"); 635 636 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 637 DBG(DBG_A_SUB, "4.Link R 0x101 read back\n"); 638 639 /* Normal / Test case */ 640 if (Auto_Lane_Count) 641 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 642 else 643 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 644 645 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 646 DBG(DBG_A_SUB, "5.Link W 0x101 clear\n"); 647 648 /* Set the 2 lanes and enhance frame by checking AUX 0x2 bit 7 */ 649 value = ((readl(DP_TX_MAIN_SET) & ~(0x1070)) | 0x20); 650 651 if (bEn_Frame) 652 value |= 0x1000; 653 654 writel(value, DP_TX_MAIN_SET); 655 656 value = ((readl(DP_TX_PHY_CFG) & ~(0x3000)) | 0x3000); 657 658 writel(value, DP_TX_PHY_CFG); 659 660 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 661 DBG(DBG_A_SUB, "6.Link R 0x101 read back\n"); 662 663 /* Normal / Test case */ 664 if (Auto_Lane_Count) 665 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 666 else 667 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 668 669 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 670 DBG(DBG_A_SUB, "7.Link W 0x101 clear\n"); 671 672 /* Set the main link control on */ 673 value = ((readl(DP_TX_PHY_SET) & ~(0x100)) | 0x100); 674 675 udelay(1000); 676 udelay(1500); 677 678 writel(value, DP_TX_PHY_SET); 679 680 do { 681 value = (readl(DP_TX_PHY_SET) & 0x200); 682 } while (value != 0x200); 683 DBG(DBG_A_SUB, "8.Link Main Link Ready\n"); 684 685 /* Adjust for CR */ 686 if (Adjust_CR_EQ_Train(0x10000000, 0x11)) { 687 Ret = 1; 688 return Ret; 689 } 690 691 /* Adjust for EQ */ 692 if (Adjust_CR_EQ_Train(0x20000000, 0x77)) { 693 Ret = 1; 694 return Ret; 695 } 696 697 return Ret; 698 } 699 700 void Apply_HPD_Normal(void) 701 { 702 char AUX_Data[16] = {0}; 703 uchar Length = 1; 704 uchar Status = 0; 705 int value = 0; 706 707 DBG(DBG_STAGE, "HPD Normal set!\n"); 708 709 AUX_Data[0] = 0x01; 710 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 711 DBG(DBG_NOR, "1.HPD_N W 0x600 set power!\n"); 712 713 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 714 DBG(DBG_NOR, "2.HPD_N R 0x0 read back is 0x%X!\n", AUX_Data[0]); 715 716 Length = 8; 717 AUX_R(AUX_CMD_R, 0x500, (int *)(&AUX_Data), &Length, &Status); 718 DBG(DBG_NOR, "3.HPD_N R 0x500 - 0x508 read back\n"); 719 720 Length = 14; 721 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 722 DBG(DBG_NOR, "4.HPD_N R 0x0 - 0xD read back\n"); 723 724 bEn_Frame = AUX_Data[2] & 0x80; 725 Link_Aux_RD_Val = AUX_Data[14]; 726 727 if (bEn_Frame) 728 DBG(DBG_NOR, "4.HPD_N R 0x2 En_Frame_Cap\n"); 729 730 Length = 1; 731 AUX_R(AUX_CMD_R, 0xe, (int *)(&AUX_Data), &Length, &Status); 732 DBG(DBG_NOR, "5.HPD_N R 0xE read back\n"); 733 734 /* Read EDID */ 735 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Enter\n"); 736 737 Apply_EDID_Reading(); 738 739 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Leave\n"); 740 741 Length = 2; 742 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 743 DBG(DBG_NOR, "7.HPD_N R 0x200 - 0x201 read back.\n"); 744 745 Length = 1; 746 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 747 DBG(DBG_NOR, "8.HPD_N R 0x68028 read back.\n"); 748 749 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 750 DBG(DBG_NOR, "9.HPD_N R 0x68028 read back.\n"); 751 752 AUX_R(AUX_CMD_R, 0x600, (int *)(&AUX_Data), &Length, &Status); 753 DBG(DBG_NOR, "10.HPD_N R 0x600 read back.\n"); 754 755 AUX_Data[0] = 0x01; 756 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 757 DBG(DBG_NOR, "11.HPD_N W 0x600 set power!\n"); 758 759 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Enter\n"); 760 761 Status = Link_Train_Flow(0x1); 762 763 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Leave\n"); 764 765 if (Status) { 766 AUX_Data[0] = 0x20; 767 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 768 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x1 Fail!!\n"); 769 770 DBG(DBG_NOR, "13.HPD_N Link_Train_Flow 0x0 Enter\n"); 771 772 Status = Link_Train_Flow(0x0); 773 774 DBG(DBG_NOR, "13.HPD_NLink_Train_Flow 0x0 Leave\n"); 775 776 if (Status) { 777 AUX_Data[0] = 0x20; 778 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 779 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x0 Fail!!\n"); 780 781 DBG(DBG_ERR, "### CAUTION!! LINK TRAN FAIL!! ###\n"); 782 783 return; 784 } 785 } 786 787 /* Link successful */ 788 AUX_Data[0] = 0x00; 789 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 790 DBG(DBG_NOR, "14.HPD_N W 0x102 clear!\n"); 791 792 /* Fill idle pattern */ 793 value = ((readl(DP_TX_MAIN_PAT) & ~(0x31000000)) | 0x01000000); 794 writel(value, DP_TX_MAIN_PAT); 795 DBG(DBG_NOR, "15.HPD_N Fill idle pattern!\n"); 796 797 Length = 1; 798 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 799 DBG(DBG_NOR, "16.HPD_N R 0x68028 read back.\n"); 800 801 Length = 5; 802 AUX_R(AUX_CMD_R, 0x68000, (int *)(&AUX_Data), &Length, &Status); 803 DBG(DBG_NOR, "17.HPD_N R 0x68000 - 0x68004 read back.\n"); 804 805 Length = 1; 806 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 807 DBG(DBG_NOR, "18.HPD_N R 0x68028 read back.\n"); 808 809 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 810 DBG(DBG_NOR, "19.HPD_N R 0x68028 read back.\n"); 811 812 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 813 DBG(DBG_NOR, "20.HPD_N R 0x0 read back.\n"); 814 } 815 816 void Apply_HPD_Auto_Test(void) 817 { 818 char AUX_Data[16]; 819 uchar Length = 0; 820 uchar Status = 0; 821 uchar clear_auto_test = 0; 822 uchar auto_test_link = 0; 823 uchar auto_test_phy = 0; 824 uchar swing0 = 0, preemphasis0 = 0; 825 uchar swing1 = 0, preemphasis1 = 0; 826 int flag = 0; 827 char temp0 = 0, temp1 = 0; 828 char temp206 = 0; 829 830 DBG(DBG_STAGE, "HPD Auto test set!\n"); 831 832 /* Set power D0 */ 833 AUX_Data[0] = 0x01; 834 Length = 1; 835 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 836 DBG(DBG_A_TEST, "1.HP_I W 0x600 done!\n"); 837 838 Length = 6; 839 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 840 DBG(DBG_A_TEST, "2.HP_I R 0x200 - 0x206 done!\n"); 841 842 Length = 1; 843 AUX_R(AUX_CMD_R, 0x201, (int *)(&AUX_Data), &Length, &Status); 844 DBG(DBG_A_TEST, "3.HP_I R 0x201 : 0x%x\n", AUX_Data[0]); 845 846 /* Obtain auto test */ 847 if (AUX_Data[0] & 0x2) 848 clear_auto_test = 1; 849 else 850 clear_auto_test = 0; 851 852 /* Read dummy */ 853 Length = 3; 854 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 855 Length = 1; 856 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 857 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 858 Length = 3; 859 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 860 Length = 1; 861 AUX_R(AUX_CMD_R, 0x205, (int *)(&AUX_Data), &Length, &Status); 862 DBG(DBG_A_TEST, "4. HP_I R Dummy!\n"); 863 864 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 865 DBG(DBG_A_TEST, "5. HP_I Link Rate R 0x219 : 0x%x\n", AUX_Data[0]); 866 867 if (AUX_Data[0] == 0x06) { 868 Auto_Link_Rate = AUX_Data[0]; 869 DP_Rate = DP_RATE_1_62; 870 PRINT_RATE_1_62; 871 } else if (AUX_Data[0] == 0x0a) { 872 Auto_Link_Rate = AUX_Data[0]; 873 DP_Rate = DP_RATE_2_70; 874 PRINT_RATE_2_70; 875 } else if (AUX_Data[0] == 0x14) { 876 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 877 return; 878 } 879 880 if (clear_auto_test) { 881 AUX_Data[0] = 0x02; 882 AUX_W(AUX_CMD_W, 0x201, (int *)(&AUX_Data), &Length, &Status); 883 DBG(DBG_A_TEST, "1.HP_I CA W 0x201 clear auto!\n"); 884 clear_auto_test = 0; 885 886 /* Fetch Testing data */ 887 AUX_R(AUX_CMD_R, 0x218, (int *)(&AUX_Data), &Length, &Status); 888 DBG(DBG_A_TEST, "2.HP_I CA R 0x218 : 0x%x\n", AUX_Data[0]); 889 890 /* Check auto test link flag */ 891 if (AUX_Data[0] & 0x1) 892 auto_test_link = 1; 893 else 894 auto_test_link = 0; 895 896 /* Check auto test phy flag */ 897 if (AUX_Data[0] & 0x8) 898 auto_test_phy = 1; 899 else 900 auto_test_phy = 0; 901 DBG(DBG_A_TEST, "auto test link(%d) phy(%d)\n", auto_test_link, auto_test_phy); 902 903 if (auto_test_link) { 904 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 905 DBG(DBG_A_TEST, "1.HP_I TL R 0x219 : 0x%x\n", AUX_Data[0]); 906 907 if (AUX_Data[0] == 0x06) { 908 Auto_Link_Rate = AUX_Data[0]; 909 DP_Rate = DP_RATE_1_62; 910 PRINT_RATE_1_62; 911 } else if (AUX_Data[0] == 0x0a) { 912 Auto_Link_Rate = AUX_Data[0]; 913 DP_Rate = DP_RATE_2_70; 914 PRINT_RATE_2_70; 915 } else if (AUX_Data[0] == 0x14) { 916 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 917 return; 918 } 919 920 AUX_R(AUX_CMD_R, 0x220, (int *)(&AUX_Data), &Length, &Status); 921 DBG(DBG_A_TEST, "2.HP_I TL R 0x220 : 0x%x\n", AUX_Data[0]); 922 Auto_Lane_Count = AUX_Data[0] & 0x1F; 923 924 AUX_Data[0] = 0x01; 925 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 926 DBG(DBG_A_TEST, "3.HP_I TL W 0x260 test ACK\n"); 927 928 mdelay(95); 929 930 /* Set power D0 */ 931 AUX_Data[0] = 0x01; 932 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 933 DBG(DBG_A_TEST, "3.1 HP_I W 0x600 done!\n"); 934 935 switch (Auto_Link_Rate) { 936 case 0x06: 937 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Enter\n"); 938 Status = Link_Train_Flow(0x0); 939 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Leave\n"); 940 break; 941 942 case 0x0a: 943 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Enter\n"); 944 Status = Link_Train_Flow(0x1); 945 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Leave\n"); 946 break; 947 948 default: 949 DBG(DBG_ERR, "!!BAD LINK RATE!!\n"); 950 return; 951 } 952 953 if (Status) { 954 DBG(DBG_ERR, "!!AUTO TEST LINK FAIL!!\n"); 955 return; 956 } 957 958 /* Link successful */ 959 AUX_Data[0] = 0x00; 960 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 961 DBG(DBG_A_TEST, "5.HP_I TL Link clear!\n"); 962 963 auto_test_link = 0; 964 } 965 966 if (auto_test_phy) { 967 Length = 1; 968 flag = 0; 969 temp206 = 0; 970 971 AUX_R(AUX_CMD_R, 0x248, (int *)(&AUX_Data), &Length, &Status); 972 DBG(DBG_A_TEST, "1.HP_I TP R 0x248 : 0x%x!\n", AUX_Data[0]); 973 974 if (AUX_Data[0] == 0x01) { 975 flag |= F_PAT_D10_2; 976 DBG(DBG_A_TEST, "HP_I TP D10.2!\n"); 977 } else if (AUX_Data[0] == 0x03) { 978 flag |= F_PAT_PRBS7; 979 DBG(DBG_A_TEST, "HP_I TP PRBS7!\n"); 980 } 981 982 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 983 DBG(DBG_A_TEST, "2.HP_I TP R 0x206 : 0x%x!\n", AUX_Data[0]); 984 985 /* Temp for verified */ 986 DBG(DBG_INF, "Read value 0x206 : 0x%x!\n", AUX_Data[0]); 987 988 /* Check Swing */ 989 temp0 = (AUX_Data[0] & 0x03); 990 temp1 = (AUX_Data[0] & 0x30); 991 992 /* Check Swing0 */ 993 switch (temp0) { 994 case 0x2: 995 swing0 = 0x2; 996 temp206 |= 6; 997 break; 998 case 0x1: 999 swing0 = 0x1; 1000 temp206 |= 1; 1001 break; 1002 case 0x0: 1003 swing0 = 0x0; 1004 break; 1005 default: 1006 DBG(DBG_ERR, "HP_I TP 0x206 other swing0 val %x!\n", temp0); 1007 break; 1008 } 1009 1010 /* Check Swing1 */ 1011 switch (temp1) { 1012 case 0x20: 1013 swing1 = 0x2; 1014 temp206 |= 6; 1015 break; 1016 case 0x10: 1017 swing1 = 0x1; 1018 temp206 |= 1; 1019 break; 1020 case 0x00: 1021 swing1 = 0x0; 1022 break; 1023 default: 1024 DBG(DBG_ERR, "HP_I TP 0x206 other swing1 val %x!\n", temp1); 1025 break; 1026 } 1027 1028 if (swing0 != swing1) 1029 DBG(DBG_ERR, "Swing 0 / 1 diff val %x!\n", AUX_Data[0]); 1030 1031 /* Check Pre-emphasis */ 1032 temp0 = (AUX_Data[0] & 0x0C); 1033 temp1 = (AUX_Data[0] & 0xC0); 1034 1035 /* Check Pre-emphasis0 */ 1036 switch (temp0) { 1037 case 0x8: 1038 preemphasis0 = 0x2; 1039 temp206 |= 0x30; 1040 break; 1041 case 0x4: 1042 preemphasis0 = 0x1; 1043 temp206 |= 0x08; 1044 break; 1045 case 0x0: 1046 preemphasis0 = 0x0; 1047 break; 1048 default: 1049 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis0 val %x!\n", temp0); 1050 break; 1051 } 1052 1053 /* Check Pre-emphasis1 */ 1054 switch (temp1) { 1055 case 0x80: 1056 preemphasis1 = 0x2; 1057 temp206 |= 0x30; 1058 break; 1059 case 0x40: 1060 preemphasis1 = 0x1; 1061 temp206 |= 0x08; 1062 break; 1063 case 0x00: 1064 preemphasis1 = 0x0; 1065 break; 1066 default: 1067 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis1 val %x!\n", temp1); 1068 break; 1069 } 1070 1071 if (preemphasis0 != preemphasis1) 1072 DBG(DBG_ERR, "Preemphasis 0 / 1 diff val %x!\n", AUX_Data[0]); 1073 1074 /* Judgement */ 1075 if (swing0 == 0x2 || swing1 == 0x2) 1076 Swing_Level = 0x2; 1077 else if (swing0 == 1 || swing1 == 0x1) 1078 Swing_Level = 0x1; 1079 else if (swing0 == 0x0 || swing1 == 0x0) 1080 Swing_Level = 0x0; 1081 1082 if (preemphasis0 == 0x2 || preemphasis1 == 0x2) { 1083 Deemphasis_RD = DP_DEEMP_2; 1084 Deemphasis_Level_1 = DP_DEEMP_1; 1085 DBG(DBG_ERR, "!!De-type 1 P_2 !!\n"); 1086 } else if (preemphasis0 == 0x1 || preemphasis1 == 0x1) { 1087 Deemphasis_RD = DP_DEEMP_1; 1088 Deemphasis_Level_1 = DP_DEEMP_0; 1089 DBG(DBG_ERR, "!!De-type 0 P_1 !!\n"); 1090 } else if (preemphasis0 == 0x0 || preemphasis1 == 0x0) { 1091 Deemphasis_RD = DP_DEEMP_0; 1092 Deemphasis_Level_1 = DP_DEEMP_2; 1093 DBG(DBG_ERR, "!!De-type 2 P_0 !!\n"); 1094 } 1095 1096 DBG(DBG_INF, "!!Swing %d / Pre-emphasis %d !!\n", swing0, preemphasis0); 1097 1098 flag |= F_EMPHASIS_1; 1099 1100 AUX_R(AUX_CMD_R, 0x102, (int *)(&AUX_Data), &Length, &Status); 1101 DBG(DBG_A_TEST, "3.HP_I TP R 0x102 : 0x%x\n", AUX_Data[0]); 1102 temp0 = AUX_Data[0]; 1103 1104 Length = 2; 1105 AUX_R(AUX_CMD_R, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1106 DBG(DBG_A_TEST, "4.HP_I TP R 0x10b : 0x%x\n", AUX_Data[0]); 1107 1108 AUX_W(AUX_CMD_W, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1109 DBG(DBG_A_TEST, "5.HP_I TP W 0x10b done!\n"); 1110 1111 AUX_Data[0] = temp0 | 0x20; 1112 Length = 1; 1113 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 1114 DBG(DBG_A_TEST, "6.HP_I TP W 0x102 done!\n"); 1115 1116 AUX_Data[0] = temp206; 1117 AUX_Data[1] = temp206; 1118 Length = 2; 1119 1120 do { 1121 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 1122 DBG(DBG_A_TEST, "7.HP_I TP W 0x103 - 0x104 done!\n"); 1123 } while (Status == 0x20); 1124 1125 DPPHYTX_Show_Cfg(); 1126 Apply_Main_Mesument(flag); 1127 1128 Length = 1; 1129 AUX_Data[0] = 0x01; 1130 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 1131 DBG(DBG_A_TEST, "8.HP_I TP W 0x260 done!\n"); 1132 1133 DBG(DBG_STAGE, "Leave Apply Auto Test\n"); 1134 1135 auto_test_phy = 0; 1136 } 1137 clear_auto_test = 0; 1138 } 1139 } 1140 1141 /* TEST SECTION */ 1142 void Apply_Auto_Mesument(void) 1143 { 1144 char auto_received = 0; 1145 int temp = 0, wdata = 0; 1146 int breakcount = 0; 1147 1148 while (1) { 1149 breakcount = 0; 1150 1151 /* Wait HPD */ 1152 do { 1153 temp = (readl(DP_TX_INT_STATUS) & 0x3800); 1154 breakcount++; 1155 1156 if (breakcount == 0x96000) { 1157 /* A simple break for esc press received */ 1158 break; 1159 } 1160 1161 } while (!(temp & 0x3800)); 1162 1163 if (temp) { 1164 /* Clear AUX write interrupt status */ 1165 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1166 writel(wdata, DP_TX_INT_CLEAR); 1167 } 1168 1169 /* Interrupt occur */ 1170 if (temp & 0x2800) { 1171 /* Initial global parameter */ 1172 Auto_Link_Rate = 0; 1173 Auto_Lane_Count = 0; 1174 bEn_Frame = 0; 1175 CR_EQ_Keep = 0; 1176 1177 if (temp & 0x2000) { 1178 printf("DP HPD irq is detected!\n"); 1179 Apply_HPD_Normal(); 1180 } 1181 1182 if (temp & 0x800) { 1183 printf("DP HPD event is detected!\n"); 1184 Apply_HPD_Auto_Test(); 1185 } 1186 } 1187 1188 /* Leave auto test if the 'ESC' is pressed */ 1189 if (tstc()) { 1190 auto_received = getc(); 1191 1192 /* Check the ESC key */ 1193 if (auto_received == 27) { 1194 printf("'ESC' is pressed under auto test!\n\n"); 1195 return; 1196 } 1197 1198 printf("DP TX auto test is executed!\n"); 1199 } 1200 } 1201 } 1202 1203 void Apply_Main_Mesument(int flag) 1204 { 1205 DPTX_MCU_Reset(); 1206 1207 /* Emphasis setting */ 1208 if (flag & F_EMPHASIS_NULL) 1209 writel(PHY_Cfg_N, DP_TX_PHY_CFG); 1210 else if (flag & F_EMPHASIS) 1211 writel(PHY_Cfg, DP_TX_PHY_CFG); 1212 else if (flag & F_EMPHASIS_1) 1213 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1214 1215 if (flag & F_RES_HIGH) 1216 writel(DP_TX_HIGH_SPEED, DP_TX_RES_CFG); 1217 else 1218 writel(DP_TX_NOR_SPEED, DP_TX_RES_CFG); 1219 1220 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1221 1222 DPPHY_Set(); 1223 1224 if (flag & F_PAT_PRBS7) 1225 Set_PRBS7(); 1226 else if (flag & F_PAT_PLTPAT) 1227 Set_PLTPAT(); 1228 else if (flag & F_PAT_HBR2CPAT) 1229 Set_HBR2CPAT(); 1230 else if (flag & F_PAT_D10_2) 1231 Set_D10_1(); 1232 1233 /* ssc special patch */ 1234 if (flag & F_PAT_D10_2) { 1235 /*Apply special patch*/ 1236 writel(SSC_SHIFT << 10, DP_TX_RES_CFG); 1237 TX_SSCG_Cfg |= DP_SSCG_ON; 1238 } else { 1239 /*Recover into original setting*/ 1240 writel(0x00000000, DP_TX_RES_CFG); 1241 } 1242 1243 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 1244 } 1245 1246 void Apply_AUX_Mesument(int flag) 1247 { 1248 DPTX_MCU_Reset(); 1249 DPPHY_Set(); 1250 1251 writel(0x0F000000, DP_AUX_ADDR_LEN); 1252 writel(0x80000010, DP_AUX_REQ_CFG); 1253 } 1254 1255 /* FUNCTION SECTION */ 1256 /* i2c set */ 1257 #ifdef RE_DRIVER 1258 void Set_Redriver(void) 1259 { 1260 int value = 0x0; 1261 uchar offset = 0x0; 1262 uchar *set_table = &set_table0; 1263 1264 if (Deemphasis_RD == DP_DEEMP_1) 1265 set_table = &set_table1; 1266 else if (Deemphasis_RD == DP_DEEMP_2) 1267 set_table = &set_table2; 1268 1269 RD_VAL = set_table[Swing_Level]; 1270 1271 printf("RD_VAL is 0x%x\n", RD_VAL); 1272 1273 writel(0x600, I2C_BASE + I2C0_COUNT_O); 1274 value = (0x0000f0f0 | (RD_VAL << 24)); 1275 writel(value, I2C_BUFF); 1276 printf("value0 is 0x%x\n", value); 1277 value = (RD_VAL | (RD_VAL << 8) | (RD_VAL << 16) | (RD_VAL << 24)); 1278 writel(value, (I2C_BUFF + 0x4)); 1279 printf("value1 is 0x%x\n", value); 1280 writel(0x70010063, (I2C_BASE + I2C0_EXECUTE_O)); 1281 mdelay(1000); 1282 } 1283 1284 /* i2c single initial */ 1285 void I2C_L_Initial(void) 1286 { 1287 I2C_BASE = (I2C0_BASE + (I2C_DEV_OFFSET * I2C_PORT)); 1288 I2C_BUFF = (I2C0_BUFF + (I2C_BUFF_OFFSET * I2C_PORT)); 1289 1290 writel(0x0, I2C_BASE); 1291 mdelay(1); 1292 writel(0x28001, I2C_BASE); 1293 writel(0x344001, I2C_BASE + I2C0_TIMMING_O); 1294 writel(0xFFFFFFFF, I2C_BASE + I2C0_INT_STATUS_O); 1295 writel(0x0, I2C_BASE + I2C0_INT_O); 1296 mdelay(10); 1297 } 1298 1299 /* i2c golbal iniitial */ 1300 void I2C_G_Initial(void) 1301 { 1302 /* i2c multi-function */ 1303 writel(0x0FFF3000, MP_SCU410); 1304 writel(0x0F00FF00, MP_SCU414); 1305 writel(0xCFFF001F, MP_SCU418); 1306 writel(0xF00000FF, MP_SCU4b0); 1307 writel(0xF0FF00FF, MP_SCU4b4); 1308 writel(0x0000FF00, MP_SCU4b8); 1309 1310 /* I2c control */ 1311 writel(0x16, (I2C_GBASE + 0xC)); 1312 writel(0x041230C6, (I2C_GBASE + 0x10)); 1313 1314 mdelay(1000); 1315 } 1316 #endif 1317 1318 void DPTX_MCU_Reset(void) 1319 { 1320 /* Reset DPMCU & Release DPTX */ 1321 writel(0x20000000, SYS_REST); 1322 writel(0x10000000, SYS_REST_CLR); 1323 1324 /* Wait for apply setting */ 1325 mdelay(1000); 1326 } 1327 1328 void DPPHY_Set(void) 1329 { 1330 int value = 0, count = 0; 1331 1332 /* Clear power on reset */ 1333 writel(0x10000000, DP_TX_PHY_SET); 1334 mdelay(1); 1335 1336 /* Clear DPTX reset */ 1337 writel(0x11000000, DP_TX_PHY_SET); 1338 mdelay(1); 1339 1340 /* Turn on Main link / Aux channel */ 1341 writel(0x11001100, DP_TX_PHY_SET); 1342 mdelay(1); 1343 1344 while (value != DP_TX_RDY_TEST) { 1345 value = readl(DP_TX_PHY_SET); 1346 mdelay(1); 1347 count++; 1348 } 1349 } 1350 1351 char DPPHYTX_Show_Cfg(void) 1352 { 1353 char SetFail = 0; 1354 1355 PHY_Cfg = DP_PHY_INIT_CFG; 1356 PHY_Cfg_1 = DP_PHY_INIT_CFG; 1357 TX_SSCG_Cfg = DP_TX_RDY_TEST; 1358 1359 /* Show the setting */ 1360 1361 printf("######################################\n"); 1362 printf("#Current DP TX setting is shown below#\n"); 1363 printf("######################################\n\n"); 1364 1365 DPPHYTX_Show_Item(Current_Item); 1366 1367 switch (DP_Rate) { 1368 case DP_RATE_1_62: 1369 PRINT_RATE_1_62; 1370 break; 1371 1372 case DP_RATE_2_70: 1373 PRINT_RATE_2_70; 1374 break; 1375 1376 case DP_RATE_5_40: 1377 PRINT_RATE_5_40; 1378 break; 1379 1380 default: 1381 PRINT_INVALID; 1382 printf("DP Rate\n"); 1383 SetFail = 1; 1384 break; 1385 } 1386 1387 switch (Deemphasis_Show) { 1388 case DP_DEEMP_0: 1389 if (GFlag & F_SHOW_SWING) 1390 PRINT_SWING_0; 1391 else 1392 PRINT_EMPVAL_0; 1393 break; 1394 1395 case DP_DEEMP_1: 1396 if (GFlag & F_SHOW_SWING) 1397 PRINT_SWING_1; 1398 else 1399 PRINT_EMPVAL_1; 1400 break; 1401 1402 case DP_DEEMP_2: 1403 if (GFlag & F_SHOW_SWING) 1404 PRINT_SWING_2; 1405 else 1406 PRINT_EMPVAL_2; 1407 break; 1408 1409 default: 1410 PRINT_INVALID; 1411 printf("Deemphasis Level\n"); 1412 SetFail = 1; 1413 break; 1414 } 1415 1416 switch (Swing_Level) { 1417 case 0: 1418 PRINT_SWING_0; 1419 break; 1420 1421 case 1: 1422 PRINT_SWING_1; 1423 break; 1424 1425 case 2: 1426 PRINT_SWING_2; 1427 break; 1428 1429 default: 1430 PRINT_INVALID; 1431 printf("Swing Level\n"); 1432 SetFail = 1; 1433 break; 1434 } 1435 1436 PHY_Cfg = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level); 1437 PHY_Cfg_1 = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level_1); 1438 PHY_Cfg_N = DP_PHY_INIT_CFG | (DP_Rate | DP_DEEMP_2); 1439 1440 switch (SSCG) { 1441 case DP_SSCG_ON: 1442 /*PRINT_SSCG_ON;*/ 1443 break; 1444 1445 case DP_SSCG_OFF: 1446 /*PRINT_SSCG_OFF;*/ 1447 break; 1448 1449 default: 1450 PRINT_INVALID; 1451 printf("SSCG\n"); 1452 SetFail = 1; 1453 break; 1454 } 1455 /* TX_SSCG_Cfg |= SSCG; */ 1456 TX_SSCG_Cfg |= DP_SSCG_ON; 1457 1458 printf("\n"); 1459 1460 return SetFail; 1461 } 1462 1463 void DPPHYTX_Show_Item(char received) 1464 { 1465 switch (received) { 1466 case 'a': 1467 PRINT_ITEM_A; 1468 break; 1469 1470 case 'b': 1471 PRINT_ITEM_B; 1472 break; 1473 1474 case 'c': 1475 PRINT_ITEM_C; 1476 break; 1477 1478 case 'd': 1479 PRINT_ITEM_D; 1480 break; 1481 1482 case 'e': 1483 PRINT_ITEM_E; 1484 break; 1485 1486 case 'f': 1487 PRINT_ITEM_F; 1488 break; 1489 1490 case 'g': 1491 PRINT_ITEM_G; 1492 break; 1493 1494 case 'h': 1495 PRINT_ITEM_H; 1496 break; 1497 1498 case 'i': 1499 PRINT_ITEM_I; 1500 break; 1501 1502 case 'j': 1503 PRINT_ITEM_J; 1504 break; 1505 1506 case 'x': 1507 PRINT_ITEM_X; 1508 break; 1509 1510 default: 1511 break; 1512 } 1513 1514 printf("\n"); 1515 } 1516 1517 void Set_PRBS7(void) 1518 { 1519 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1520 writel((DP_PY_PAT | DP_PY_PAT_PRB7), DP_TX_PHY_PAT); 1521 } 1522 1523 void Set_HBR2CPAT(void) 1524 { 1525 int value = 0, count = 0; 1526 1527 writel(DP_TX_MAIN_ADV, DP_TX_MAIN_SET); 1528 1529 writel(DP_TX_PAT_HBR2, DP_TX_MAIN_PAT); 1530 writel((DP_PY_PAT | DP_PY_PAT_SCRB), DP_TX_PHY_PAT); 1531 1532 writel(DP_TX_MAIN_TRA, DP_TX_MAIN_CFG); 1533 mdelay(1); 1534 1535 while (value != DP_TX_RDY_25201) { 1536 value = (readl(DP_TX_MAIN_CFG) & 0xFFF); 1537 mdelay(1); 1538 count++; 1539 } 1540 1541 /* Reset for signal apply */ 1542 writel((DP_TX_MAIN_ADV | DP_TX_PY_RESET), DP_TX_MAIN_SET); 1543 } 1544 1545 void Set_PLTPAT(void) 1546 { 1547 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1548 1549 writel(DP_TX_PLTPAT_0, DP_TX_CUS_PAT_0); 1550 writel(DP_TX_PLTPAT_1, DP_TX_CUS_PAT_1); 1551 writel(DP_TX_PLTPAT_2, DP_TX_CUS_PAT_2); 1552 1553 writel((DP_PY_PAT | DP_PY_PAT_CUS), DP_TX_PHY_PAT); 1554 } 1555 1556 void Set_D10_1(void) 1557 { 1558 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1559 1560 writel(DP_TX_PAT_TPS1, DP_TX_MAIN_PAT); 1561 writel(DP_PY_PAT, DP_TX_PHY_PAT); 1562 } 1563 1564 uchar AUX_R(int aux_cmd, int aux_addr, int *aux_r_data, uchar *length, uchar *status) 1565 { 1566 int wdata = 0, temp = 0; 1567 uchar len = *length; 1568 1569 /* Check valid length */ 1570 if (len >= 1) 1571 len -= 1; 1572 else 1573 return 1; 1574 1575 /* Prepare AUX write address and data */ 1576 wdata = (int)((len << 24) | aux_addr); 1577 writel(wdata, DP_AUX_ADDR_LEN); 1578 1579 DBG(DBG_AUX_R, "AUX Read on 0x%x with %d bytes.\n", aux_addr, *length); 1580 1581 /* Fire AUX read */ 1582 writel(aux_cmd, DP_AUX_REQ_CFG); 1583 1584 /* Wait AUX read finish or timeout */ 1585 do { 1586 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1587 } while (!(temp & 0xC000)); 1588 1589 /* Clear AUX write interrupt status */ 1590 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1591 writel(wdata, DP_TX_INT_CLEAR); 1592 1593 if (temp & AUX_CMD_DONE) { 1594 /* Read back data count */ 1595 *aux_r_data = readl(DP_AUX_R_D_0); 1596 1597 DBG(DBG_AUX_R, "Data on 0x0 is 0x%x.\n", *aux_r_data); 1598 1599 if ((*length) > 0x4) { 1600 aux_r_data++; 1601 *aux_r_data = readl(DP_AUX_R_D_4); 1602 DBG(DBG_AUX_R, "Data on 0x4 is 0x%x.\n", *aux_r_data); 1603 } 1604 1605 if ((*length) > 0x8) { 1606 aux_r_data++; 1607 *aux_r_data = readl(DP_AUX_R_D_8); 1608 DBG(DBG_AUX_R, "Data on 0x8 is 0x%x.\n", *aux_r_data); 1609 } 1610 1611 if ((*length) > 0xC) { 1612 aux_r_data++; 1613 *aux_r_data = readl(DP_AUX_R_D_C); 1614 DBG(DBG_AUX_R, "Data on 0xC is 0x%x.\n", *aux_r_data); 1615 } 1616 1617 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1618 return 0; 1619 } else { 1620 return 1; 1621 } 1622 } 1623 1624 uchar AUX_W(int aux_cmd, int aux_addr, int *aux_w_data, uchar *length, uchar *status) 1625 { 1626 int wdata = 0, temp = 0; 1627 uchar len = *length; 1628 1629 /* Check valid length */ 1630 if (len >= 1) 1631 len -= 1; 1632 else 1633 return 1; 1634 1635 /* Prepare AUX write address and data */ 1636 wdata = (int)((len << 24) | aux_addr); 1637 writel(wdata, DP_AUX_ADDR_LEN); 1638 1639 writel(*aux_w_data, DP_AUX_W_D_0); 1640 1641 if ((*length) > 0x4) { 1642 aux_w_data++; 1643 writel(*aux_w_data, DP_AUX_W_D_4); 1644 } 1645 1646 if ((*length) > 0x8) { 1647 aux_w_data++; 1648 writel(*aux_w_data, DP_AUX_W_D_8); 1649 } 1650 1651 if ((*length) > 0xC) { 1652 aux_w_data++; 1653 writel(*aux_w_data, DP_AUX_W_D_C); 1654 } 1655 1656 /* Fire AUX write */ 1657 writel(aux_cmd, DP_AUX_REQ_CFG); 1658 1659 /* Wait AUX write finish or timeout */ 1660 do { 1661 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1662 } while (!(temp & 0xC000)); 1663 1664 /* Clear AUX write interrupt status */ 1665 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1666 writel(wdata, DP_TX_INT_CLEAR); 1667 1668 if (temp & AUX_CMD_DONE) { 1669 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1670 return 0; 1671 } else { 1672 return 1; 1673 } 1674 } 1675 1676 U_BOOT_CMD(dptest, 2, 0, do_ast_dptest, "ASPEED Display Port phy test", "ASPEED DP test v.0.2.9"); 1677