1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <exports.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <reset.h> 12 #include <fdtdec.h> 13 #include <asm/io.h> 14 15 #include "dptest.h" 16 17 /* Version info*/ 18 #define MAINVER 0 19 #define SUBVER 3 20 #define TEMPVER 2 21 22 #define YEAR 2022 23 #define MONTH 07 24 #define DAY 11 25 26 /* Compile define */ 27 /* #define RE_DRIVER */ 28 /* #define INTERNAL */ 29 30 /* Debug define */ 31 #define DBG_Print 32 33 #define DBG_ERR 0x00000001 /* DBG_ERROR */ 34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */ 35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */ 36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */ 37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */ 38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */ 39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */ 40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */ 41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */ 42 /* #define DBG_AUX_W 0x00002000 *//*DBG_AUX_W_VALUE */ 43 44 int DBG_LEVEL = 0x00000040; /* Information and stage */ 45 /* int DBG_LEVEL = 0x0000107F; *//*Fully */ 46 /* int DBG_LEVEL = 0x00000001; *//*Error */ 47 48 #ifdef DBG_Print 49 #define DBG(Level, format, args...) if ((Level) & DBG_LEVEL) printf(format, ##args) 50 #else 51 #define DBG(Level, format, args...) 52 #endif 53 54 int PHY_Cfg_N; 55 int PHY_Cfg; 56 int PHY_Cfg_1; 57 int TX_SSCG_Cfg; 58 int DP_Rate; 59 int Deemphasis_Level; 60 int Deemphasis_Level_1; 61 int Deemphasis_Show; 62 int Deemphasis_RD; 63 int Swing_Level; 64 int SSCG; 65 int Current_Item; 66 int GFlag; 67 uchar EDID[256]; 68 69 int I2C_PORT;/* I2c port */ 70 int I2C_BASE; 71 int I2C_BUFF; 72 uchar RD_VAL; 73 74 /* Record DP Sink status */ 75 uchar bEn_Frame; 76 uchar Link_Aux_RD_Val; 77 uchar CR_EQ_Keep; 78 int Deemlevel[3] = {DP_DEEMP_2, DP_DEEMP_0, DP_DEEMP_1}; 79 uchar Auto_Link_Rate; 80 uchar Auto_Lane_Count; 81 /* uchar Patch_Normal_Behavior; */ 82 83 static int 84 do_ast_dptest(cmd_tbl_t *cmdtp, int flags, int argc, char *const argv[]) 85 { 86 char received = 0; 87 char execute_test = 0; 88 int flag = 0, i; 89 char *Temp = NULL; 90 91 /* Default setting */ 92 DP_Rate = DP_RATE_1_62; 93 94 Deemphasis_Show = DP_DEEMP_0; 95 Deemphasis_Level = DP_DEEMP_0; 96 Deemphasis_Level_1 = DP_DEEMP_2; 97 Swing_Level = 2; 98 SSCG = DP_SSCG_ON; 99 100 /* Obtain the argc / argv */ 101 for (i = 1; i < argc; i++) { 102 if (argv[i][0] == '-') { 103 switch (argv[i][1]) { 104 case 'D': 105 case 'd': 106 Temp = (char *)&argv[i][2]; 107 DBG_LEVEL = (int)(strtoul(Temp, NULL, 16)); 108 DBG_LEVEL |= DBG_ERR; /* Add must print. */ 109 printf("DBG_LEVEL change into 0x%x\n", DBG_LEVEL); 110 break; 111 case 'R': 112 case 'r': 113 Temp = (char *)&argv[i][2]; 114 I2C_PORT = (int)(strtoul(Temp, NULL, 16)); 115 printf("I2C_PORT change into 0x%x\n", I2C_PORT); 116 break; 117 default: 118 I2C_PORT = 0x0; 119 break; 120 } 121 } 122 } 123 124 printf("ASPEED DP Physical Layer Test Tool V %d.%d.%d\n", MAINVER, SUBVER, TEMPVER); 125 #ifdef INTERNAL 126 printf("Internal Version\n"); 127 #endif 128 129 printf("Build Date: %d.%d.%d\n\n", YEAR, MONTH, DAY); 130 131 printf("PLEASE REFER USER MANUAL BEFORE TEST!!\n\n"); 132 133 /* DP TX MCU reset */ 134 DPTX_MCU_Reset(); 135 printf("DP TX MCU Initial Done!\n"); 136 137 /* DP phy set */ 138 DPPHY_Set(); 139 printf("DP Physcial Config Done!\n"); 140 141 printf("Press ESC key to leave test ...\n\n"); 142 143 // While for auto testing 144 while (1) { 145 if (tstc()) { 146 received = getc(); 147 148 /* printf("Press %d\n",received); */ 149 150 /* Set parameters path */ 151 if (received >= 49 && received <= 53) { 152 switch (received) { 153 /* Press "1" : Set DP_Rate as 1.62 */ 154 case '1': 155 DP_Rate = DP_RATE_1_62; 156 PRINT_RATE_1_62; 157 break; 158 /* Press "2" : Set DP_Rate as 2.701 */ 159 case '2': 160 DP_Rate = DP_RATE_2_70; 161 PRINT_RATE_2_70; 162 break; 163 /* Press "3" : Set DP_Rate as 5.40 */ 164 /* case '3': */ 165 /* DP_Rate = DP_RATE_5_40; */ 166 /* PRINT_RATE_5_40 */ 167 /* break; */ 168 #ifdef INTERNAL 169 /* Press "3" : Set Deemphasis_Level as 1 / Deemphasis_Level_1 as 2 */ 170 case '3': 171 Deemphasis_Level = DP_DEEMP_1; 172 Deemphasis_Level_1 = DP_DEEMP_2; 173 Deemphasis_Show = DP_DEEMP_0; 174 Deemphasis_RD = Deemphasis_Show; 175 PRINT_DEEMP_0; 176 break; 177 /* Press "4" : Set Deemphasis_Level as 0 / Deemphasis_Level_1 as 0 */ 178 case '4': 179 Deemphasis_Level = DP_DEEMP_0; 180 Deemphasis_Level_1 = DP_DEEMP_0; 181 Deemphasis_Show = DP_DEEMP_1; 182 Deemphasis_RD = Deemphasis_Show; 183 PRINT_DEEMP_1; 184 break; 185 /* Press "5" : Set Deemphasis_Level as 2 / Deemphasis_Level_1 as 1 */ 186 case '5': 187 Deemphasis_Level = DP_DEEMP_2; 188 Deemphasis_Level_1 = DP_DEEMP_1; 189 Deemphasis_Show = DP_DEEMP_2; 190 Deemphasis_RD = Deemphasis_Show; 191 PRINT_DEEMP_2; 192 break; 193 #endif 194 default: 195 break; 196 } 197 198 if (execute_test) 199 printf("The parameter is applied next measure!\n"); 200 201 } else if (received == '!') /* show config */ { 202 if (execute_test) 203 printf("Measurement is executed!\n"); 204 else 205 printf("Measurement is stopped!\n"); 206 207 DPPHYTX_Show_Cfg(); 208 } else if (received == '0') /* change sscfg */ { 209 if (SSCG == DP_SSCG_ON) { 210 SSCG = DP_SSCG_OFF; 211 PRINT_SSCG_OFF; 212 } else { 213 SSCG = DP_SSCG_ON; 214 PRINT_SSCG_ON; 215 } 216 217 /* SSCG could be applied without reset device. */ 218 if (execute_test) { 219 printf("Apply SSCG into current measurement !\n\n"); 220 TX_SSCG_Cfg = DP_TX_RDY_TEST; 221 /* TX_SSCG_Cfg |= SSCG; */ 222 TX_SSCG_Cfg |= DP_SSCG_ON; 223 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 224 } 225 } else { 226 /* Check the ESC key */ 227 if (received == 27) { 228 execute_test = 0; 229 DPTX_MCU_Reset(); 230 printf("'ESC' is pressed!\n"); 231 break; 232 } 233 234 /* If the test is execute, reset it */ 235 if (execute_test) { 236 execute_test = 0; 237 DPTX_MCU_Reset(); 238 239 printf("Stop current measurement !\n\n\n\n\n\n"); 240 } 241 242 /* Clear flag */ 243 flag = 0; 244 245 Current_Item = received; 246 247 switch (received) { 248 case 'a': 249 flag = (F_EMPHASIS_NULL | F_PAT_PRBS7); 250 break; 251 #ifdef INTERNAL 252 case 'b': 253 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 254 break; 255 256 case 'c': 257 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT); 258 break; 259 260 case 'd': /* Non-Transition Voltage Range Measurement - PLTPAT */ 261 flag = (F_EMPHASIS | F_PAT_PLTPAT); 262 break; 263 264 case 'e': /* Pre-Emphasis Level Test and Pre-Emphasis Level Delta Test- PRBS7 */ 265 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 266 break; 267 268 case 'f': /* Non-Transition Voltage Range Measurement - PRBS7 */ 269 flag = (F_EMPHASIS | F_PAT_PRBS7); 270 break; 271 272 case 'g': /* Total - PRBS7 */ 273 flag = (F_EMPHASIS_1 | F_PAT_D10_2); 274 break; 275 276 case 'h': 277 printf("Change the Swing value from request\n"); 278 flag = (F_EMPHASIS_1 | F_PAT_PRBS7 | F_SHOW_SWING); 279 break; 280 281 case 'i': 282 printf("Change the Swing value from request\n"); 283 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT | DP_TX_HIGH_SPEED | F_SHOW_SWING); 284 break; 285 286 case 'j': 287 flag = F_PAT_AUX; 288 break; 289 #endif 290 case 'x': /* Auto hand shaking with DPR-100 */ 291 flag = F_EXE_AUTO; 292 break; 293 294 default: 295 printf("Non - define command!\n"); 296 break; 297 } 298 299 // Execute testing 300 if (flag) { 301 execute_test = 1; 302 GFlag = flag; 303 304 if (flag & F_PAT_AUX) { 305 printf("######################################\n"); 306 printf("#Current DP TX setting is shown below#\n"); 307 printf("######################################\n\n"); 308 309 DPPHYTX_Show_Item(Current_Item); 310 Apply_AUX_Mesument(flag); 311 } else if (flag & F_EXE_AUTO) { 312 printf("#########################\n"); 313 printf("#Enter DP TX Auto Test!!#\n"); 314 printf("#########################\n\n"); 315 316 Apply_Auto_Preset(0x1); 317 Apply_Auto_Mesument(); 318 Apply_Auto_Preset(0x0); 319 320 printf("#########################\n"); 321 printf("#Leave DP TX Auto Test!!#\n"); 322 printf("#########################\n\n"); 323 } else { 324 DPPHYTX_Show_Cfg(); 325 Apply_Main_Mesument(flag); 326 } 327 } 328 } 329 } 330 mdelay(200); 331 }; 332 333 printf("\n\n"); 334 return 0; 335 } 336 337 /* Temp for cording here */ 338 void Apply_Auto_Preset(char Init) 339 { 340 /* Fill some nessary register value for auto test */ 341 if (Init) { 342 /* Enable MCU received interrupt */ 343 writel(0x00e80000, DP_TX_INT_CLEAR); 344 345 /* Set HPD irq time interval */ 346 writel(0x04e300fb, DP_TX_IRQ_CFG); 347 348 /* Set HPD event time interval */ 349 writel(0x000007d1, DP_TX_EVENT_CFG); 350 } else { 351 /* Recover */ 352 writel(0x0, DP_TX_INT_CLEAR); 353 writel(0x0, DP_TX_IRQ_CFG); 354 writel(0x0, DP_TX_EVENT_CFG); 355 } 356 } 357 358 /* READ EDID */ 359 void Read_EDID_128(char Offset) 360 { 361 char AUX_Data[16] = {0}; 362 uchar Length = 1; 363 uchar Status = 0; 364 uchar i, j; 365 366 DBG(DBG_A_EDID, "R EDID Offset %d\n", Offset); 367 368 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 369 370 AUX_Data[0] = Offset; 371 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 372 373 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 374 375 Length = 16; 376 377 // Read 128 bytes block 378 for (i = 0; i < 8; i++) { 379 do { 380 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 381 DBG(DBG_A_EDID, "EDID read %d!\n", i); 382 383 udelay(100); 384 } while (Status == 0x20); 385 386 /* copy from temp into EDID */ 387 for (j = 0; j < 16; j++) 388 EDID[Offset + i * 16 + j] = AUX_Data[j]; 389 } 390 391 Length = 1; 392 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 393 } 394 395 void Apply_EDID_Reading(void) 396 { 397 char AUX_Data[16] = {0}; 398 uchar Length = 1; 399 uchar Status = 0; 400 401 DBG(DBG_STAGE, "Apply EDID Reading!\n"); 402 403 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 404 405 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 406 407 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 408 409 /* Check read EDID header */ 410 Length = 4; 411 do { 412 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 413 414 udelay(100); 415 } while (Status == 0x20); 416 417 DBG(DBG_A_EDID, "EDID First 4 is 0x%X_0x%X_0x%X_0x%X\n", AUX_Data[0], AUX_Data[1], AUX_Data[2], AUX_Data[3]); 418 419 Length = 1; 420 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 421 422 DBG(DBG_A_EDID, "Read 128!\n"); 423 Read_EDID_128(0x0); 424 425 /* If the extension bit is set, then read back next block */ 426 if (EDID[0x7E] == 0x1) { 427 DBG(DBG_A_EDID, "Read 256!\n"); 428 Read_EDID_128(0x80); 429 } 430 } 431 432 /* LINK TRAIN */ 433 uchar Adjust_CR_EQ_Train(int TrainPat, uchar ADJStatus) 434 { 435 char AUX_Data[16] = {0}; 436 uchar Ret = 0; 437 uchar Length = 1; 438 uchar Status = 0; 439 uchar AUX_R_Level = 0; 440 uchar AUX_W_Level = 0; 441 uchar DE_Level = 0x0; 442 uchar CR_Status = 0; 443 int value = 0; 444 uchar bFirst = 1; 445 uchar tempkeep = 0; 446 447 /* Set the main link pattern with TPS1 / TPS2 for Lanex_CR_Done */ 448 value = ((readl(DP_TX_MAIN_PAT) & ~(0x30000000)) | TrainPat); 449 writel(value, DP_TX_MAIN_PAT); 450 DBG(DBG_A_SUB, "1.A_C_E Set Link Pattern\n"); 451 452 /* AST phy 0xE4 Bit28 (0x1000000) / DP 0x102 Bit0 : TPS1 */ 453 /* AST phy 0xE4 Bit29 (0x2000000) / DP 0x102 Bit1 : TPS2 */ 454 if (TrainPat == 0x10000000) 455 AUX_Data[0] = 0x21; 456 else 457 AUX_Data[0] = 0x22; 458 459 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 460 DBG(DBG_A_SUB, "2.A_C_E W 0x102 set 0x%x\n", AUX_Data[0]); 461 462 /* First */ 463 if (bFirst) { 464 Length = 4; 465 466 AUX_Data[0] = CR_EQ_Keep; 467 AUX_Data[1] = CR_EQ_Keep; 468 AUX_Data[2] = CR_EQ_Keep; 469 AUX_Data[3] = CR_EQ_Keep; 470 tempkeep = CR_EQ_Keep; 471 472 do { 473 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 474 DBG(DBG_A_SUB, "3.A_C_E W 0x103 - 0x106 set\n"); 475 } while (Status == 0x20); 476 477 Length = 6; 478 479 udelay(1200); 480 481 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 482 DBG(DBG_A_SUB, "4.A_C_E R 0x200 - 0x205 read back\n"); 483 484 if ((AUX_Data[2] & ADJStatus) == ADJStatus) { 485 CR_EQ_Keep = tempkeep; 486 return Ret; 487 } 488 489 bFirst = 0; 490 } 491 492 /* loop for CR_lock */ 493 do { 494 Length = 1; 495 496 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 497 DBG(DBG_A_SUB, "5.A_C_E R 0x206 read back\n"); 498 AUX_R_Level = AUX_Data[0]; 499 500 AUX_R(AUX_CMD_R, 0x207, (int *)(&AUX_Data), &Length, &Status); 501 DBG(DBG_A_SUB, "6.A_C_E R 0x207 read back\n"); 502 503 /* Update SW Level */ 504 switch (AUX_R_Level & 0x33) { 505 case 0x00: 506 AUX_W_Level = 00; 507 break; 508 case 0x11: 509 AUX_W_Level = 01; 510 break; 511 default: 512 AUX_W_Level = 06; 513 break; 514 } 515 516 /* Update SW Level */ 517 switch (AUX_R_Level & 0xCC) { 518 case 0x00: 519 /* AUX_W_Level |= 00; */ 520 DE_Level = 0; 521 break; 522 case 0x44: 523 AUX_W_Level |= 0x08; 524 DE_Level = 1; 525 break; 526 default: 527 AUX_W_Level |= 0x30; 528 DE_Level = 2; 529 break; 530 } 531 532 /* Set the de-emphsis value */ 533 value = ((readl(DP_TX_PHY_CFG) & ~(0x33000000)) | Deemlevel[DE_Level]); 534 writel(value, DP_TX_PHY_CFG); 535 DBG(DBG_A_SUB, "6.A_C_E Set Phy config %d\n", DE_Level); 536 537 DBG(DBG_A_SUB, "Link AUX_W_Level is 0x%x\n", AUX_W_Level); 538 539 Length = 4; 540 541 AUX_Data[0] = AUX_W_Level; 542 AUX_Data[1] = AUX_W_Level; 543 AUX_Data[2] = AUX_W_Level; 544 AUX_Data[3] = AUX_W_Level; 545 tempkeep = AUX_W_Level; 546 547 do { 548 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 549 DBG(DBG_A_SUB, "7.A_C_E W 0x103 - 0x106 set\n"); 550 } while (Status == 0x20); 551 552 udelay(1380); 553 554 Length = 6; 555 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 556 DBG(DBG_A_SUB, "8.A_C_E R 0x200 - 0x205 read back\n"); 557 558 CR_Status = AUX_Data[2] & ADJStatus; 559 560 /* Decrease speed because the deemphasis level reach max value */ 561 if (AUX_W_Level == 0x36) { 562 Ret = 1; 563 break; 564 } 565 566 } while (CR_Status != ADJStatus); 567 568 CR_EQ_Keep = tempkeep; 569 570 return Ret; 571 } 572 573 uchar Link_Train_Flow(char Link_Level) 574 { 575 char AUX_Data[16] = {0}; 576 uchar Length = 1; 577 uchar Status = 0; 578 uchar Ret = 0; 579 int value = 0; 580 581 DBG(DBG_STAGE, "Link train flow! Level : %d\n", Link_Level); 582 583 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 584 DBG(DBG_A_SUB, "1.Link R 0x101 read back\n"); 585 586 /* Normal / Test case */ 587 if (Auto_Lane_Count) 588 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 589 else 590 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 591 592 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 593 DBG(DBG_A_SUB, "2.Link W 0x101 clear\n"); 594 595 /* Set different clock bit rate */ 596 value = ((readl(DP_TX_MAIN_SET) & ~(0x300)) | (Link_Level << 8)); 597 writel(value, DP_TX_MAIN_SET); 598 599 switch (Link_Level) { 600 case 0x1: /* 2.7 */ 601 AUX_Data[0] = 0x0a; 602 break; 603 604 default: /* 1.62 */ 605 AUX_Data[0] = 0x06; 606 break; 607 } 608 609 AUX_W(AUX_CMD_W, 0x100, (int *)(&AUX_Data), &Length, &Status); 610 DBG(DBG_A_SUB, "3.Link W 0x100 set\n"); 611 612 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 613 DBG(DBG_A_SUB, "4.Link R 0x101 read back\n"); 614 615 /* Normal / Test case */ 616 if (Auto_Lane_Count) 617 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 618 else 619 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 620 621 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 622 DBG(DBG_A_SUB, "5.Link W 0x101 clear\n"); 623 624 /* Set the 2 lanes and enhance frame by checking AUX 0x2 bit 7 */ 625 value = ((readl(DP_TX_MAIN_SET) & ~(0x1070)) | 0x20); 626 627 if (bEn_Frame) 628 value |= 0x1000; 629 630 writel(value, DP_TX_MAIN_SET); 631 632 value = ((readl(DP_TX_PHY_CFG) & ~(0x3000)) | 0x3000); 633 634 writel(value, DP_TX_PHY_CFG); 635 636 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 637 DBG(DBG_A_SUB, "6.Link R 0x101 read back\n"); 638 639 /* Normal / Test case */ 640 if (Auto_Lane_Count) 641 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 642 else 643 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 644 645 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 646 DBG(DBG_A_SUB, "7.Link W 0x101 clear\n"); 647 648 /* Set the main link control on */ 649 value = ((readl(DP_TX_PHY_SET) & ~(0x100)) | 0x100); 650 651 udelay(1000); 652 udelay(1500); 653 654 writel(value, DP_TX_PHY_SET); 655 656 do { 657 value = (readl(DP_TX_PHY_SET) & 0x200); 658 } while (value != 0x200); 659 DBG(DBG_A_SUB, "8.Link Main Link Ready\n"); 660 661 /* Adjust for CR */ 662 if (Adjust_CR_EQ_Train(0x10000000, 0x11)) { 663 Ret = 1; 664 return Ret; 665 } 666 667 /* Adjust for EQ */ 668 if (Adjust_CR_EQ_Train(0x20000000, 0x77)) { 669 Ret = 1; 670 return Ret; 671 } 672 673 return Ret; 674 } 675 676 void Apply_HPD_Normal(void) 677 { 678 char AUX_Data[16] = {0}; 679 uchar Length = 1; 680 uchar Status = 0; 681 int value = 0; 682 683 DBG(DBG_STAGE, "HPD Normal set!\n"); 684 685 AUX_Data[0] = 0x01; 686 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 687 DBG(DBG_NOR, "1.HPD_N W 0x600 set power!\n"); 688 689 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 690 DBG(DBG_NOR, "2.HPD_N R 0x0 read back is 0x%X!\n", AUX_Data[0]); 691 692 Length = 8; 693 AUX_R(AUX_CMD_R, 0x500, (int *)(&AUX_Data), &Length, &Status); 694 DBG(DBG_NOR, "3.HPD_N R 0x500 - 0x508 read back\n"); 695 696 Length = 14; 697 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 698 DBG(DBG_NOR, "4.HPD_N R 0x0 - 0xD read back\n"); 699 700 bEn_Frame = AUX_Data[2] & 0x80; 701 Link_Aux_RD_Val = AUX_Data[14]; 702 703 if (bEn_Frame) 704 DBG(DBG_NOR, "4.HPD_N R 0x2 En_Frame_Cap\n"); 705 706 Length = 1; 707 AUX_R(AUX_CMD_R, 0xe, (int *)(&AUX_Data), &Length, &Status); 708 DBG(DBG_NOR, "5.HPD_N R 0xE read back\n"); 709 710 /* Read EDID */ 711 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Enter\n"); 712 713 Apply_EDID_Reading(); 714 715 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Leave\n"); 716 717 Length = 2; 718 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 719 DBG(DBG_NOR, "7.HPD_N R 0x200 - 0x201 read back.\n"); 720 721 Length = 1; 722 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 723 DBG(DBG_NOR, "8.HPD_N R 0x68028 read back.\n"); 724 725 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 726 DBG(DBG_NOR, "9.HPD_N R 0x68028 read back.\n"); 727 728 AUX_R(AUX_CMD_R, 0x600, (int *)(&AUX_Data), &Length, &Status); 729 DBG(DBG_NOR, "10.HPD_N R 0x600 read back.\n"); 730 731 AUX_Data[0] = 0x01; 732 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 733 DBG(DBG_NOR, "11.HPD_N W 0x600 set power!\n"); 734 735 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Enter\n"); 736 737 Status = Link_Train_Flow(0x1); 738 739 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Leave\n"); 740 741 if (Status) { 742 AUX_Data[0] = 0x20; 743 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 744 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x1 Fail!!\n"); 745 746 DBG(DBG_NOR, "13.HPD_N Link_Train_Flow 0x0 Enter\n"); 747 748 Status = Link_Train_Flow(0x0); 749 750 DBG(DBG_NOR, "13.HPD_NLink_Train_Flow 0x0 Leave\n"); 751 752 if (Status) { 753 AUX_Data[0] = 0x20; 754 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 755 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x0 Fail!!\n"); 756 757 DBG(DBG_ERR, "### CAUTION!! LINK TRAN FAIL!! ###\n"); 758 759 return; 760 } 761 } 762 763 /* Link successful */ 764 AUX_Data[0] = 0x00; 765 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 766 DBG(DBG_NOR, "14.HPD_N W 0x102 clear!\n"); 767 768 /* Fill idle pattern */ 769 value = ((readl(DP_TX_MAIN_PAT) & ~(0x31000000)) | 0x01000000); 770 writel(value, DP_TX_MAIN_PAT); 771 DBG(DBG_NOR, "15.HPD_N Fill idle pattern!\n"); 772 773 Length = 1; 774 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 775 DBG(DBG_NOR, "16.HPD_N R 0x68028 read back.\n"); 776 777 Length = 5; 778 AUX_R(AUX_CMD_R, 0x68000, (int *)(&AUX_Data), &Length, &Status); 779 DBG(DBG_NOR, "17.HPD_N R 0x68000 - 0x68004 read back.\n"); 780 781 Length = 1; 782 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 783 DBG(DBG_NOR, "18.HPD_N R 0x68028 read back.\n"); 784 785 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 786 DBG(DBG_NOR, "19.HPD_N R 0x68028 read back.\n"); 787 788 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 789 DBG(DBG_NOR, "20.HPD_N R 0x0 read back.\n"); 790 } 791 792 void Apply_HPD_Auto_Test(void) 793 { 794 char AUX_Data[16]; 795 uchar Length = 0; 796 uchar Status = 0; 797 uchar clear_auto_test = 0; 798 uchar auto_test_link = 0; 799 uchar auto_test_phy = 0; 800 uchar swing0 = 0, preemphasis0 = 0; 801 uchar swing1 = 0, preemphasis1 = 0; 802 int flag = 0; 803 char temp0 = 0, temp1 = 0; 804 char temp206 = 0; 805 806 DBG(DBG_STAGE, "HPD Auto test set!\n"); 807 808 /* Set power D0 */ 809 AUX_Data[0] = 0x01; 810 Length = 1; 811 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 812 DBG(DBG_A_TEST, "1.HP_I W 0x600 done!\n"); 813 814 Length = 6; 815 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 816 DBG(DBG_A_TEST, "2.HP_I R 0x200 - 0x206 done!\n"); 817 818 Length = 1; 819 AUX_R(AUX_CMD_R, 0x201, (int *)(&AUX_Data), &Length, &Status); 820 DBG(DBG_A_TEST, "3.HP_I R 0x201 done!\n"); 821 822 /* Obtain auto test */ 823 if (AUX_Data[0] & 0x2) 824 clear_auto_test = 1; 825 else 826 clear_auto_test = 0; 827 828 /* Read dummy */ 829 Length = 3; 830 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 831 Length = 1; 832 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 833 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 834 Length = 3; 835 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 836 Length = 1; 837 AUX_R(AUX_CMD_R, 0x205, (int *)(&AUX_Data), &Length, &Status); 838 DBG(DBG_A_TEST, "4. HP_I R Dummy!\n"); 839 840 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 841 DBG(DBG_A_TEST, "5. HP_I Link Rate R 0x219 : 0x%x\n", AUX_Data[0]); 842 843 if (AUX_Data[0] == 0x06) { 844 Auto_Link_Rate = AUX_Data[0]; 845 DP_Rate = DP_RATE_1_62; 846 PRINT_RATE_1_62; 847 } else if (AUX_Data[0] == 0x0a) { 848 Auto_Link_Rate = AUX_Data[0]; 849 DP_Rate = DP_RATE_2_70; 850 PRINT_RATE_2_70; 851 } else if (AUX_Data[0] == 0x14) { 852 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 853 return; 854 } 855 856 if (clear_auto_test) { 857 AUX_Data[0] = 0x02; 858 AUX_W(AUX_CMD_W, 0x201, (int *)(&AUX_Data), &Length, &Status); 859 DBG(DBG_A_TEST, "1.HP_I CA W 0x201 clear auto!\n"); 860 clear_auto_test = 0; 861 862 /* Fetch Testing data */ 863 AUX_R(AUX_CMD_R, 0x218, (int *)(&AUX_Data), &Length, &Status); 864 DBG(DBG_A_TEST, "2.HP_I CA R 0x218 done!\n"); 865 866 /* Check auto test link flag */ 867 if (AUX_Data[0] & 0x1) 868 auto_test_link = 1; 869 else 870 auto_test_link = 0; 871 872 /* Check auto test phy flag */ 873 if (AUX_Data[0] & 0x8) 874 auto_test_phy = 1; 875 else 876 auto_test_phy = 0; 877 878 if (auto_test_link) { 879 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 880 DBG(DBG_A_TEST, "1.HP_I TL R 0x219 : 0x%x\n", AUX_Data[0]); 881 882 if (AUX_Data[0] == 0x06) { 883 Auto_Link_Rate = AUX_Data[0]; 884 DP_Rate = DP_RATE_1_62; 885 PRINT_RATE_1_62; 886 } else if (AUX_Data[0] == 0x0a) { 887 Auto_Link_Rate = AUX_Data[0]; 888 DP_Rate = DP_RATE_2_70; 889 PRINT_RATE_2_70; 890 } else if (AUX_Data[0] == 0x14) { 891 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 892 return; 893 } 894 895 AUX_R(AUX_CMD_R, 0x220, (int *)(&AUX_Data), &Length, &Status); 896 DBG(DBG_A_TEST, "2.HP_I TL R 0x220 : 0x%x\n", AUX_Data[0]); 897 Auto_Lane_Count = AUX_Data[0] & 0x1F; 898 899 AUX_Data[0] = 0x01; 900 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 901 DBG(DBG_A_TEST, "3.HP_I TL W 0x260 test ACK\n"); 902 903 mdelay(95); 904 905 /* Set power D0 */ 906 AUX_Data[0] = 0x01; 907 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 908 DBG(DBG_A_TEST, "3.1 HP_I W 0x600 done!\n"); 909 910 switch (Auto_Link_Rate) { 911 case 0x06: 912 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Enter\n"); 913 Status = Link_Train_Flow(0x0); 914 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Leave\n"); 915 break; 916 917 case 0x0a: 918 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Enter\n"); 919 Status = Link_Train_Flow(0x1); 920 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Leave\n"); 921 break; 922 923 default: 924 DBG(DBG_ERR, "!!BAD LINK RATE!!\n"); 925 return; 926 } 927 928 if (Status) { 929 DBG(DBG_ERR, "!!AUTO TEST LINK FAIL!!\n"); 930 return; 931 } 932 933 /* Link successful */ 934 AUX_Data[0] = 0x00; 935 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 936 DBG(DBG_A_TEST, "5.HP_I TL Link clear!\n"); 937 938 auto_test_link = 0; 939 } 940 941 if (auto_test_phy) { 942 Length = 1; 943 flag = 0; 944 temp206 = 0; 945 946 AUX_R(AUX_CMD_R, 0x248, (int *)(&AUX_Data), &Length, &Status); 947 DBG(DBG_A_TEST, "1.HP_I TP R 0x248 : 0x%x!\n", AUX_Data[0]); 948 949 if (AUX_Data[0] == 0x01) { 950 flag |= F_PAT_D10_2; 951 DBG(DBG_A_TEST, "HP_I TP D10.2!\n"); 952 } else if (AUX_Data[0] == 0x03) { 953 flag |= F_PAT_PRBS7; 954 DBG(DBG_A_TEST, "HP_I TP PRBS7!\n"); 955 } 956 957 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 958 DBG(DBG_A_TEST, "2.HP_I TP R 0x206 : 0x%x!\n", AUX_Data[0]); 959 960 /* Temp for verified */ 961 DBG(DBG_INF, "Read value 0x206 : 0x%x!\n", AUX_Data[0]); 962 963 /* Check Swing */ 964 temp0 = (AUX_Data[0] & 0x03); 965 temp1 = (AUX_Data[0] & 0x30); 966 967 /* Check Swing0 */ 968 switch (temp0) { 969 case 0x2: 970 swing0 = 0x2; 971 temp206 |= 6; 972 break; 973 case 0x1: 974 swing0 = 0x1; 975 temp206 |= 1; 976 break; 977 case 0x0: 978 swing0 = 0x0; 979 break; 980 default: 981 DBG(DBG_ERR, "HP_I TP 0x206 other swing0 val %x!\n", temp0); 982 break; 983 } 984 985 /* Check Swing1 */ 986 switch (temp1) { 987 case 0x20: 988 swing1 = 0x2; 989 temp206 |= 6; 990 break; 991 case 0x10: 992 swing1 = 0x1; 993 temp206 |= 1; 994 break; 995 case 0x00: 996 swing1 = 0x0; 997 break; 998 default: 999 DBG(DBG_ERR, "HP_I TP 0x206 other swing1 val %x!\n", temp1); 1000 break; 1001 } 1002 1003 if (swing0 != swing1) 1004 DBG(DBG_ERR, "Swing 0 / 1 diff val %x!\n", AUX_Data[0]); 1005 1006 /* Check Pre-emphasis */ 1007 temp0 = (AUX_Data[0] & 0x0C); 1008 temp1 = (AUX_Data[0] & 0xC0); 1009 1010 /* Check Pre-emphasis0 */ 1011 switch (temp0) { 1012 case 0x8: 1013 preemphasis0 = 0x2; 1014 temp206 |= 0x30; 1015 break; 1016 case 0x4: 1017 preemphasis0 = 0x1; 1018 temp206 |= 0x08; 1019 break; 1020 case 0x0: 1021 preemphasis0 = 0x0; 1022 break; 1023 default: 1024 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis0 val %x!\n", temp0); 1025 break; 1026 } 1027 1028 /* Check Pre-emphasis1 */ 1029 switch (temp1) { 1030 case 0x80: 1031 preemphasis1 = 0x2; 1032 temp206 |= 0x30; 1033 break; 1034 case 0x40: 1035 preemphasis1 = 0x1; 1036 temp206 |= 0x08; 1037 break; 1038 case 0x00: 1039 preemphasis1 = 0x0; 1040 break; 1041 default: 1042 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis1 val %x!\n", temp1); 1043 break; 1044 } 1045 1046 if (preemphasis0 != preemphasis1) 1047 DBG(DBG_ERR, "Preemphasis 0 / 1 diff val %x!\n", AUX_Data[0]); 1048 1049 /* Judgement */ 1050 if (swing0 == 0x2 || swing1 == 0x2) 1051 Swing_Level = 0x2; 1052 else if (swing0 == 1 || swing1 == 0x1) 1053 Swing_Level = 0x1; 1054 else if (swing0 == 0x0 || swing1 == 0x0) 1055 Swing_Level = 0x0; 1056 1057 if (preemphasis0 == 0x2 || preemphasis1 == 0x2) { 1058 Deemphasis_RD = DP_DEEMP_2; 1059 Deemphasis_Level_1 = DP_DEEMP_1; 1060 DBG(DBG_ERR, "!!De-type 1 P_2 !!\n"); 1061 } else if (preemphasis0 == 0x1 || preemphasis1 == 0x1) { 1062 Deemphasis_RD = DP_DEEMP_1; 1063 Deemphasis_Level_1 = DP_DEEMP_0; 1064 DBG(DBG_ERR, "!!De-type 0 P_1 !!\n"); 1065 } else if (preemphasis0 == 0x0 || preemphasis1 == 0x0) { 1066 Deemphasis_RD = DP_DEEMP_0; 1067 Deemphasis_Level_1 = DP_DEEMP_2; 1068 DBG(DBG_ERR, "!!De-type 2 P_0 !!\n"); 1069 } 1070 1071 DBG(DBG_INF, "!!Swing %d / Pre-emphasis %d !!\n", swing0, preemphasis0); 1072 1073 flag |= F_EMPHASIS_1; 1074 1075 AUX_R(AUX_CMD_R, 0x102, (int *)(&AUX_Data), &Length, &Status); 1076 DBG(DBG_A_TEST, "3.HP_I TP R 0x102 done!\n"); 1077 temp0 = AUX_Data[0]; 1078 1079 Length = 2; 1080 AUX_R(AUX_CMD_R, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1081 DBG(DBG_A_TEST, "4.HP_I TP R 0x10b done!\n"); 1082 1083 AUX_W(AUX_CMD_W, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1084 DBG(DBG_A_TEST, "5.HP_I TP W 0x10b done!\n"); 1085 1086 AUX_Data[0] = temp0 | 0x20; 1087 Length = 1; 1088 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 1089 DBG(DBG_A_TEST, "6.HP_I TP W 0x102 done!\n"); 1090 1091 AUX_Data[0] = temp206; 1092 AUX_Data[1] = temp206; 1093 Length = 2; 1094 1095 do { 1096 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 1097 DBG(DBG_A_TEST, "7.HP_I TP W 0x103 - 0x104 done!\n"); 1098 } while (Status == 0x20); 1099 1100 DPPHYTX_Show_Cfg(); 1101 Apply_Main_Mesument(flag); 1102 1103 Length = 1; 1104 AUX_Data[0] = 0x01; 1105 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 1106 DBG(DBG_A_TEST, "8.HP_I TP W 0x260 done!\n"); 1107 1108 DBG(DBG_STAGE, "Leave Apply Auto Test\n"); 1109 1110 auto_test_phy = 0; 1111 } 1112 clear_auto_test = 0; 1113 } 1114 } 1115 1116 /* TEST SECTION */ 1117 void Apply_Auto_Mesument(void) 1118 { 1119 char auto_received = 0; 1120 int temp = 0, wdata = 0; 1121 int breakcount = 0; 1122 1123 while (1) { 1124 breakcount = 0; 1125 1126 /* Wait HPD */ 1127 do { 1128 temp = (readl(DP_TX_INT_STATUS) & 0x3800); 1129 breakcount++; 1130 1131 if (breakcount == 0x96000) { 1132 /* A simple break for esc press received */ 1133 break; 1134 } 1135 1136 } while (!(temp & 0x3800)); 1137 1138 if (temp) { 1139 /* Clear AUX write interrupt status */ 1140 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1141 writel(wdata, DP_TX_INT_CLEAR); 1142 } 1143 1144 /* Interrupt occur */ 1145 if (temp & 0x2800) { 1146 /* Initial global parameter */ 1147 Auto_Link_Rate = 0; 1148 Auto_Lane_Count = 0; 1149 bEn_Frame = 0; 1150 CR_EQ_Keep = 0; 1151 1152 if (temp & 0x2000) { 1153 printf("DP HPD event is detected!\n"); 1154 Apply_HPD_Normal(); 1155 } 1156 1157 if (temp & 0x800) { 1158 printf("DP HPD irq is detected!\n"); 1159 Apply_HPD_Auto_Test(); 1160 } 1161 } 1162 1163 /* Leave auto test if the 'ESC' is pressed */ 1164 if (tstc()) { 1165 auto_received = getc(); 1166 1167 /* Check the ESC key */ 1168 if (auto_received == 27) { 1169 printf("'ESC' is pressed under auto test!\n\n"); 1170 return; 1171 } 1172 1173 printf("DP TX auto test is executed!\n"); 1174 } 1175 } 1176 } 1177 1178 void Apply_Main_Mesument(int flag) 1179 { 1180 DPTX_MCU_Reset(); 1181 1182 /* Emphasis setting */ 1183 if (flag & F_EMPHASIS_NULL) 1184 writel(PHY_Cfg_N, DP_TX_PHY_CFG); 1185 else if (flag & F_EMPHASIS) 1186 writel(PHY_Cfg, DP_TX_PHY_CFG); 1187 else if (flag & F_EMPHASIS_1) 1188 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1189 1190 if (flag & F_RES_HIGH) 1191 writel(DP_TX_HIGH_SPEED, DP_TX_RES_CFG); 1192 else 1193 writel(DP_TX_NOR_SPEED, DP_TX_RES_CFG); 1194 1195 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1196 1197 DPPHY_Set(); 1198 1199 if (flag & F_PAT_PRBS7) 1200 Set_PRBS7(); 1201 else if (flag & F_PAT_PLTPAT) 1202 Set_PLTPAT(); 1203 else if (flag & F_PAT_HBR2CPAT) 1204 Set_HBR2CPAT(); 1205 else if (flag & F_PAT_D10_2) 1206 Set_D10_1(); 1207 1208 /* ssc special patch */ 1209 if (flag & F_PAT_D10_2) { 1210 /*Apply special patch*/ 1211 writel(0x00000400, DP_TX_RES_CFG); 1212 TX_SSCG_Cfg |= DP_SSCG_ON; 1213 } else { 1214 /*Recover into original setting*/ 1215 writel(0x00000000, DP_TX_RES_CFG); 1216 } 1217 1218 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 1219 } 1220 1221 void Apply_AUX_Mesument(int flag) 1222 { 1223 DPTX_MCU_Reset(); 1224 DPPHY_Set(); 1225 1226 writel(0x0F000000, DP_AUX_ADDR_LEN); 1227 writel(0x80000010, DP_AUX_REQ_CFG); 1228 } 1229 1230 /* FUNCTION SECTION */ 1231 /* i2c set */ 1232 #ifdef RE_DRIVER 1233 void Set_Redriver(void) 1234 { 1235 int value = 0x0; 1236 uchar offset = 0x0; 1237 uchar *set_table = &set_table0; 1238 1239 if (Deemphasis_RD == DP_DEEMP_1) 1240 set_table = &set_table1; 1241 else if (Deemphasis_RD == DP_DEEMP_2) 1242 set_table = &set_table2; 1243 1244 RD_VAL = set_table[Swing_Level]; 1245 1246 printf("RD_VAL is 0x%x\n", RD_VAL); 1247 1248 writel(0x600, I2C_BASE + I2C0_COUNT_O); 1249 value = (0x0000f0f0 | (RD_VAL << 24)); 1250 writel(value, I2C_BUFF); 1251 printf("value0 is 0x%x\n", value); 1252 value = (RD_VAL | (RD_VAL << 8) | (RD_VAL << 16) | (RD_VAL << 24)); 1253 writel(value, (I2C_BUFF + 0x4)); 1254 printf("value1 is 0x%x\n", value); 1255 writel(0x70010063, (I2C_BASE + I2C0_EXECUTE_O)); 1256 mdelay(1000); 1257 } 1258 1259 /* i2c single initial */ 1260 void I2C_L_Initial(void) 1261 { 1262 I2C_BASE = (I2C0_BASE + (I2C_DEV_OFFSET * I2C_PORT)); 1263 I2C_BUFF = (I2C0_BUFF + (I2C_BUFF_OFFSET * I2C_PORT)); 1264 1265 writel(0x0, I2C_BASE); 1266 mdelay(1); 1267 writel(0x28001, I2C_BASE); 1268 writel(0x344001, I2C_BASE + I2C0_TIMMING_O); 1269 writel(0xFFFFFFFF, I2C_BASE + I2C0_INT_STATUS_O); 1270 writel(0x0, I2C_BASE + I2C0_INT_O); 1271 mdelay(10); 1272 } 1273 1274 /* i2c golbal iniitial */ 1275 void I2C_G_Initial(void) 1276 { 1277 /* i2c multi-function */ 1278 writel(0x0FFF3000, MP_SCU410); 1279 writel(0x0F00FF00, MP_SCU414); 1280 writel(0xCFFF001F, MP_SCU418); 1281 writel(0xF00000FF, MP_SCU4b0); 1282 writel(0xF0FF00FF, MP_SCU4b4); 1283 writel(0x0000FF00, MP_SCU4b8); 1284 1285 /* I2c control */ 1286 writel(0x16, (I2C_GBASE + 0xC)); 1287 writel(0x041230C6, (I2C_GBASE + 0x10)); 1288 1289 mdelay(1000); 1290 } 1291 #endif 1292 1293 void DPTX_MCU_Reset(void) 1294 { 1295 /* Reset DPMCU & Release DPTX */ 1296 writel(0x20000000, SYS_REST); 1297 writel(0x10000000, SYS_REST_CLR); 1298 1299 /* Wait for apply setting */ 1300 mdelay(1000); 1301 } 1302 1303 void DPPHY_Set(void) 1304 { 1305 int value = 0, count = 0; 1306 1307 /* Clear power on reset */ 1308 writel(0x10000000, DP_TX_PHY_SET); 1309 mdelay(1); 1310 1311 /* Clear DPTX reset */ 1312 writel(0x11000000, DP_TX_PHY_SET); 1313 mdelay(1); 1314 1315 /* Turn on Main link / Aux channel */ 1316 writel(0x11001100, DP_TX_PHY_SET); 1317 mdelay(1); 1318 1319 while (value != DP_TX_RDY_TEST) { 1320 value = readl(DP_TX_PHY_SET); 1321 mdelay(1); 1322 count++; 1323 } 1324 } 1325 1326 char DPPHYTX_Show_Cfg(void) 1327 { 1328 char SetFail = 0; 1329 1330 PHY_Cfg = DP_PHY_INIT_CFG; 1331 PHY_Cfg_1 = DP_PHY_INIT_CFG; 1332 TX_SSCG_Cfg = DP_TX_RDY_TEST; 1333 1334 /* Show the setting */ 1335 1336 printf("######################################\n"); 1337 printf("#Current DP TX setting is shown below#\n"); 1338 printf("######################################\n\n"); 1339 1340 DPPHYTX_Show_Item(Current_Item); 1341 1342 switch (DP_Rate) { 1343 case DP_RATE_1_62: 1344 PRINT_RATE_1_62; 1345 break; 1346 1347 case DP_RATE_2_70: 1348 PRINT_RATE_2_70; 1349 break; 1350 1351 case DP_RATE_5_40: 1352 PRINT_RATE_5_40; 1353 break; 1354 1355 default: 1356 PRINT_INVALID; 1357 printf("DP Rate\n"); 1358 SetFail = 1; 1359 break; 1360 } 1361 1362 switch (Deemphasis_Show) { 1363 case DP_DEEMP_0: 1364 if (GFlag & F_SHOW_SWING) 1365 PRINT_SWING_0; 1366 else 1367 PRINT_EMPVAL_0; 1368 break; 1369 1370 case DP_DEEMP_1: 1371 if (GFlag & F_SHOW_SWING) 1372 PRINT_SWING_1; 1373 else 1374 PRINT_EMPVAL_1; 1375 break; 1376 1377 case DP_DEEMP_2: 1378 if (GFlag & F_SHOW_SWING) 1379 PRINT_SWING_2; 1380 else 1381 PRINT_EMPVAL_2; 1382 break; 1383 1384 default: 1385 PRINT_INVALID; 1386 printf("Deemphasis Level\n"); 1387 SetFail = 1; 1388 break; 1389 } 1390 1391 switch (Swing_Level) { 1392 case 0: 1393 PRINT_SWING_0; 1394 break; 1395 1396 case 1: 1397 PRINT_SWING_1; 1398 break; 1399 1400 case 2: 1401 PRINT_SWING_2; 1402 break; 1403 1404 default: 1405 PRINT_INVALID; 1406 printf("Swing Level\n"); 1407 SetFail = 1; 1408 break; 1409 } 1410 1411 PHY_Cfg = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level); 1412 PHY_Cfg_1 = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level_1); 1413 PHY_Cfg_N = DP_PHY_INIT_CFG | (DP_Rate | DP_DEEMP_2); 1414 1415 switch (SSCG) { 1416 case DP_SSCG_ON: 1417 /*PRINT_SSCG_ON;*/ 1418 break; 1419 1420 case DP_SSCG_OFF: 1421 /*PRINT_SSCG_OFF;*/ 1422 break; 1423 1424 default: 1425 PRINT_INVALID; 1426 printf("SSCG\n"); 1427 SetFail = 1; 1428 break; 1429 } 1430 /* TX_SSCG_Cfg |= SSCG; */ 1431 TX_SSCG_Cfg |= DP_SSCG_ON; 1432 1433 printf("\n"); 1434 1435 return SetFail; 1436 } 1437 1438 void DPPHYTX_Show_Item(char received) 1439 { 1440 switch (received) { 1441 case 'a': 1442 PRINT_ITEM_A; 1443 break; 1444 1445 case 'b': 1446 PRINT_ITEM_B; 1447 break; 1448 1449 case 'c': 1450 PRINT_ITEM_C; 1451 break; 1452 1453 case 'd': 1454 PRINT_ITEM_D; 1455 break; 1456 1457 case 'e': 1458 PRINT_ITEM_E; 1459 break; 1460 1461 case 'f': 1462 PRINT_ITEM_F; 1463 break; 1464 1465 case 'g': 1466 PRINT_ITEM_G; 1467 break; 1468 1469 case 'h': 1470 PRINT_ITEM_H; 1471 break; 1472 1473 case 'i': 1474 PRINT_ITEM_I; 1475 break; 1476 1477 case 'j': 1478 PRINT_ITEM_J; 1479 break; 1480 1481 case 'x': 1482 PRINT_ITEM_X; 1483 break; 1484 1485 default: 1486 break; 1487 } 1488 1489 printf("\n"); 1490 } 1491 1492 void Set_PRBS7(void) 1493 { 1494 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1495 writel((DP_PY_PAT | DP_PY_PAT_PRB7), DP_TX_PHY_PAT); 1496 } 1497 1498 void Set_HBR2CPAT(void) 1499 { 1500 int value = 0, count = 0; 1501 1502 writel(DP_TX_MAIN_ADV, DP_TX_MAIN_SET); 1503 1504 writel(DP_TX_PAT_HBR2, DP_TX_MAIN_PAT); 1505 writel((DP_PY_PAT | DP_PY_PAT_SCRB), DP_TX_PHY_PAT); 1506 1507 writel(DP_TX_MAIN_TRA, DP_TX_MAIN_CFG); 1508 mdelay(1); 1509 1510 while (value != DP_TX_RDY_25201) { 1511 value = (readl(DP_TX_MAIN_CFG) & 0xFFF); 1512 mdelay(1); 1513 count++; 1514 } 1515 1516 /* Reset for signal apply */ 1517 writel((DP_TX_MAIN_ADV | DP_TX_PY_RESET), DP_TX_MAIN_SET); 1518 } 1519 1520 void Set_PLTPAT(void) 1521 { 1522 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1523 1524 writel(DP_TX_PLTPAT_0, DP_TX_CUS_PAT_0); 1525 writel(DP_TX_PLTPAT_1, DP_TX_CUS_PAT_1); 1526 writel(DP_TX_PLTPAT_2, DP_TX_CUS_PAT_2); 1527 1528 writel((DP_PY_PAT | DP_PY_PAT_CUS), DP_TX_PHY_PAT); 1529 } 1530 1531 void Set_D10_1(void) 1532 { 1533 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1534 1535 writel(DP_TX_PAT_TPS1, DP_TX_MAIN_PAT); 1536 writel(DP_PY_PAT, DP_TX_PHY_PAT); 1537 } 1538 1539 uchar AUX_R(int aux_cmd, int aux_addr, int *aux_r_data, uchar *length, uchar *status) 1540 { 1541 int wdata = 0, temp = 0; 1542 uchar len = *length; 1543 1544 /* Check valid length */ 1545 if (len >= 1) 1546 len -= 1; 1547 else 1548 return 1; 1549 1550 /* Prepare AUX write address and data */ 1551 wdata = (int)((len << 24) | aux_addr); 1552 writel(wdata, DP_AUX_ADDR_LEN); 1553 1554 DBG(DBG_AUX_R, "AUX Read on 0x%x with %d bytes.\n", aux_addr, *length); 1555 1556 /* Fire AUX read */ 1557 writel(aux_cmd, DP_AUX_REQ_CFG); 1558 1559 /* Wait AUX read finish or timeout */ 1560 do { 1561 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1562 } while (!(temp & 0xC000)); 1563 1564 /* Clear AUX write interrupt status */ 1565 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1566 writel(wdata, DP_TX_INT_CLEAR); 1567 1568 if (temp & AUX_CMD_DONE) { 1569 /* Read back data count */ 1570 *aux_r_data = readl(DP_AUX_R_D_0); 1571 1572 DBG(DBG_AUX_R, "Data on 0x0 is 0x%x.\n", *aux_r_data); 1573 1574 if ((*length) > 0x4) { 1575 aux_r_data++; 1576 *aux_r_data = readl(DP_AUX_R_D_4); 1577 DBG(DBG_AUX_R, "Data on 0x4 is 0x%x.\n", *aux_r_data); 1578 } 1579 1580 if ((*length) > 0x8) { 1581 aux_r_data++; 1582 *aux_r_data = readl(DP_AUX_R_D_8); 1583 DBG(DBG_AUX_R, "Data on 0x8 is 0x%x.\n", *aux_r_data); 1584 } 1585 1586 if ((*length) > 0xC) { 1587 aux_r_data++; 1588 *aux_r_data = readl(DP_AUX_R_D_C); 1589 DBG(DBG_AUX_R, "Data on 0xC is 0x%x.\n", *aux_r_data); 1590 } 1591 1592 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1593 return 0; 1594 } else { 1595 return 1; 1596 } 1597 } 1598 1599 uchar AUX_W(int aux_cmd, int aux_addr, int *aux_w_data, uchar *length, uchar *status) 1600 { 1601 int wdata = 0, temp = 0; 1602 uchar len = *length; 1603 1604 /* Check valid length */ 1605 if (len >= 1) 1606 len -= 1; 1607 else 1608 return 1; 1609 1610 /* Prepare AUX write address and data */ 1611 wdata = (int)((len << 24) | aux_addr); 1612 writel(wdata, DP_AUX_ADDR_LEN); 1613 1614 writel(*aux_w_data, DP_AUX_W_D_0); 1615 1616 if ((*length) > 0x4) { 1617 aux_w_data++; 1618 writel(*aux_w_data, DP_AUX_W_D_4); 1619 } 1620 1621 if ((*length) > 0x8) { 1622 aux_w_data++; 1623 writel(*aux_w_data, DP_AUX_W_D_8); 1624 } 1625 1626 if ((*length) > 0xC) { 1627 aux_w_data++; 1628 writel(*aux_w_data, DP_AUX_W_D_C); 1629 } 1630 1631 /* Fire AUX write */ 1632 writel(aux_cmd, DP_AUX_REQ_CFG); 1633 1634 /* Wait AUX write finish or timeout */ 1635 do { 1636 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1637 } while (!(temp & 0xC000)); 1638 1639 /* Clear AUX write interrupt status */ 1640 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1641 writel(wdata, DP_TX_INT_CLEAR); 1642 1643 if (temp & AUX_CMD_DONE) { 1644 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1645 return 0; 1646 } else { 1647 return 1; 1648 } 1649 } 1650 1651 U_BOOT_CMD(dptest, 2, 0, do_ast_dptest, "ASPEED Display Port phy test", "ASPEED DP test v.0.2.9"); 1652