1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <exports.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <reset.h> 12 #include <fdtdec.h> 13 #include <asm/io.h> 14 15 #include "dptest.h" 16 17 /* Version info*/ 18 #define MAINVER 0 19 #define SUBVER 2 20 #define TEMPVER 9 21 22 #define YEAR 2022 23 #define MONTH 04 24 #define DAY 8 25 26 /* Compile define */ 27 /* #define RE_DRIVER */ 28 /* #define INTERNAL */ 29 30 /* Debug define */ 31 #define DBG_Print 32 33 #define DBG_ERR 0x00000001 /* DBG_ERROR */ 34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */ 35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */ 36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */ 37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */ 38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */ 39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */ 40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */ 41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */ 42 /* #define DBG_AUX_W 0x00002000 *//*DBG_AUX_W_VALUE */ 43 44 int DBG_LEVEL = 0x00000040; /* Information and stage */ 45 /* int DBG_LEVEL = 0x0000107F; *//*Fully */ 46 /* int DBG_LEVEL = 0x00000001; *//*Error */ 47 48 #ifdef DBG_Print 49 #define DBG(Level, format, args...) if ((Level) & DBG_LEVEL) printf(format, ##args) 50 #else 51 #define DBG(Level, format, args...) 52 #endif 53 54 int PHY_Cfg_N; 55 int PHY_Cfg; 56 int PHY_Cfg_1; 57 int TX_SSCG_Cfg; 58 int DP_Rate; 59 int Deemphasis_Level; 60 int Deemphasis_Level_1; 61 int Deemphasis_Show; 62 int Deemphasis_RD; 63 int Swing_Level; 64 int SSCG; 65 int Current_Item; 66 int GFlag; 67 uchar EDID[256]; 68 69 int I2C_PORT;/* I2c port */ 70 int I2C_BASE; 71 int I2C_BUFF; 72 uchar RD_VAL; 73 74 /* Record DP Sink status */ 75 uchar bEn_Frame; 76 uchar Link_Aux_RD_Val; 77 uchar CR_EQ_Keep; 78 int Deemlevel[3] = {DP_DEEMP_2, DP_DEEMP_0, DP_DEEMP_1}; 79 uchar Auto_Link_Rate; 80 uchar Auto_Lane_Count; 81 /* uchar Patch_Normal_Behavior; */ 82 83 static int 84 do_ast_dptest(cmd_tbl_t *cmdtp, int flags, int argc, char *const argv[]) 85 { 86 char received = 0; 87 char execute_test = 0; 88 int flag = 0, i; 89 char *Temp = NULL; 90 91 /* Default setting */ 92 DP_Rate = DP_RATE_1_62; 93 94 Deemphasis_Show = DP_DEEMP_0; 95 Deemphasis_Level = DP_DEEMP_0; 96 Deemphasis_Level_1 = DP_DEEMP_2; 97 Swing_Level = 2; 98 SSCG = DP_SSCG_OFF; 99 100 /* Obtain the argc / argv */ 101 for (i = 1; i < argc; i++) { 102 if (argv[i][0] == '-') { 103 switch (argv[i][1]) { 104 case 'D': 105 case 'd': 106 Temp = (char *)&argv[i][2]; 107 DBG_LEVEL = (int)(strtoul(Temp, NULL, 16)); 108 DBG_LEVEL |= DBG_ERR; /* Add must print. */ 109 printf("DBG_LEVEL change into 0x%x\n", DBG_LEVEL); 110 break; 111 case 'R': 112 case 'r': 113 Temp = (char *)&argv[i][2]; 114 I2C_PORT = (int)(strtoul(Temp, NULL, 16)); 115 printf("I2C_PORT change into 0x%x\n", I2C_PORT); 116 break; 117 default: 118 I2C_PORT = 0x0; 119 break; 120 } 121 } 122 } 123 124 printf("ASPEED DP Physical Layer Test Tool V %d.%d.%d\n", MAINVER, SUBVER, TEMPVER); 125 #ifdef INTERNAL 126 printf("Internal Version\n"); 127 #endif 128 129 printf("Build Date: %d.%d.%d\n\n", YEAR, MONTH, DAY); 130 131 printf("PLEASE REFER USER MANUAL BEFORE TEST!!\n\n"); 132 133 /* DP TX MCU reset */ 134 DPTX_MCU_Reset(); 135 printf("DP TX MCU Initial Done!\n"); 136 137 /* DP phy set */ 138 DPPHY_Set(); 139 printf("DP Physcial Config Done!\n"); 140 141 printf("Press ESC key to leave test ...\n\n"); 142 143 // While for auto testing 144 while (1) { 145 if (tstc()) { 146 received = getc(); 147 148 /* printf("Press %d\n",received); */ 149 150 /* Set parameters path */ 151 if (received >= 49 && received <= 57) { 152 switch (received) { 153 /* Press "1" : Set DP_Rate as 1.62 */ 154 case '1': 155 DP_Rate = DP_RATE_1_62; 156 PRINT_RATE_1_62; 157 break; 158 /* Press "2" : Set DP_Rate as 2.701 */ 159 case '2': 160 DP_Rate = DP_RATE_2_70; 161 PRINT_RATE_2_70; 162 break; 163 /* Press "3" : Set DP_Rate as 5.40 */ 164 /* case '3': */ 165 /* DP_Rate = DP_RATE_5_40; */ 166 /* PRINT_RATE_5_40 */ 167 /* break; */ 168 #ifdef INTERNAL 169 /* Press "4" : Set Deemphasis_Level as 1 / Deemphasis_Level_1 as 2 */ 170 case '4': 171 Deemphasis_Level = DP_DEEMP_1; 172 Deemphasis_Level_1 = DP_DEEMP_2; 173 Deemphasis_Show = DP_DEEMP_0; 174 Deemphasis_RD = Deemphasis_Show; 175 PRINT_DEEMP_0; 176 break; 177 /* Press "5" : Set Deemphasis_Level as 0 / Deemphasis_Level_1 as 0 */ 178 case '5': 179 Deemphasis_Level = DP_DEEMP_0; 180 Deemphasis_Level_1 = DP_DEEMP_0; 181 Deemphasis_Show = DP_DEEMP_1; 182 Deemphasis_RD = Deemphasis_Show; 183 PRINT_DEEMP_1; 184 break; 185 /* Press "6" : Set Deemphasis_Level as 2 / Deemphasis_Level_1 as 1 */ 186 case '6': 187 Deemphasis_Level = DP_DEEMP_2; 188 Deemphasis_Level_1 = DP_DEEMP_1; 189 Deemphasis_Show = DP_DEEMP_2; 190 Deemphasis_RD = Deemphasis_Show; 191 PRINT_DEEMP_2; 192 break; 193 /* Press "7" : Set Swing as 0 */ 194 case '7': 195 Swing_Level = 0; 196 PRINT_SWING_0; 197 break; 198 /* Press "8" : Set Swing as 1 */ 199 case '8': 200 Swing_Level = 1; 201 PRINT_SWING_1; 202 break; 203 /* Press "9" : Set Swing as 2 */ 204 case '9': 205 Swing_Level = 2; 206 PRINT_SWING_2; 207 break; 208 #endif 209 default: 210 break; 211 } 212 213 if (execute_test) 214 printf("The parameter is applied next measure!\n"); 215 216 } else if (received == '!') /* show config */ { 217 if (execute_test) 218 printf("Measurement is executed!\n"); 219 else 220 printf("Measurement is stopped!\n"); 221 222 DPPHYTX_Show_Cfg(); 223 } else if (received == '0') /* change sscfg */ { 224 if (SSCG == DP_SSCG_ON) { 225 SSCG = DP_SSCG_OFF; 226 PRINT_SSCG_OFF; 227 } else { 228 SSCG = DP_SSCG_ON; 229 PRINT_SSCG_ON; 230 } 231 232 /* SSCG could be applied without reset device. */ 233 if (execute_test) { 234 printf("Apply SSCG into current measurement !\n\n"); 235 TX_SSCG_Cfg = DP_TX_RDY_TEST; 236 TX_SSCG_Cfg |= SSCG; 237 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 238 } 239 } else { 240 /* Check the ESC key */ 241 if (received == 27) { 242 execute_test = 0; 243 DPTX_MCU_Reset(); 244 printf("'ESC' is pressed!\n"); 245 break; 246 } 247 248 /* If the test is execute, reset it */ 249 if (execute_test) { 250 execute_test = 0; 251 DPTX_MCU_Reset(); 252 253 printf("Stop current measurement !\n\n\n\n\n\n"); 254 } 255 256 /* Clear flag */ 257 flag = 0; 258 259 Current_Item = received; 260 261 switch (received) { 262 case 'a': 263 flag = (F_EMPHASIS_NULL | F_PAT_PRBS7); 264 break; 265 #ifdef INTERNAL 266 case 'b': 267 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 268 break; 269 270 case 'c': /* Eye Diagram Test w/t w/o Cable - HBR2CPAT */ 271 flag = (F_EMPHASIS_1 | F_PAT_HBR2CPAT); 272 break; 273 274 case 'd': 275 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT); 276 break; 277 278 case 'e': /* Non-Transition Voltage Range Measurement - PLTPAT */ 279 flag = (F_EMPHASIS | F_PAT_PLTPAT); 280 break; 281 282 case 'f': /* Pre-Emphasis Level Test and Pre-Emphasis Level Delta Test- PRBS7 */ 283 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 284 break; 285 286 case 'g': /* Non-Transition Voltage Range Measurement - PRBS7 */ 287 flag = (F_EMPHASIS | F_PAT_PRBS7); 288 break; 289 290 case 'h': /* Total - PRBS7 */ 291 flag = (F_EMPHASIS_1 | F_PAT_D10_2); 292 break; 293 294 case 'i': 295 printf("Change the Swing value from request\n"); 296 flag = (F_EMPHASIS_1 | F_PAT_PRBS7 | F_SHOW_SWING); 297 break; 298 299 case 'j': 300 printf("Change the Swing value from request\n"); 301 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT | DP_TX_HIGH_SPEED | F_SHOW_SWING); 302 break; 303 304 case 'k': 305 flag = F_PAT_AUX; 306 break; 307 #endif 308 case 'x': /* Auto hand shaking with DPR-100 */ 309 flag = F_EXE_AUTO; 310 break; 311 312 default: 313 printf("Non - define command!\n"); 314 break; 315 } 316 317 // Execute testing 318 if (flag) { 319 execute_test = 1; 320 GFlag = flag; 321 322 if (flag & F_PAT_AUX) { 323 printf("######################################\n"); 324 printf("#Current DP TX setting is shown below#\n"); 325 printf("######################################\n\n"); 326 327 DPPHYTX_Show_Item(Current_Item); 328 Apply_AUX_Mesument(flag); 329 } else if (flag & F_EXE_AUTO) { 330 printf("#########################\n"); 331 printf("#Enter DP TX Auto Test!!#\n"); 332 printf("#########################\n\n"); 333 334 Apply_Auto_Preset(0x1); 335 Apply_Auto_Mesument(); 336 Apply_Auto_Preset(0x0); 337 338 printf("#########################\n"); 339 printf("#Leave DP TX Auto Test!!#\n"); 340 printf("#########################\n\n"); 341 } else { 342 DPPHYTX_Show_Cfg(); 343 Apply_Main_Mesument(flag); 344 } 345 } 346 } 347 } 348 mdelay(200); 349 }; 350 351 printf("\n\n"); 352 return 0; 353 } 354 355 /* Temp for cording here */ 356 void Apply_Auto_Preset(char Init) 357 { 358 /* Fill some nessary register value for auto test */ 359 if (Init) { 360 /* Enable MCU received interrupt */ 361 writel(0x00e80000, DP_TX_INT_CLEAR); 362 363 /* Set HPD irq time interval */ 364 writel(0x04e300fb, DP_TX_IRQ_CFG); 365 366 /* Set HPD event time interval */ 367 writel(0x000007d1, DP_TX_EVENT_CFG); 368 } else { 369 /* Recover */ 370 writel(0x0, DP_TX_INT_CLEAR); 371 writel(0x0, DP_TX_IRQ_CFG); 372 writel(0x0, DP_TX_EVENT_CFG); 373 } 374 } 375 376 /* READ EDID */ 377 void Read_EDID_128(char Offset) 378 { 379 char AUX_Data[16] = {0}; 380 uchar Length = 1; 381 uchar Status = 0; 382 uchar i, j; 383 384 DBG(DBG_A_EDID, "R EDID Offset %d\n", Offset); 385 386 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 387 388 AUX_Data[0] = Offset; 389 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 390 391 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 392 393 Length = 16; 394 395 // Read 128 bytes block 396 for (i = 0; i < 8; i++) { 397 do { 398 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 399 DBG(DBG_A_EDID, "EDID read %d!\n", i); 400 401 udelay(100); 402 } while (Status == 0x20); 403 404 /* copy from temp into EDID */ 405 for (j = 0; j < 16; j++) 406 EDID[Offset + i * 16 + j] = AUX_Data[j]; 407 } 408 409 Length = 1; 410 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 411 } 412 413 void Apply_EDID_Reading(void) 414 { 415 char AUX_Data[16] = {0}; 416 uchar Length = 1; 417 uchar Status = 0; 418 419 DBG(DBG_STAGE, "Apply EDID Reading!\n"); 420 421 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 422 423 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 424 425 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 426 427 /* Check read EDID header */ 428 Length = 4; 429 do { 430 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 431 432 udelay(100); 433 } while (Status == 0x20); 434 435 DBG(DBG_A_EDID, "EDID First 4 is 0x%X_0x%X_0x%X_0x%X\n", AUX_Data[0], AUX_Data[1], AUX_Data[2], AUX_Data[3]); 436 437 Length = 1; 438 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 439 440 DBG(DBG_A_EDID, "Read 128!\n"); 441 Read_EDID_128(0x0); 442 443 /* If the extension bit is set, then read back next block */ 444 if (EDID[0x7E] == 0x1) { 445 DBG(DBG_A_EDID, "Read 256!\n"); 446 Read_EDID_128(0x80); 447 } 448 } 449 450 /* LINK TRAIN */ 451 uchar Adjust_CR_EQ_Train(int TrainPat, uchar ADJStatus) 452 { 453 char AUX_Data[16] = {0}; 454 uchar Ret = 0; 455 uchar Length = 1; 456 uchar Status = 0; 457 uchar AUX_R_Level = 0; 458 uchar AUX_W_Level = 0; 459 uchar DE_Level = 0x0; 460 uchar CR_Status = 0; 461 int value = 0; 462 uchar bFirst = 1; 463 uchar tempkeep = 0; 464 465 /* Set the main link pattern with TPS1 / TPS2 for Lanex_CR_Done */ 466 value = ((readl(DP_TX_MAIN_PAT) & ~(0x30000000)) | TrainPat); 467 writel(value, DP_TX_MAIN_PAT); 468 DBG(DBG_A_SUB, "1.A_C_E Set Link Pattern\n"); 469 470 /* AST phy 0xE4 Bit28 (0x1000000) / DP 0x102 Bit0 : TPS1 */ 471 /* AST phy 0xE4 Bit29 (0x2000000) / DP 0x102 Bit1 : TPS2 */ 472 if (TrainPat == 0x10000000) 473 AUX_Data[0] = 0x21; 474 else 475 AUX_Data[0] = 0x22; 476 477 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 478 DBG(DBG_A_SUB, "2.A_C_E W 0x102 set 0x%x\n", AUX_Data[0]); 479 480 /* First */ 481 if (bFirst) { 482 Length = 4; 483 484 AUX_Data[0] = CR_EQ_Keep; 485 AUX_Data[1] = CR_EQ_Keep; 486 AUX_Data[2] = CR_EQ_Keep; 487 AUX_Data[3] = CR_EQ_Keep; 488 tempkeep = CR_EQ_Keep; 489 490 do { 491 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 492 DBG(DBG_A_SUB, "3.A_C_E W 0x103 - 0x106 set\n"); 493 } while (Status == 0x20); 494 495 Length = 6; 496 497 udelay(1200); 498 499 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 500 DBG(DBG_A_SUB, "4.A_C_E R 0x200 - 0x205 read back\n"); 501 502 if ((AUX_Data[2] & ADJStatus) == ADJStatus) { 503 CR_EQ_Keep = tempkeep; 504 return Ret; 505 } 506 507 bFirst = 0; 508 } 509 510 /* loop for CR_lock */ 511 do { 512 Length = 1; 513 514 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 515 DBG(DBG_A_SUB, "5.A_C_E R 0x206 read back\n"); 516 AUX_R_Level = AUX_Data[0]; 517 518 AUX_R(AUX_CMD_R, 0x207, (int *)(&AUX_Data), &Length, &Status); 519 DBG(DBG_A_SUB, "6.A_C_E R 0x207 read back\n"); 520 521 /* Update SW Level */ 522 switch (AUX_R_Level & 0x33) { 523 case 0x00: 524 AUX_W_Level = 00; 525 break; 526 case 0x11: 527 AUX_W_Level = 01; 528 break; 529 default: 530 AUX_W_Level = 06; 531 break; 532 } 533 534 /* Update SW Level */ 535 switch (AUX_R_Level & 0xCC) { 536 case 0x00: 537 /* AUX_W_Level |= 00; */ 538 DE_Level = 0; 539 break; 540 case 0x44: 541 AUX_W_Level |= 0x08; 542 DE_Level = 1; 543 break; 544 default: 545 AUX_W_Level |= 0x30; 546 DE_Level = 2; 547 break; 548 } 549 550 /* Set the de-emphsis value */ 551 value = ((readl(DP_TX_PHY_CFG) & ~(0x33000000)) | Deemlevel[DE_Level]); 552 writel(value, DP_TX_PHY_CFG); 553 DBG(DBG_A_SUB, "6.A_C_E Set Phy config %d\n", DE_Level); 554 555 DBG(DBG_A_SUB, "Link AUX_W_Level is 0x%x\n", AUX_W_Level); 556 557 Length = 4; 558 559 AUX_Data[0] = AUX_W_Level; 560 AUX_Data[1] = AUX_W_Level; 561 AUX_Data[2] = AUX_W_Level; 562 AUX_Data[3] = AUX_W_Level; 563 tempkeep = AUX_W_Level; 564 565 do { 566 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 567 DBG(DBG_A_SUB, "7.A_C_E W 0x103 - 0x106 set\n"); 568 } while (Status == 0x20); 569 570 udelay(1380); 571 572 Length = 6; 573 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 574 DBG(DBG_A_SUB, "8.A_C_E R 0x200 - 0x205 read back\n"); 575 576 CR_Status = AUX_Data[2] & ADJStatus; 577 578 /* Decrease speed because the deemphasis level reach max value */ 579 if (AUX_W_Level == 0x36) { 580 Ret = 1; 581 break; 582 } 583 584 } while (CR_Status != ADJStatus); 585 586 CR_EQ_Keep = tempkeep; 587 588 return Ret; 589 } 590 591 uchar Link_Train_Flow(char Link_Level) 592 { 593 char AUX_Data[16] = {0}; 594 uchar Length = 1; 595 uchar Status = 0; 596 uchar Ret = 0; 597 int value = 0; 598 599 DBG(DBG_STAGE, "Link train flow! Level : %d\n", Link_Level); 600 601 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 602 DBG(DBG_A_SUB, "1.Link R 0x101 read back\n"); 603 604 /* Normal / Test case */ 605 if (Auto_Lane_Count) 606 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 607 else 608 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 609 610 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 611 DBG(DBG_A_SUB, "2.Link W 0x101 clear\n"); 612 613 /* Set different clock bit rate */ 614 value = ((readl(DP_TX_MAIN_SET) & ~(0x300)) | (Link_Level << 8)); 615 writel(value, DP_TX_MAIN_SET); 616 617 switch (Link_Level) { 618 case 0x1: /* 2.7 */ 619 AUX_Data[0] = 0x0a; 620 break; 621 622 default: /* 1.62 */ 623 AUX_Data[0] = 0x06; 624 break; 625 } 626 627 AUX_W(AUX_CMD_W, 0x100, (int *)(&AUX_Data), &Length, &Status); 628 DBG(DBG_A_SUB, "3.Link W 0x100 set\n"); 629 630 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 631 DBG(DBG_A_SUB, "4.Link R 0x101 read back\n"); 632 633 /* Normal / Test case */ 634 if (Auto_Lane_Count) 635 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 636 else 637 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 638 639 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 640 DBG(DBG_A_SUB, "5.Link W 0x101 clear\n"); 641 642 /* Set the 2 lanes and enhance frame by checking AUX 0x2 bit 7 */ 643 value = ((readl(DP_TX_MAIN_SET) & ~(0x1070)) | 0x20); 644 645 if (bEn_Frame) 646 value |= 0x1000; 647 648 writel(value, DP_TX_MAIN_SET); 649 650 value = ((readl(DP_TX_PHY_CFG) & ~(0x3000)) | 0x3000); 651 652 writel(value, DP_TX_PHY_CFG); 653 654 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 655 DBG(DBG_A_SUB, "6.Link R 0x101 read back\n"); 656 657 /* Normal / Test case */ 658 if (Auto_Lane_Count) 659 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 660 else 661 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 662 663 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 664 DBG(DBG_A_SUB, "7.Link W 0x101 clear\n"); 665 666 /* Set the main link control on */ 667 value = ((readl(DP_TX_PHY_SET) & ~(0x100)) | 0x100); 668 669 udelay(1000); 670 udelay(1500); 671 672 writel(value, DP_TX_PHY_SET); 673 674 do { 675 value = (readl(DP_TX_PHY_SET) & 0x200); 676 } while (value != 0x200); 677 DBG(DBG_A_SUB, "8.Link Main Link Ready\n"); 678 679 /* Adjust for CR */ 680 if (Adjust_CR_EQ_Train(0x10000000, 0x11)) { 681 Ret = 1; 682 return Ret; 683 } 684 685 /* Adjust for EQ */ 686 if (Adjust_CR_EQ_Train(0x20000000, 0x77)) { 687 Ret = 1; 688 return Ret; 689 } 690 691 return Ret; 692 } 693 694 void Apply_HPD_Normal(void) 695 { 696 char AUX_Data[16] = {0}; 697 uchar Length = 1; 698 uchar Status = 0; 699 int value = 0; 700 701 DBG(DBG_STAGE, "HPD Normal set!\n"); 702 703 AUX_Data[0] = 0x01; 704 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 705 DBG(DBG_NOR, "1.HPD_N W 0x600 set power!\n"); 706 707 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 708 DBG(DBG_NOR, "2.HPD_N R 0x0 read back is 0x%X!\n", AUX_Data[0]); 709 710 Length = 8; 711 AUX_R(AUX_CMD_R, 0x500, (int *)(&AUX_Data), &Length, &Status); 712 DBG(DBG_NOR, "3.HPD_N R 0x500 - 0x508 read back\n"); 713 714 Length = 14; 715 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 716 DBG(DBG_NOR, "4.HPD_N R 0x0 - 0xD read back\n"); 717 718 bEn_Frame = AUX_Data[2] & 0x80; 719 Link_Aux_RD_Val = AUX_Data[14]; 720 721 if (bEn_Frame) 722 DBG(DBG_NOR, "4.HPD_N R 0x2 En_Frame_Cap\n"); 723 724 Length = 1; 725 AUX_R(AUX_CMD_R, 0xe, (int *)(&AUX_Data), &Length, &Status); 726 DBG(DBG_NOR, "5.HPD_N R 0xE read back\n"); 727 728 /* Read EDID */ 729 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Enter\n"); 730 731 Apply_EDID_Reading(); 732 733 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Leave\n"); 734 735 Length = 2; 736 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 737 DBG(DBG_NOR, "7.HPD_N R 0x200 - 0x201 read back.\n"); 738 739 Length = 1; 740 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 741 DBG(DBG_NOR, "8.HPD_N R 0x68028 read back.\n"); 742 743 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 744 DBG(DBG_NOR, "9.HPD_N R 0x68028 read back.\n"); 745 746 AUX_R(AUX_CMD_R, 0x600, (int *)(&AUX_Data), &Length, &Status); 747 DBG(DBG_NOR, "10.HPD_N R 0x600 read back.\n"); 748 749 AUX_Data[0] = 0x01; 750 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 751 DBG(DBG_NOR, "11.HPD_N W 0x600 set power!\n"); 752 753 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Enter\n"); 754 755 Status = Link_Train_Flow(0x1); 756 757 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Leave\n"); 758 759 if (Status) { 760 AUX_Data[0] = 0x20; 761 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 762 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x1 Fail!!\n"); 763 764 DBG(DBG_NOR, "13.HPD_N Link_Train_Flow 0x0 Enter\n"); 765 766 Status = Link_Train_Flow(0x0); 767 768 DBG(DBG_NOR, "13.HPD_NLink_Train_Flow 0x0 Leave\n"); 769 770 if (Status) { 771 AUX_Data[0] = 0x20; 772 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 773 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x0 Fail!!\n"); 774 775 DBG(DBG_ERR, "### CAUTION!! LINK TRAN FAIL!! ###\n"); 776 777 return; 778 } 779 } 780 781 /* Link successful */ 782 AUX_Data[0] = 0x00; 783 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 784 DBG(DBG_NOR, "14.HPD_N W 0x102 clear!\n"); 785 786 /* Fill idle pattern */ 787 value = ((readl(DP_TX_MAIN_PAT) & ~(0x31000000)) | 0x01000000); 788 writel(value, DP_TX_MAIN_PAT); 789 DBG(DBG_NOR, "15.HPD_N Fill idle pattern!\n"); 790 791 Length = 1; 792 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 793 DBG(DBG_NOR, "16.HPD_N R 0x68028 read back.\n"); 794 795 Length = 5; 796 AUX_R(AUX_CMD_R, 0x68000, (int *)(&AUX_Data), &Length, &Status); 797 DBG(DBG_NOR, "17.HPD_N R 0x68000 - 0x68004 read back.\n"); 798 799 Length = 1; 800 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 801 DBG(DBG_NOR, "18.HPD_N R 0x68028 read back.\n"); 802 803 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 804 DBG(DBG_NOR, "19.HPD_N R 0x68028 read back.\n"); 805 806 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 807 DBG(DBG_NOR, "20.HPD_N R 0x0 read back.\n"); 808 } 809 810 void Apply_HPD_Auto_Test(void) 811 { 812 char AUX_Data[16]; 813 uchar Length = 0; 814 uchar Status = 0; 815 uchar clear_auto_test = 0; 816 uchar auto_test_link = 0; 817 uchar auto_test_phy = 0; 818 uchar swing0 = 0, preemphasis0 = 0; 819 uchar swing1 = 0, preemphasis1 = 0; 820 int flag = 0; 821 char temp0 = 0, temp1 = 0; 822 char temp206 = 0; 823 824 DBG(DBG_STAGE, "HPD Auto test set!\n"); 825 826 /* Set power D0 */ 827 AUX_Data[0] = 0x01; 828 Length = 1; 829 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 830 DBG(DBG_A_TEST, "1.HP_I W 0x600 done!\n"); 831 832 Length = 6; 833 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 834 DBG(DBG_A_TEST, "2.HP_I R 0x200 - 0x206 done!\n"); 835 836 Length = 1; 837 AUX_R(AUX_CMD_R, 0x201, (int *)(&AUX_Data), &Length, &Status); 838 DBG(DBG_A_TEST, "3.HP_I R 0x201 done!\n"); 839 840 /* Obtain auto test */ 841 if (AUX_Data[0] & 0x2) 842 clear_auto_test = 1; 843 else 844 clear_auto_test = 0; 845 846 /* Read dummy */ 847 Length = 3; 848 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 849 Length = 1; 850 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 851 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 852 Length = 3; 853 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 854 Length = 1; 855 AUX_R(AUX_CMD_R, 0x205, (int *)(&AUX_Data), &Length, &Status); 856 DBG(DBG_A_TEST, "4. HP_I R Dummy!\n"); 857 858 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 859 DBG(DBG_A_TEST, "5. HP_I Link Rate R 0x219 : 0x%x\n", AUX_Data[0]); 860 861 if (AUX_Data[0] == 0x06) { 862 Auto_Link_Rate = AUX_Data[0]; 863 DP_Rate = DP_RATE_1_62; 864 PRINT_RATE_1_62; 865 } else if (AUX_Data[0] == 0x0a) { 866 Auto_Link_Rate = AUX_Data[0]; 867 DP_Rate = DP_RATE_2_70; 868 PRINT_RATE_2_70; 869 } else if (AUX_Data[0] == 0x14) { 870 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 871 return; 872 } 873 874 if (clear_auto_test) { 875 AUX_Data[0] = 0x02; 876 AUX_W(AUX_CMD_W, 0x201, (int *)(&AUX_Data), &Length, &Status); 877 DBG(DBG_A_TEST, "1.HP_I CA W 0x201 clear auto!\n"); 878 clear_auto_test = 0; 879 880 /* Fetch Testing data */ 881 AUX_R(AUX_CMD_R, 0x218, (int *)(&AUX_Data), &Length, &Status); 882 DBG(DBG_A_TEST, "2.HP_I CA R 0x218 done!\n"); 883 884 /* Check auto test link flag */ 885 if (AUX_Data[0] & 0x1) 886 auto_test_link = 1; 887 else 888 auto_test_link = 0; 889 890 /* Check auto test phy flag */ 891 if (AUX_Data[0] & 0x8) 892 auto_test_phy = 1; 893 else 894 auto_test_phy = 0; 895 896 if (auto_test_link) { 897 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 898 DBG(DBG_A_TEST, "1.HP_I TL R 0x219 : 0x%x\n", AUX_Data[0]); 899 900 if (AUX_Data[0] == 0x06) { 901 Auto_Link_Rate = AUX_Data[0]; 902 DP_Rate = DP_RATE_1_62; 903 PRINT_RATE_1_62; 904 } else if (AUX_Data[0] == 0x0a) { 905 Auto_Link_Rate = AUX_Data[0]; 906 DP_Rate = DP_RATE_2_70; 907 PRINT_RATE_2_70; 908 } else if (AUX_Data[0] == 0x14) { 909 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 910 return; 911 } 912 913 AUX_R(AUX_CMD_R, 0x220, (int *)(&AUX_Data), &Length, &Status); 914 DBG(DBG_A_TEST, "2.HP_I TL R 0x220 : 0x%x\n", AUX_Data[0]); 915 Auto_Lane_Count = AUX_Data[0] & 0x1F; 916 917 AUX_Data[0] = 0x01; 918 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 919 DBG(DBG_A_TEST, "3.HP_I TL W 0x260 test ACK\n"); 920 921 mdelay(95); 922 923 /* Set power D0 */ 924 AUX_Data[0] = 0x01; 925 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 926 DBG(DBG_A_TEST, "3.1 HP_I W 0x600 done!\n"); 927 928 switch (Auto_Link_Rate) { 929 case 0x06: 930 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Enter\n"); 931 Status = Link_Train_Flow(0x0); 932 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Leave\n"); 933 break; 934 935 case 0x0a: 936 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Enter\n"); 937 Status = Link_Train_Flow(0x1); 938 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Leave\n"); 939 break; 940 941 default: 942 DBG(DBG_ERR, "!!BAD LINK RATE!!\n"); 943 return; 944 } 945 946 if (Status) { 947 DBG(DBG_ERR, "!!AUTO TEST LINK FAIL!!\n"); 948 return; 949 } 950 951 /* Link successful */ 952 AUX_Data[0] = 0x00; 953 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 954 DBG(DBG_A_TEST, "5.HP_I TL Link clear!\n"); 955 956 auto_test_link = 0; 957 } 958 959 if (auto_test_phy) { 960 Length = 1; 961 flag = 0; 962 temp206 = 0; 963 964 AUX_R(AUX_CMD_R, 0x248, (int *)(&AUX_Data), &Length, &Status); 965 DBG(DBG_A_TEST, "1.HP_I TP R 0x248 : 0x%x!\n", AUX_Data[0]); 966 967 if (AUX_Data[0] == 0x01) { 968 flag |= F_PAT_D10_2; 969 DBG(DBG_A_TEST, "HP_I TP D10.2!\n"); 970 } else if (AUX_Data[0] == 0x03) { 971 flag |= F_PAT_PRBS7; 972 DBG(DBG_A_TEST, "HP_I TP PRBS7!\n"); 973 } 974 975 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 976 DBG(DBG_A_TEST, "2.HP_I TP R 0x206 : 0x%x!\n", AUX_Data[0]); 977 978 /* Temp for verified */ 979 DBG(DBG_INF, "Read value 0x206 : 0x%x!\n", AUX_Data[0]); 980 981 /* Check Swing */ 982 temp0 = (AUX_Data[0] & 0x03); 983 temp1 = (AUX_Data[0] & 0x30); 984 985 /* Check Swing0 */ 986 switch (temp0) { 987 case 0x2: 988 swing0 = 0x2; 989 temp206 |= 6; 990 break; 991 case 0x1: 992 swing0 = 0x1; 993 temp206 |= 1; 994 break; 995 case 0x0: 996 swing0 = 0x0; 997 break; 998 default: 999 DBG(DBG_ERR, "HP_I TP 0x206 other swing0 val %x!\n", temp0); 1000 break; 1001 } 1002 1003 /* Check Swing1 */ 1004 switch (temp1) { 1005 case 0x20: 1006 swing1 = 0x2; 1007 temp206 |= 6; 1008 break; 1009 case 0x10: 1010 swing1 = 0x1; 1011 temp206 |= 1; 1012 break; 1013 case 0x00: 1014 swing1 = 0x0; 1015 break; 1016 default: 1017 DBG(DBG_ERR, "HP_I TP 0x206 other swing1 val %x!\n", temp1); 1018 break; 1019 } 1020 1021 if (swing0 != swing1) 1022 DBG(DBG_ERR, "Swing 0 / 1 diff val %x!\n", AUX_Data[0]); 1023 1024 /* Check Pre-emphasis */ 1025 temp0 = (AUX_Data[0] & 0x0C); 1026 temp1 = (AUX_Data[0] & 0xC0); 1027 1028 /* Check Pre-emphasis0 */ 1029 switch (temp0) { 1030 case 0x8: 1031 preemphasis0 = 0x2; 1032 temp206 |= 0x30; 1033 break; 1034 case 0x4: 1035 preemphasis0 = 0x1; 1036 temp206 |= 0x08; 1037 break; 1038 case 0x0: 1039 preemphasis0 = 0x0; 1040 break; 1041 default: 1042 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis0 val %x!\n", temp0); 1043 break; 1044 } 1045 1046 /* Check Pre-emphasis1 */ 1047 switch (temp1) { 1048 case 0x80: 1049 preemphasis1 = 0x2; 1050 temp206 |= 0x30; 1051 break; 1052 case 0x40: 1053 preemphasis1 = 0x1; 1054 temp206 |= 0x08; 1055 break; 1056 case 0x00: 1057 preemphasis1 = 0x0; 1058 break; 1059 default: 1060 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis1 val %x!\n", temp1); 1061 break; 1062 } 1063 1064 if (preemphasis0 != preemphasis1) 1065 DBG(DBG_ERR, "Preemphasis 0 / 1 diff val %x!\n", AUX_Data[0]); 1066 1067 /* Judgement */ 1068 if (swing0 == 0x2 || swing1 == 0x2) 1069 Swing_Level = 0x2; 1070 else if (swing0 == 1 || swing1 == 0x1) 1071 Swing_Level = 0x1; 1072 else if (swing0 == 0x0 || swing1 == 0x0) 1073 Swing_Level = 0x0; 1074 1075 if (preemphasis0 == 0x2 || preemphasis1 == 0x2) { 1076 Deemphasis_RD = DP_DEEMP_2; 1077 Deemphasis_Level_1 = DP_DEEMP_1; 1078 DBG(DBG_ERR, "!!De-type 1 P_2 !!\n"); 1079 } else if (preemphasis0 == 0x1 || preemphasis1 == 0x1) { 1080 Deemphasis_RD = DP_DEEMP_1; 1081 Deemphasis_Level_1 = DP_DEEMP_0; 1082 DBG(DBG_ERR, "!!De-type 0 P_1 !!\n"); 1083 } else if (preemphasis0 == 0x0 || preemphasis1 == 0x0) { 1084 Deemphasis_RD = DP_DEEMP_0; 1085 Deemphasis_Level_1 = DP_DEEMP_2; 1086 DBG(DBG_ERR, "!!De-type 2 P_0 !!\n"); 1087 } 1088 1089 DBG(DBG_INF, "!!Swing %d / Pre-emphasis %d !!\n", swing0, preemphasis0); 1090 1091 flag |= F_EMPHASIS_1; 1092 1093 AUX_R(AUX_CMD_R, 0x102, (int *)(&AUX_Data), &Length, &Status); 1094 DBG(DBG_A_TEST, "3.HP_I TP R 0x102 done!\n"); 1095 temp0 = AUX_Data[0]; 1096 1097 Length = 2; 1098 AUX_R(AUX_CMD_R, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1099 DBG(DBG_A_TEST, "4.HP_I TP R 0x10b done!\n"); 1100 1101 AUX_W(AUX_CMD_W, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1102 DBG(DBG_A_TEST, "5.HP_I TP W 0x10b done!\n"); 1103 1104 AUX_Data[0] = temp0 | 0x20; 1105 Length = 1; 1106 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 1107 DBG(DBG_A_TEST, "6.HP_I TP W 0x102 done!\n"); 1108 1109 AUX_Data[0] = temp206; 1110 AUX_Data[1] = temp206; 1111 Length = 2; 1112 1113 do { 1114 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 1115 DBG(DBG_A_TEST, "7.HP_I TP W 0x103 - 0x104 done!\n"); 1116 } while (Status == 0x20); 1117 1118 DPPHYTX_Show_Cfg(); 1119 Apply_Main_Mesument(flag); 1120 1121 Length = 1; 1122 AUX_Data[0] = 0x01; 1123 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 1124 DBG(DBG_A_TEST, "8.HP_I TP W 0x260 done!\n"); 1125 1126 DBG(DBG_STAGE, "Leave Apply Auto Test\n"); 1127 1128 auto_test_phy = 0; 1129 } 1130 clear_auto_test = 0; 1131 } 1132 } 1133 1134 /* TEST SECTION */ 1135 void Apply_Auto_Mesument(void) 1136 { 1137 char auto_received = 0; 1138 int temp = 0, wdata = 0; 1139 int breakcount = 0; 1140 1141 while (1) { 1142 breakcount = 0; 1143 1144 /* Wait HPD */ 1145 do { 1146 temp = (readl(DP_TX_INT_STATUS) & 0x3800); 1147 breakcount++; 1148 1149 if (breakcount == 0x96000) { 1150 /* A simple break for esc press received */ 1151 break; 1152 } 1153 1154 } while (!(temp & 0x3800)); 1155 1156 if (temp) { 1157 /* Clear AUX write interrupt status */ 1158 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1159 writel(wdata, DP_TX_INT_CLEAR); 1160 } 1161 1162 /* Interrupt occur */ 1163 if (temp & 0x2800) { 1164 /* Initial global parameter */ 1165 Auto_Link_Rate = 0; 1166 Auto_Lane_Count = 0; 1167 bEn_Frame = 0; 1168 CR_EQ_Keep = 0; 1169 1170 if (temp & 0x2000) { 1171 printf("DP HPD event is detected!\n"); 1172 Apply_HPD_Normal(); 1173 } 1174 1175 if (temp & 0x800) { 1176 printf("DP HPD irq is detected!\n"); 1177 Apply_HPD_Auto_Test(); 1178 } 1179 } 1180 1181 /* Leave auto test if the 'ESC' is pressed */ 1182 if (tstc()) { 1183 auto_received = getc(); 1184 1185 /* Check the ESC key */ 1186 if (auto_received == 27) { 1187 printf("'ESC' is pressed under auto test!\n\n"); 1188 return; 1189 } 1190 1191 printf("DP TX auto test is executed!\n"); 1192 } 1193 } 1194 } 1195 1196 void Apply_Main_Mesument(int flag) 1197 { 1198 DPTX_MCU_Reset(); 1199 1200 /* Emphasis setting */ 1201 if (flag & F_EMPHASIS_NULL) 1202 writel(PHY_Cfg_N, DP_TX_PHY_CFG); 1203 else if (flag & F_EMPHASIS) 1204 writel(PHY_Cfg, DP_TX_PHY_CFG); 1205 else if (flag & F_EMPHASIS_1) 1206 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1207 1208 if (flag & F_RES_HIGH) 1209 writel(DP_TX_HIGH_SPEED, DP_TX_RES_CFG); 1210 else 1211 writel(DP_TX_NOR_SPEED, DP_TX_RES_CFG); 1212 1213 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1214 1215 DPPHY_Set(); 1216 1217 if (flag & F_PAT_PRBS7) 1218 Set_PRBS7(); 1219 else if (flag & F_PAT_PLTPAT) 1220 Set_PLTPAT(); 1221 else if (flag & F_PAT_HBR2CPAT) 1222 Set_HBR2CPAT(); 1223 else if (flag & F_PAT_D10_2) 1224 Set_D10_1(); 1225 1226 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 1227 } 1228 1229 void Apply_AUX_Mesument(int flag) 1230 { 1231 DPTX_MCU_Reset(); 1232 DPPHY_Set(); 1233 1234 writel(0x0F000000, DP_AUX_ADDR_LEN); 1235 writel(0x80000010, DP_AUX_REQ_CFG); 1236 } 1237 1238 /* FUNCTION SECTION */ 1239 /* i2c set */ 1240 #ifdef RE_DRIVER 1241 void Set_Redriver(void) 1242 { 1243 int value = 0x0; 1244 uchar offset = 0x0; 1245 uchar *set_table = &set_table0; 1246 1247 if (Deemphasis_RD == DP_DEEMP_1) 1248 set_table = &set_table1; 1249 else if (Deemphasis_RD == DP_DEEMP_2) 1250 set_table = &set_table2; 1251 1252 RD_VAL = set_table[Swing_Level]; 1253 1254 printf("RD_VAL is 0x%x\n", RD_VAL); 1255 1256 writel(0x600, I2C_BASE + I2C0_COUNT_O); 1257 value = (0x0000f0f0 | (RD_VAL << 24)); 1258 writel(value, I2C_BUFF); 1259 printf("value0 is 0x%x\n", value); 1260 value = (RD_VAL | (RD_VAL << 8) | (RD_VAL << 16) | (RD_VAL << 24)); 1261 writel(value, (I2C_BUFF + 0x4)); 1262 printf("value1 is 0x%x\n", value); 1263 writel(0x70010063, (I2C_BASE + I2C0_EXECUTE_O)); 1264 mdelay(1000); 1265 } 1266 1267 /* i2c single initial */ 1268 void I2C_L_Initial(void) 1269 { 1270 I2C_BASE = (I2C0_BASE + (I2C_DEV_OFFSET * I2C_PORT)); 1271 I2C_BUFF = (I2C0_BUFF + (I2C_BUFF_OFFSET * I2C_PORT)); 1272 1273 writel(0x0, I2C_BASE); 1274 mdelay(1); 1275 writel(0x28001, I2C_BASE); 1276 writel(0x344001, I2C_BASE + I2C0_TIMMING_O); 1277 writel(0xFFFFFFFF, I2C_BASE + I2C0_INT_STATUS_O); 1278 writel(0x0, I2C_BASE + I2C0_INT_O); 1279 mdelay(10); 1280 } 1281 1282 /* i2c golbal iniitial */ 1283 void I2C_G_Initial(void) 1284 { 1285 /* i2c multi-function */ 1286 writel(0x0FFF3000, MP_SCU410); 1287 writel(0x0F00FF00, MP_SCU414); 1288 writel(0xCFFF001F, MP_SCU418); 1289 writel(0xF00000FF, MP_SCU4b0); 1290 writel(0xF0FF00FF, MP_SCU4b4); 1291 writel(0x0000FF00, MP_SCU4b8); 1292 1293 /* I2c control */ 1294 writel(0x16, (I2C_GBASE + 0xC)); 1295 writel(0x041230C6, (I2C_GBASE + 0x10)); 1296 1297 mdelay(1000); 1298 } 1299 #endif 1300 1301 void DPTX_MCU_Reset(void) 1302 { 1303 /* Reset DPMCU & Release DPTX */ 1304 writel(0x20000000, SYS_REST); 1305 writel(0x10000000, SYS_REST_CLR); 1306 1307 /* Wait for apply setting */ 1308 mdelay(1000); 1309 } 1310 1311 void DPPHY_Set(void) 1312 { 1313 int value = 0, count = 0; 1314 1315 /* Clear power on reset */ 1316 writel(0x10000000, DP_TX_PHY_SET); 1317 mdelay(1); 1318 1319 /* Clear DPTX reset */ 1320 writel(0x11000000, DP_TX_PHY_SET); 1321 mdelay(1); 1322 1323 /* Turn on Main link / Aux channel */ 1324 writel(0x11001100, DP_TX_PHY_SET); 1325 mdelay(1); 1326 1327 while (value != DP_TX_RDY_TEST) { 1328 value = readl(DP_TX_PHY_SET); 1329 mdelay(1); 1330 count++; 1331 } 1332 } 1333 1334 char DPPHYTX_Show_Cfg(void) 1335 { 1336 char SetFail = 0; 1337 1338 PHY_Cfg = DP_PHY_INIT_CFG; 1339 PHY_Cfg_1 = DP_PHY_INIT_CFG; 1340 TX_SSCG_Cfg = DP_TX_RDY_TEST; 1341 1342 /* Show the setting */ 1343 1344 printf("######################################\n"); 1345 printf("#Current DP TX setting is shown below#\n"); 1346 printf("######################################\n\n"); 1347 1348 DPPHYTX_Show_Item(Current_Item); 1349 1350 switch (DP_Rate) { 1351 case DP_RATE_1_62: 1352 PRINT_RATE_1_62; 1353 break; 1354 1355 case DP_RATE_2_70: 1356 PRINT_RATE_2_70; 1357 break; 1358 1359 case DP_RATE_5_40: 1360 PRINT_RATE_5_40; 1361 break; 1362 1363 default: 1364 PRINT_INVALID; 1365 printf("DP Rate\n"); 1366 SetFail = 1; 1367 break; 1368 } 1369 1370 switch (Deemphasis_Show) { 1371 case DP_DEEMP_0: 1372 if (GFlag & F_SHOW_SWING) 1373 PRINT_SWING_0; 1374 else 1375 PRINT_EMPVAL_0; 1376 break; 1377 1378 case DP_DEEMP_1: 1379 if (GFlag & F_SHOW_SWING) 1380 PRINT_SWING_1; 1381 else 1382 PRINT_EMPVAL_1; 1383 break; 1384 1385 case DP_DEEMP_2: 1386 if (GFlag & F_SHOW_SWING) 1387 PRINT_SWING_2; 1388 else 1389 PRINT_EMPVAL_2; 1390 break; 1391 1392 default: 1393 PRINT_INVALID; 1394 printf("Deemphasis Level\n"); 1395 SetFail = 1; 1396 break; 1397 } 1398 1399 switch (Swing_Level) { 1400 case 0: 1401 PRINT_SWING_0; 1402 break; 1403 1404 case 1: 1405 PRINT_SWING_1; 1406 break; 1407 1408 case 2: 1409 PRINT_SWING_2; 1410 break; 1411 1412 default: 1413 PRINT_INVALID; 1414 printf("Swing Level\n"); 1415 SetFail = 1; 1416 break; 1417 } 1418 1419 PHY_Cfg = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level); 1420 PHY_Cfg_1 = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level_1); 1421 PHY_Cfg_N = DP_PHY_INIT_CFG | (DP_Rate | DP_DEEMP_2); 1422 1423 switch (SSCG) { 1424 case DP_SSCG_ON: 1425 PRINT_SSCG_ON; 1426 break; 1427 1428 case DP_SSCG_OFF: 1429 PRINT_SSCG_OFF; 1430 break; 1431 1432 default: 1433 PRINT_INVALID; 1434 printf("SSCG\n"); 1435 SetFail = 1; 1436 break; 1437 } 1438 TX_SSCG_Cfg |= SSCG; 1439 1440 printf("\n"); 1441 1442 return SetFail; 1443 } 1444 1445 void DPPHYTX_Show_Item(char received) 1446 { 1447 switch (received) { 1448 case 'a': 1449 PRINT_ITEM_A; 1450 break; 1451 1452 case 'b': 1453 PRINT_ITEM_B; 1454 break; 1455 1456 case 'c': 1457 PRINT_ITEM_C; 1458 break; 1459 1460 case 'd': 1461 PRINT_ITEM_D; 1462 break; 1463 1464 case 'e': 1465 PRINT_ITEM_E; 1466 break; 1467 1468 case 'f': 1469 PRINT_ITEM_F; 1470 break; 1471 1472 case 'g': 1473 PRINT_ITEM_G; 1474 break; 1475 1476 case 'h': 1477 PRINT_ITEM_H; 1478 break; 1479 1480 case 'i': 1481 PRINT_ITEM_I; 1482 break; 1483 1484 case 'j': 1485 PRINT_ITEM_J; 1486 break; 1487 1488 case 'k': 1489 PRINT_ITEM_K; 1490 break; 1491 1492 case 'x': 1493 PRINT_ITEM_X; 1494 break; 1495 1496 default: 1497 break; 1498 } 1499 1500 printf("\n"); 1501 } 1502 1503 void Set_PRBS7(void) 1504 { 1505 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1506 writel((DP_PY_PAT | DP_PY_PAT_PRB7), DP_TX_PHY_PAT); 1507 } 1508 1509 void Set_HBR2CPAT(void) 1510 { 1511 int value = 0, count = 0; 1512 1513 writel(DP_TX_MAIN_ADV, DP_TX_MAIN_SET); 1514 1515 writel(DP_TX_PAT_HBR2, DP_TX_MAIN_PAT); 1516 writel((DP_PY_PAT | DP_PY_PAT_SCRB), DP_TX_PHY_PAT); 1517 1518 writel(DP_TX_MAIN_TRA, DP_TX_MAIN_CFG); 1519 mdelay(1); 1520 1521 while (value != DP_TX_RDY_25201) { 1522 value = (readl(DP_TX_MAIN_CFG) & 0xFFF); 1523 mdelay(1); 1524 count++; 1525 } 1526 1527 /* Reset for signal apply */ 1528 writel((DP_TX_MAIN_ADV | DP_TX_PY_RESET), DP_TX_MAIN_SET); 1529 } 1530 1531 void Set_PLTPAT(void) 1532 { 1533 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1534 1535 writel(DP_TX_PLTPAT_0, DP_TX_CUS_PAT_0); 1536 writel(DP_TX_PLTPAT_1, DP_TX_CUS_PAT_1); 1537 writel(DP_TX_PLTPAT_2, DP_TX_CUS_PAT_2); 1538 1539 writel((DP_PY_PAT | DP_PY_PAT_CUS), DP_TX_PHY_PAT); 1540 } 1541 1542 void Set_D10_1(void) 1543 { 1544 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1545 1546 writel(DP_TX_PAT_TPS1, DP_TX_MAIN_PAT); 1547 writel(DP_PY_PAT, DP_TX_PHY_PAT); 1548 } 1549 1550 uchar AUX_R(int aux_cmd, int aux_addr, int *aux_r_data, uchar *length, uchar *status) 1551 { 1552 int wdata = 0, temp = 0; 1553 uchar len = *length; 1554 1555 /* Check valid length */ 1556 if (len >= 1) 1557 len -= 1; 1558 else 1559 return 1; 1560 1561 /* Prepare AUX write address and data */ 1562 wdata = (int)((len << 24) | aux_addr); 1563 writel(wdata, DP_AUX_ADDR_LEN); 1564 1565 DBG(DBG_AUX_R, "AUX Read on 0x%x with %d bytes.\n", aux_addr, *length); 1566 1567 /* Fire AUX read */ 1568 writel(aux_cmd, DP_AUX_REQ_CFG); 1569 1570 /* Wait AUX read finish or timeout */ 1571 do { 1572 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1573 } while (!(temp & 0xC000)); 1574 1575 /* Clear AUX write interrupt status */ 1576 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1577 writel(wdata, DP_TX_INT_CLEAR); 1578 1579 if (temp & AUX_CMD_DONE) { 1580 /* Read back data count */ 1581 *aux_r_data = readl(DP_AUX_R_D_0); 1582 1583 DBG(DBG_AUX_R, "Data on 0x0 is 0x%x.\n", *aux_r_data); 1584 1585 if ((*length) > 0x4) { 1586 aux_r_data++; 1587 *aux_r_data = readl(DP_AUX_R_D_4); 1588 DBG(DBG_AUX_R, "Data on 0x4 is 0x%x.\n", *aux_r_data); 1589 } 1590 1591 if ((*length) > 0x8) { 1592 aux_r_data++; 1593 *aux_r_data = readl(DP_AUX_R_D_8); 1594 DBG(DBG_AUX_R, "Data on 0x8 is 0x%x.\n", *aux_r_data); 1595 } 1596 1597 if ((*length) > 0xC) { 1598 aux_r_data++; 1599 *aux_r_data = readl(DP_AUX_R_D_C); 1600 DBG(DBG_AUX_R, "Data on 0xC is 0x%x.\n", *aux_r_data); 1601 } 1602 1603 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1604 return 0; 1605 } else { 1606 return 1; 1607 } 1608 } 1609 1610 uchar AUX_W(int aux_cmd, int aux_addr, int *aux_w_data, uchar *length, uchar *status) 1611 { 1612 int wdata = 0, temp = 0; 1613 uchar len = *length; 1614 1615 /* Check valid length */ 1616 if (len >= 1) 1617 len -= 1; 1618 else 1619 return 1; 1620 1621 /* Prepare AUX write address and data */ 1622 wdata = (int)((len << 24) | aux_addr); 1623 writel(wdata, DP_AUX_ADDR_LEN); 1624 1625 writel(*aux_w_data, DP_AUX_W_D_0); 1626 1627 if ((*length) > 0x4) { 1628 aux_w_data++; 1629 writel(*aux_w_data, DP_AUX_W_D_4); 1630 } 1631 1632 if ((*length) > 0x8) { 1633 aux_w_data++; 1634 writel(*aux_w_data, DP_AUX_W_D_8); 1635 } 1636 1637 if ((*length) > 0xC) { 1638 aux_w_data++; 1639 writel(*aux_w_data, DP_AUX_W_D_C); 1640 } 1641 1642 /* Fire AUX write */ 1643 writel(aux_cmd, DP_AUX_REQ_CFG); 1644 1645 /* Wait AUX write finish or timeout */ 1646 do { 1647 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1648 } while (!(temp & 0xC000)); 1649 1650 /* Clear AUX write interrupt status */ 1651 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1652 writel(wdata, DP_TX_INT_CLEAR); 1653 1654 if (temp & AUX_CMD_DONE) { 1655 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1656 return 0; 1657 } else { 1658 return 1; 1659 } 1660 } 1661 1662 U_BOOT_CMD(dptest, 2, 0, do_ast_dptest, "ASPEED Display Port phy test", "ASPEED DP test v.0.2.9"); 1663