1 /* 2 * Copyright (C) 2009 3 * Marek Vasut <marek.vasut@gmail.com> 4 * 5 * Heavily based on pxa255_idp platform 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <command.h> 12 #include <serial.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/pxa.h> 15 #include <asm/arch/regs-mmc.h> 16 #include <spi.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #ifdef CONFIG_CMD_SPI 22 void lcd_start(void); 23 #else 24 inline void lcd_start(void) {}; 25 #endif 26 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 31 int board_init (void) 32 { 33 /* We have RAM, disable cache */ 34 dcache_disable(); 35 icache_disable(); 36 37 /* arch number of Z2 */ 38 gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; 39 40 /* adress of boot parameters */ 41 gd->bd->bi_boot_params = 0xa0000100; 42 43 /* Enable LCD */ 44 lcd_start(); 45 46 return 0; 47 } 48 49 int dram_init(void) 50 { 51 pxa2xx_dram_init(); 52 gd->ram_size = PHYS_SDRAM_1_SIZE; 53 return 0; 54 } 55 56 void dram_init_banksize(void) 57 { 58 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 59 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 60 } 61 62 #ifdef CONFIG_CMD_MMC 63 int board_mmc_init(bd_t *bis) 64 { 65 pxa_mmc_register(0); 66 return 0; 67 } 68 #endif 69 70 #ifdef CONFIG_CMD_SPI 71 72 struct { 73 unsigned char reg; 74 unsigned short data; 75 unsigned char mdelay; 76 } lcd_data[] = { 77 { 0x07, 0x0000, 0 }, 78 { 0x13, 0x0000, 10 }, 79 { 0x11, 0x3004, 0 }, 80 { 0x14, 0x200F, 0 }, 81 { 0x10, 0x1a20, 0 }, 82 { 0x13, 0x0040, 50 }, 83 { 0x13, 0x0060, 0 }, 84 { 0x13, 0x0070, 200 }, 85 { 0x01, 0x0127, 0 }, 86 { 0x02, 0x0700, 0 }, 87 { 0x03, 0x1030, 0 }, 88 { 0x08, 0x0208, 0 }, 89 { 0x0B, 0x0620, 0 }, 90 { 0x0C, 0x0110, 0 }, 91 { 0x30, 0x0120, 0 }, 92 { 0x31, 0x0127, 0 }, 93 { 0x32, 0x0000, 0 }, 94 { 0x33, 0x0503, 0 }, 95 { 0x34, 0x0727, 0 }, 96 { 0x35, 0x0124, 0 }, 97 { 0x36, 0x0706, 0 }, 98 { 0x37, 0x0701, 0 }, 99 { 0x38, 0x0F00, 0 }, 100 { 0x39, 0x0F00, 0 }, 101 { 0x40, 0x0000, 0 }, 102 { 0x41, 0x0000, 0 }, 103 { 0x42, 0x013f, 0 }, 104 { 0x43, 0x0000, 0 }, 105 { 0x44, 0x013f, 0 }, 106 { 0x45, 0x0000, 0 }, 107 { 0x46, 0xef00, 0 }, 108 { 0x47, 0x013f, 0 }, 109 { 0x48, 0x0000, 0 }, 110 { 0x07, 0x0015, 30 }, 111 { 0x07, 0x0017, 0 }, 112 { 0x20, 0x0000, 0 }, 113 { 0x21, 0x0000, 0 }, 114 { 0x22, 0x0000, 0 }, 115 }; 116 117 void zipitz2_spi_sda(int set) 118 { 119 /* GPIO 13 */ 120 if (set) 121 writel((1 << 13), GPSR0); 122 else 123 writel((1 << 13), GPCR0); 124 } 125 126 void zipitz2_spi_scl(int set) 127 { 128 /* GPIO 22 */ 129 if (set) 130 writel((1 << 22), GPCR0); 131 else 132 writel((1 << 22), GPSR0); 133 } 134 135 unsigned char zipitz2_spi_read(void) 136 { 137 /* GPIO 40 */ 138 return !!(readl(GPLR1) & (1 << 8)); 139 } 140 141 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 142 { 143 /* Always valid */ 144 return 1; 145 } 146 147 void spi_cs_activate(struct spi_slave *slave) 148 { 149 /* GPIO 88 low */ 150 writel((1 << 24), GPCR2); 151 } 152 153 void spi_cs_deactivate(struct spi_slave *slave) 154 { 155 /* GPIO 88 high */ 156 writel((1 << 24), GPSR2); 157 158 } 159 160 void lcd_start(void) 161 { 162 int i; 163 unsigned char reg[3] = { 0x74, 0x00, 0 }; 164 unsigned char data[3] = { 0x76, 0, 0 }; 165 unsigned char dummy[3] = { 0, 0, 0 }; 166 167 /* PWM2 AF */ 168 writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); 169 /* Enable clock to all PWM */ 170 writel(readl(CKEN) | 0x3, CKEN); 171 /* Configure PWM2 */ 172 writel(0x4f, PWM_CTRL2); 173 writel(0x2ff, PWM_PWDUTY2); 174 writel(792, PWM_PERVAL2); 175 176 /* Toggle the reset pin to reset the LCD */ 177 writel((1 << 19), GPSR0); 178 udelay(100000); 179 writel((1 << 19), GPCR0); 180 udelay(20000); 181 writel((1 << 19), GPSR0); 182 udelay(20000); 183 184 /* Program the LCD init sequence */ 185 for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { 186 reg[0] = 0x74; 187 reg[1] = 0x0; 188 reg[2] = lcd_data[i].reg; 189 spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 190 191 data[0] = 0x76; 192 data[1] = lcd_data[i].data >> 8; 193 data[2] = lcd_data[i].data & 0xff; 194 spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 195 196 if (lcd_data[i].mdelay) 197 udelay(lcd_data[i].mdelay * 1000); 198 } 199 200 writel((1 << 11), GPSR0); 201 } 202 #endif 203