1 /* 2 * Copyright (C) 2009 3 * Marek Vasut <marek.vasut@gmail.com> 4 * 5 * Heavily based on pxa255_idp platform 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <command.h> 28 #include <serial.h> 29 #include <asm/arch/hardware.h> 30 #include <asm/arch/pxa.h> 31 #include <asm/arch/regs-mmc.h> 32 #include <spi.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_CMD_SPI 38 void lcd_start(void); 39 #else 40 inline void lcd_start(void) {}; 41 #endif 42 43 /* 44 * Miscelaneous platform dependent initialisations 45 */ 46 47 int board_init (void) 48 { 49 /* We have RAM, disable cache */ 50 dcache_disable(); 51 icache_disable(); 52 53 /* arch number of Z2 */ 54 gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; 55 56 /* adress of boot parameters */ 57 gd->bd->bi_boot_params = 0xa0000100; 58 59 /* Enable LCD */ 60 lcd_start(); 61 62 return 0; 63 } 64 65 int dram_init(void) 66 { 67 pxa2xx_dram_init(); 68 gd->ram_size = PHYS_SDRAM_1_SIZE; 69 return 0; 70 } 71 72 void dram_init_banksize(void) 73 { 74 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 75 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 76 } 77 78 #ifdef CONFIG_CMD_MMC 79 int board_mmc_init(bd_t *bis) 80 { 81 pxa_mmc_register(0); 82 return 0; 83 } 84 #endif 85 86 #ifdef CONFIG_CMD_SPI 87 88 struct { 89 unsigned char reg; 90 unsigned short data; 91 unsigned char mdelay; 92 } lcd_data[] = { 93 { 0x07, 0x0000, 0 }, 94 { 0x13, 0x0000, 10 }, 95 { 0x11, 0x3004, 0 }, 96 { 0x14, 0x200F, 0 }, 97 { 0x10, 0x1a20, 0 }, 98 { 0x13, 0x0040, 50 }, 99 { 0x13, 0x0060, 0 }, 100 { 0x13, 0x0070, 200 }, 101 { 0x01, 0x0127, 0 }, 102 { 0x02, 0x0700, 0 }, 103 { 0x03, 0x1030, 0 }, 104 { 0x08, 0x0208, 0 }, 105 { 0x0B, 0x0620, 0 }, 106 { 0x0C, 0x0110, 0 }, 107 { 0x30, 0x0120, 0 }, 108 { 0x31, 0x0127, 0 }, 109 { 0x32, 0x0000, 0 }, 110 { 0x33, 0x0503, 0 }, 111 { 0x34, 0x0727, 0 }, 112 { 0x35, 0x0124, 0 }, 113 { 0x36, 0x0706, 0 }, 114 { 0x37, 0x0701, 0 }, 115 { 0x38, 0x0F00, 0 }, 116 { 0x39, 0x0F00, 0 }, 117 { 0x40, 0x0000, 0 }, 118 { 0x41, 0x0000, 0 }, 119 { 0x42, 0x013f, 0 }, 120 { 0x43, 0x0000, 0 }, 121 { 0x44, 0x013f, 0 }, 122 { 0x45, 0x0000, 0 }, 123 { 0x46, 0xef00, 0 }, 124 { 0x47, 0x013f, 0 }, 125 { 0x48, 0x0000, 0 }, 126 { 0x07, 0x0015, 30 }, 127 { 0x07, 0x0017, 0 }, 128 { 0x20, 0x0000, 0 }, 129 { 0x21, 0x0000, 0 }, 130 { 0x22, 0x0000, 0 }, 131 }; 132 133 void zipitz2_spi_sda(int set) 134 { 135 /* GPIO 13 */ 136 if (set) 137 writel((1 << 13), GPSR0); 138 else 139 writel((1 << 13), GPCR0); 140 } 141 142 void zipitz2_spi_scl(int set) 143 { 144 /* GPIO 22 */ 145 if (set) 146 writel((1 << 22), GPCR0); 147 else 148 writel((1 << 22), GPSR0); 149 } 150 151 unsigned char zipitz2_spi_read(void) 152 { 153 /* GPIO 40 */ 154 return !!(readl(GPLR1) & (1 << 8)); 155 } 156 157 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 158 { 159 /* Always valid */ 160 return 1; 161 } 162 163 void spi_cs_activate(struct spi_slave *slave) 164 { 165 /* GPIO 88 low */ 166 writel((1 << 24), GPCR2); 167 } 168 169 void spi_cs_deactivate(struct spi_slave *slave) 170 { 171 /* GPIO 88 high */ 172 writel((1 << 24), GPSR2); 173 174 } 175 176 void lcd_start(void) 177 { 178 int i; 179 unsigned char reg[3] = { 0x74, 0x00, 0 }; 180 unsigned char data[3] = { 0x76, 0, 0 }; 181 unsigned char dummy[3] = { 0, 0, 0 }; 182 183 /* PWM2 AF */ 184 writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); 185 /* Enable clock to all PWM */ 186 writel(readl(CKEN) | 0x3, CKEN); 187 /* Configure PWM2 */ 188 writel(0x4f, PWM_CTRL2); 189 writel(0x2ff, PWM_PWDUTY2); 190 writel(792, PWM_PERVAL2); 191 192 /* Toggle the reset pin to reset the LCD */ 193 writel((1 << 19), GPSR0); 194 udelay(100000); 195 writel((1 << 19), GPCR0); 196 udelay(20000); 197 writel((1 << 19), GPSR0); 198 udelay(20000); 199 200 /* Program the LCD init sequence */ 201 for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { 202 reg[0] = 0x74; 203 reg[1] = 0x0; 204 reg[2] = lcd_data[i].reg; 205 spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 206 207 data[0] = 0x76; 208 data[1] = lcd_data[i].data >> 8; 209 data[2] = lcd_data[i].data & 0xff; 210 spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 211 212 if (lcd_data[i].mdelay) 213 udelay(lcd_data[i].mdelay * 1000); 214 } 215 216 writel((1 << 11), GPSR0); 217 } 218 #endif 219