1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <sata.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <malloc.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/psu_init_gpl.h> 17 #include <asm/io.h> 18 #include <usb.h> 19 #include <dwc3-uboot.h> 20 #include <zynqmppl.h> 21 #include <i2c.h> 22 #include <g_dnl.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ 27 !defined(CONFIG_SPL_BUILD) 28 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; 29 30 static const struct { 31 u32 id; 32 u32 ver; 33 char *name; 34 bool evexists; 35 } zynqmp_devices[] = { 36 { 37 .id = 0x10, 38 .name = "3eg", 39 }, 40 { 41 .id = 0x10, 42 .ver = 0x2c, 43 .name = "3cg", 44 }, 45 { 46 .id = 0x11, 47 .name = "2eg", 48 }, 49 { 50 .id = 0x11, 51 .ver = 0x2c, 52 .name = "2cg", 53 }, 54 { 55 .id = 0x20, 56 .name = "5ev", 57 .evexists = 1, 58 }, 59 { 60 .id = 0x20, 61 .ver = 0x100, 62 .name = "5eg", 63 .evexists = 1, 64 }, 65 { 66 .id = 0x20, 67 .ver = 0x12c, 68 .name = "5cg", 69 }, 70 { 71 .id = 0x21, 72 .name = "4ev", 73 .evexists = 1, 74 }, 75 { 76 .id = 0x21, 77 .ver = 0x100, 78 .name = "4eg", 79 .evexists = 1, 80 }, 81 { 82 .id = 0x21, 83 .ver = 0x12c, 84 .name = "4cg", 85 }, 86 { 87 .id = 0x30, 88 .name = "7ev", 89 .evexists = 1, 90 }, 91 { 92 .id = 0x30, 93 .ver = 0x100, 94 .name = "7eg", 95 .evexists = 1, 96 }, 97 { 98 .id = 0x30, 99 .ver = 0x12c, 100 .name = "7cg", 101 }, 102 { 103 .id = 0x38, 104 .name = "9eg", 105 }, 106 { 107 .id = 0x38, 108 .ver = 0x2c, 109 .name = "9cg", 110 }, 111 { 112 .id = 0x39, 113 .name = "6eg", 114 }, 115 { 116 .id = 0x39, 117 .ver = 0x2c, 118 .name = "6cg", 119 }, 120 { 121 .id = 0x40, 122 .name = "11eg", 123 }, 124 { /* For testing purpose only */ 125 .id = 0x50, 126 .ver = 0x2c, 127 .name = "15cg", 128 }, 129 { 130 .id = 0x50, 131 .name = "15eg", 132 }, 133 { 134 .id = 0x58, 135 .name = "19eg", 136 }, 137 { 138 .id = 0x59, 139 .name = "17eg", 140 }, 141 { 142 .id = 0x61, 143 .name = "21dr", 144 }, 145 { 146 .id = 0x63, 147 .name = "23dr", 148 }, 149 { 150 .id = 0x65, 151 .name = "25dr", 152 }, 153 { 154 .id = 0x64, 155 .name = "27dr", 156 }, 157 { 158 .id = 0x60, 159 .name = "28dr", 160 }, 161 { 162 .id = 0x62, 163 .name = "29dr", 164 }, 165 }; 166 #endif 167 168 int chip_id(unsigned char id) 169 { 170 struct pt_regs regs; 171 int val = -EINVAL; 172 173 if (current_el() != 3) { 174 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID; 175 regs.regs[1] = 0; 176 regs.regs[2] = 0; 177 regs.regs[3] = 0; 178 179 smc_call(®s); 180 181 /* 182 * SMC returns: 183 * regs[0][31:0] = status of the operation 184 * regs[0][63:32] = CSU.IDCODE register 185 * regs[1][31:0] = CSU.version register 186 * regs[1][63:32] = CSU.IDCODE2 register 187 */ 188 switch (id) { 189 case IDCODE: 190 regs.regs[0] = upper_32_bits(regs.regs[0]); 191 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | 192 ZYNQMP_CSU_IDCODE_SVD_MASK; 193 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; 194 val = regs.regs[0]; 195 break; 196 case VERSION: 197 regs.regs[1] = lower_32_bits(regs.regs[1]); 198 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK; 199 val = regs.regs[1]; 200 break; 201 case IDCODE2: 202 regs.regs[1] = lower_32_bits(regs.regs[1]); 203 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT; 204 val = regs.regs[1]; 205 break; 206 default: 207 printf("%s, Invalid Req:0x%x\n", __func__, id); 208 } 209 } else { 210 switch (id) { 211 case IDCODE: 212 val = readl(ZYNQMP_CSU_IDCODE_ADDR); 213 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | 214 ZYNQMP_CSU_IDCODE_SVD_MASK; 215 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; 216 break; 217 case VERSION: 218 val = readl(ZYNQMP_CSU_VER_ADDR); 219 val &= ZYNQMP_CSU_SILICON_VER_MASK; 220 break; 221 default: 222 printf("%s, Invalid Req:0x%x\n", __func__, id); 223 } 224 } 225 226 return val; 227 } 228 229 #define ZYNQMP_VERSION_SIZE 9 230 #define ZYNQMP_PL_STATUS_BIT 9 231 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT) 232 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK) 233 234 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ 235 !defined(CONFIG_SPL_BUILD) 236 static char *zynqmp_get_silicon_idcode_name(void) 237 { 238 u32 i, id, ver; 239 char *buf; 240 static char name[ZYNQMP_VERSION_SIZE]; 241 242 id = chip_id(IDCODE); 243 ver = chip_id(IDCODE2); 244 245 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { 246 if ((zynqmp_devices[i].id == id) && 247 (zynqmp_devices[i].ver == (ver & 248 ZYNQMP_CSU_VERSION_MASK))) { 249 strncat(name, "zu", 2); 250 strncat(name, zynqmp_devices[i].name, 251 ZYNQMP_VERSION_SIZE - 3); 252 break; 253 } 254 } 255 256 if (i >= ARRAY_SIZE(zynqmp_devices)) 257 return "unknown"; 258 259 if (!zynqmp_devices[i].evexists) 260 return name; 261 262 if (ver & ZYNQMP_PL_STATUS_MASK) 263 return name; 264 265 if (strstr(name, "eg") || strstr(name, "ev")) { 266 buf = strstr(name, "e"); 267 *buf = '\0'; 268 } 269 270 return name; 271 } 272 #endif 273 274 int board_early_init_f(void) 275 { 276 int ret = 0; 277 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) 278 zynqmp_pmufw_version(); 279 #endif 280 281 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) 282 ret = psu_init(); 283 #endif 284 285 return ret; 286 } 287 288 int board_init(void) 289 { 290 printf("EL Level:\tEL%d\n", current_el()); 291 292 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ 293 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ 294 defined(CONFIG_SPL_BUILD)) 295 if (current_el() != 3) { 296 zynqmppl.name = zynqmp_get_silicon_idcode_name(); 297 printf("Chip ID:\t%s\n", zynqmppl.name); 298 fpga_init(); 299 fpga_add(fpga_xilinx, &zynqmppl); 300 } 301 #endif 302 303 return 0; 304 } 305 306 int board_early_init_r(void) 307 { 308 u32 val; 309 310 if (current_el() != 3) 311 return 0; 312 313 val = readl(&crlapb_base->timestamp_ref_ctrl); 314 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 315 316 if (!val) { 317 val = readl(&crlapb_base->timestamp_ref_ctrl); 318 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 319 writel(val, &crlapb_base->timestamp_ref_ctrl); 320 321 /* Program freq register in System counter */ 322 writel(zynqmp_get_system_timer_freq(), 323 &iou_scntr_secure->base_frequency_id_register); 324 /* And enable system counter */ 325 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 326 &iou_scntr_secure->counter_control_register); 327 } 328 return 0; 329 } 330 331 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 332 { 333 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 334 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ 335 defined(CONFIG_ZYNQ_EEPROM_BUS) 336 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); 337 338 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 339 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 340 ethaddr, 6)) 341 printf("I2C EEPROM MAC address read failed\n"); 342 #endif 343 344 return 0; 345 } 346 347 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, 348 char * const argv[]) 349 { 350 int ret = 0; 351 352 if (current_el() > 1) { 353 smp_kick_all_cpus(); 354 dcache_disable(); 355 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry, 356 ES_TO_AARCH64); 357 } else { 358 printf("FAIL: current EL is not above EL1\n"); 359 ret = EINVAL; 360 } 361 return ret; 362 } 363 364 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 365 int dram_init_banksize(void) 366 { 367 return fdtdec_setup_memory_banksize(); 368 } 369 370 int dram_init(void) 371 { 372 if (fdtdec_setup_memory_size() != 0) 373 return -EINVAL; 374 375 return 0; 376 } 377 #else 378 int dram_init(void) 379 { 380 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 381 382 return 0; 383 } 384 #endif 385 386 void reset_cpu(ulong addr) 387 { 388 } 389 390 int board_late_init(void) 391 { 392 u32 reg = 0; 393 u8 bootmode; 394 const char *mode; 395 char *new_targets; 396 char *env_targets; 397 int ret; 398 399 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { 400 debug("Saved variables - Skipping\n"); 401 return 0; 402 } 403 404 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); 405 if (ret) 406 return -EINVAL; 407 408 if (reg >> BOOT_MODE_ALT_SHIFT) 409 reg >>= BOOT_MODE_ALT_SHIFT; 410 411 bootmode = reg & BOOT_MODES_MASK; 412 413 puts("Bootmode: "); 414 switch (bootmode) { 415 case USB_MODE: 416 puts("USB_MODE\n"); 417 mode = "usb"; 418 env_set("modeboot", "usb_dfu_spl"); 419 break; 420 case JTAG_MODE: 421 puts("JTAG_MODE\n"); 422 mode = "pxe dhcp"; 423 env_set("modeboot", "jtagboot"); 424 break; 425 case QSPI_MODE_24BIT: 426 case QSPI_MODE_32BIT: 427 mode = "qspi0"; 428 puts("QSPI_MODE\n"); 429 env_set("modeboot", "qspiboot"); 430 break; 431 case EMMC_MODE: 432 puts("EMMC_MODE\n"); 433 mode = "mmc0"; 434 env_set("modeboot", "emmcboot"); 435 break; 436 case SD_MODE: 437 puts("SD_MODE\n"); 438 mode = "mmc0"; 439 env_set("modeboot", "sdboot"); 440 break; 441 case SD1_LSHFT_MODE: 442 puts("LVL_SHFT_"); 443 /* fall through */ 444 case SD_MODE1: 445 puts("SD_MODE1\n"); 446 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) 447 mode = "mmc1"; 448 env_set("sdbootdev", "1"); 449 #else 450 mode = "mmc0"; 451 #endif 452 env_set("modeboot", "sdboot"); 453 break; 454 case NAND_MODE: 455 puts("NAND_MODE\n"); 456 mode = "nand0"; 457 env_set("modeboot", "nandboot"); 458 break; 459 default: 460 mode = ""; 461 printf("Invalid Boot Mode:0x%x\n", bootmode); 462 break; 463 } 464 465 /* 466 * One terminating char + one byte for space between mode 467 * and default boot_targets 468 */ 469 env_targets = env_get("boot_targets"); 470 if (env_targets) { 471 new_targets = calloc(1, strlen(mode) + 472 strlen(env_targets) + 2); 473 sprintf(new_targets, "%s %s", mode, env_targets); 474 } else { 475 new_targets = calloc(1, strlen(mode) + 2); 476 sprintf(new_targets, "%s", mode); 477 } 478 479 env_set("boot_targets", new_targets); 480 481 return 0; 482 } 483 484 int checkboard(void) 485 { 486 puts("Board: Xilinx ZynqMP\n"); 487 return 0; 488 } 489 490 #ifdef CONFIG_USB_DWC3 491 static struct dwc3_device dwc3_device_data0 = { 492 .maximum_speed = USB_SPEED_HIGH, 493 .base = ZYNQMP_USB0_XHCI_BASEADDR, 494 .dr_mode = USB_DR_MODE_PERIPHERAL, 495 .index = 0, 496 }; 497 498 static struct dwc3_device dwc3_device_data1 = { 499 .maximum_speed = USB_SPEED_HIGH, 500 .base = ZYNQMP_USB1_XHCI_BASEADDR, 501 .dr_mode = USB_DR_MODE_PERIPHERAL, 502 .index = 1, 503 }; 504 505 int usb_gadget_handle_interrupts(int index) 506 { 507 dwc3_uboot_handle_interrupt(index); 508 return 0; 509 } 510 511 int board_usb_init(int index, enum usb_init_type init) 512 { 513 debug("%s: index %x\n", __func__, index); 514 515 #if defined(CONFIG_USB_GADGET_DOWNLOAD) 516 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME); 517 #endif 518 519 switch (index) { 520 case 0: 521 return dwc3_uboot_init(&dwc3_device_data0); 522 case 1: 523 return dwc3_uboot_init(&dwc3_device_data1); 524 }; 525 526 return -1; 527 } 528 529 int board_usb_cleanup(int index, enum usb_init_type init) 530 { 531 dwc3_uboot_exit(index); 532 return 0; 533 } 534 #endif 535