1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/io.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 int board_init(void) 17 { 18 return 0; 19 } 20 21 int board_early_init_r(void) 22 { 23 u32 val; 24 25 val = readl(&crlapb_base->timestamp_ref_ctrl); 26 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 27 writel(val, &crlapb_base->timestamp_ref_ctrl); 28 29 /* Program freq register in System counter and enable system counter */ 30 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 31 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 32 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 33 &iou_scntr->counter_control_register); 34 35 return 0; 36 } 37 38 int dram_init(void) 39 { 40 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 41 42 return 0; 43 } 44 45 int timer_init(void) 46 { 47 return 0; 48 } 49 50 void reset_cpu(ulong addr) 51 { 52 } 53 54 #ifdef CONFIG_CMD_MMC 55 int board_mmc_init(bd_t *bd) 56 { 57 int ret = 0; 58 59 u32 ver = zynqmp_get_silicon_version(); 60 61 if (ver != ZYNQMP_CSU_VERSION_VELOCE) { 62 #if defined(CONFIG_ZYNQ_SDHCI) 63 # if defined(CONFIG_ZYNQ_SDHCI0) 64 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 65 # endif 66 # if defined(CONFIG_ZYNQ_SDHCI1) 67 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 68 # endif 69 #endif 70 } 71 72 return ret; 73 } 74 #endif 75 76 int board_late_init(void) 77 { 78 u32 reg = 0; 79 u8 bootmode; 80 81 reg = readl(&crlapb_base->boot_mode); 82 bootmode = reg & BOOT_MODES_MASK; 83 84 switch (bootmode) { 85 case SD_MODE: 86 case EMMC_MODE: 87 setenv("modeboot", "sdboot"); 88 break; 89 default: 90 printf("Invalid Boot Mode:0x%x\n", bootmode); 91 break; 92 } 93 94 return 0; 95 } 96