1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/io.h> 15 #include <usb.h> 16 #include <dwc3-uboot.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 int board_init(void) 21 { 22 printf("EL Level:\tEL%d\n", current_el()); 23 24 return 0; 25 } 26 27 int board_early_init_r(void) 28 { 29 u32 val; 30 31 val = readl(&crlapb_base->timestamp_ref_ctrl); 32 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 33 writel(val, &crlapb_base->timestamp_ref_ctrl); 34 35 /* Program freq register in System counter and enable system counter */ 36 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 37 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 38 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 39 &iou_scntr->counter_control_register); 40 41 return 0; 42 } 43 44 int dram_init(void) 45 { 46 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 47 48 return 0; 49 } 50 51 int timer_init(void) 52 { 53 return 0; 54 } 55 56 void reset_cpu(ulong addr) 57 { 58 } 59 60 #ifdef CONFIG_SCSI_AHCI_PLAT 61 void scsi_init(void) 62 { 63 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); 64 scsi_scan(1); 65 } 66 #endif 67 68 int board_eth_init(bd_t *bis) 69 { 70 u32 ret = 0; 71 72 #if defined(CONFIG_ZYNQ_GEM) 73 # if defined(CONFIG_ZYNQ_GEM0) 74 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 75 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 76 # endif 77 # if defined(CONFIG_ZYNQ_GEM1) 78 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 79 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 80 # endif 81 # if defined(CONFIG_ZYNQ_GEM2) 82 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, 83 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); 84 # endif 85 # if defined(CONFIG_ZYNQ_GEM3) 86 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, 87 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); 88 # endif 89 #endif 90 return ret; 91 } 92 93 #ifdef CONFIG_CMD_MMC 94 int board_mmc_init(bd_t *bd) 95 { 96 int ret = 0; 97 98 u32 ver = zynqmp_get_silicon_version(); 99 100 if (ver != ZYNQMP_CSU_VERSION_VELOCE) { 101 #if defined(CONFIG_ZYNQ_SDHCI) 102 # if defined(CONFIG_ZYNQ_SDHCI0) 103 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 104 # endif 105 # if defined(CONFIG_ZYNQ_SDHCI1) 106 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 107 # endif 108 #endif 109 } 110 111 return ret; 112 } 113 #endif 114 115 int board_late_init(void) 116 { 117 u32 reg = 0; 118 u8 bootmode; 119 120 reg = readl(&crlapb_base->boot_mode); 121 bootmode = reg & BOOT_MODES_MASK; 122 123 switch (bootmode) { 124 case SD_MODE: 125 case EMMC_MODE: 126 setenv("modeboot", "sdboot"); 127 break; 128 default: 129 printf("Invalid Boot Mode:0x%x\n", bootmode); 130 break; 131 } 132 133 return 0; 134 } 135 136 int checkboard(void) 137 { 138 puts("Board:\tXilinx ZynqMP\n"); 139 return 0; 140 } 141 142 #ifdef CONFIG_USB_DWC3 143 static struct dwc3_device dwc3_device_data = { 144 .maximum_speed = USB_SPEED_HIGH, 145 .base = ZYNQMP_USB0_XHCI_BASEADDR, 146 .dr_mode = USB_DR_MODE_PERIPHERAL, 147 .index = 0, 148 }; 149 150 int usb_gadget_handle_interrupts(void) 151 { 152 dwc3_uboot_handle_interrupt(0); 153 return 0; 154 } 155 156 int board_usb_init(int index, enum usb_init_type init) 157 { 158 return dwc3_uboot_init(&dwc3_device_data); 159 } 160 161 int board_usb_cleanup(int index, enum usb_init_type init) 162 { 163 dwc3_uboot_exit(index); 164 return 0; 165 } 166 #endif 167