1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <sata.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <malloc.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/io.h> 17 #include <usb.h> 18 #include <dwc3-uboot.h> 19 #include <zynqmppl.h> 20 #include <i2c.h> 21 #include <g_dnl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ 26 !defined(CONFIG_SPL_BUILD) 27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; 28 29 static const struct { 30 uint32_t id; 31 char *name; 32 } zynqmp_devices[] = { 33 { 34 .id = 0x10, 35 .name = "3eg", 36 }, 37 { 38 .id = 0x11, 39 .name = "2eg", 40 }, 41 { 42 .id = 0x20, 43 .name = "5ev", 44 }, 45 { 46 .id = 0x21, 47 .name = "4ev", 48 }, 49 { 50 .id = 0x30, 51 .name = "7ev", 52 }, 53 { 54 .id = 0x38, 55 .name = "9eg", 56 }, 57 { 58 .id = 0x39, 59 .name = "6eg", 60 }, 61 { 62 .id = 0x40, 63 .name = "11eg", 64 }, 65 { 66 .id = 0x50, 67 .name = "15eg", 68 }, 69 { 70 .id = 0x58, 71 .name = "19eg", 72 }, 73 { 74 .id = 0x59, 75 .name = "17eg", 76 }, 77 }; 78 79 static int chip_id(void) 80 { 81 struct pt_regs regs; 82 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID; 83 regs.regs[1] = 0; 84 regs.regs[2] = 0; 85 regs.regs[3] = 0; 86 87 smc_call(®s); 88 89 /* 90 * SMC returns: 91 * regs[0][31:0] = status of the operation 92 * regs[0][63:32] = CSU.IDCODE register 93 * regs[1][31:0] = CSU.version register 94 */ 95 regs.regs[0] = upper_32_bits(regs.regs[0]); 96 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | 97 ZYNQMP_CSU_IDCODE_SVD_MASK; 98 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; 99 100 return regs.regs[0]; 101 } 102 103 static char *zynqmp_get_silicon_idcode_name(void) 104 { 105 uint32_t i, id; 106 107 id = chip_id(); 108 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { 109 if (zynqmp_devices[i].id == id) 110 return zynqmp_devices[i].name; 111 } 112 return "unknown"; 113 } 114 #endif 115 116 int board_early_init_f(void) 117 { 118 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) 119 zynqmp_pmufw_version(); 120 #endif 121 return 0; 122 } 123 124 #define ZYNQMP_VERSION_SIZE 9 125 126 int board_init(void) 127 { 128 printf("EL Level:\tEL%d\n", current_el()); 129 130 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ 131 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ 132 defined(CONFIG_SPL_BUILD)) 133 if (current_el() != 3) { 134 static char version[ZYNQMP_VERSION_SIZE]; 135 136 strncat(version, "xczu", ZYNQMP_VERSION_SIZE); 137 zynqmppl.name = strncat(version, 138 zynqmp_get_silicon_idcode_name(), 139 ZYNQMP_VERSION_SIZE); 140 printf("Chip ID:\t%s\n", zynqmppl.name); 141 fpga_init(); 142 fpga_add(fpga_xilinx, &zynqmppl); 143 } 144 #endif 145 146 return 0; 147 } 148 149 int board_early_init_r(void) 150 { 151 u32 val; 152 153 if (current_el() == 3) { 154 val = readl(&crlapb_base->timestamp_ref_ctrl); 155 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 156 writel(val, &crlapb_base->timestamp_ref_ctrl); 157 158 /* Program freq register in System counter */ 159 writel(zynqmp_get_system_timer_freq(), 160 &iou_scntr_secure->base_frequency_id_register); 161 /* And enable system counter */ 162 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 163 &iou_scntr_secure->counter_control_register); 164 } 165 /* Program freq register in System counter and enable system counter */ 166 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 167 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 168 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 169 &iou_scntr->counter_control_register); 170 171 return 0; 172 } 173 174 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 175 { 176 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 177 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ 178 defined(CONFIG_ZYNQ_EEPROM_BUS) 179 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); 180 181 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 182 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 183 ethaddr, 6)) 184 printf("I2C EEPROM MAC address read failed\n"); 185 #endif 186 187 return 0; 188 } 189 190 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 191 int dram_init_banksize(void) 192 { 193 fdtdec_setup_memory_banksize(); 194 195 return 0; 196 } 197 198 int dram_init(void) 199 { 200 if (fdtdec_setup_memory_size() != 0) 201 return -EINVAL; 202 203 return 0; 204 } 205 #else 206 int dram_init(void) 207 { 208 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 209 210 return 0; 211 } 212 #endif 213 214 void reset_cpu(ulong addr) 215 { 216 } 217 218 int board_late_init(void) 219 { 220 u32 reg = 0; 221 u8 bootmode; 222 const char *mode; 223 char *new_targets; 224 225 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { 226 debug("Saved variables - Skipping\n"); 227 return 0; 228 } 229 230 reg = readl(&crlapb_base->boot_mode); 231 if (reg >> BOOT_MODE_ALT_SHIFT) 232 reg >>= BOOT_MODE_ALT_SHIFT; 233 234 bootmode = reg & BOOT_MODES_MASK; 235 236 puts("Bootmode: "); 237 switch (bootmode) { 238 case USB_MODE: 239 puts("USB_MODE\n"); 240 mode = "usb"; 241 break; 242 case JTAG_MODE: 243 puts("JTAG_MODE\n"); 244 mode = "pxe dhcp"; 245 break; 246 case QSPI_MODE_24BIT: 247 case QSPI_MODE_32BIT: 248 mode = "qspi0"; 249 puts("QSPI_MODE\n"); 250 break; 251 case EMMC_MODE: 252 puts("EMMC_MODE\n"); 253 mode = "mmc0"; 254 break; 255 case SD_MODE: 256 puts("SD_MODE\n"); 257 mode = "mmc0"; 258 break; 259 case SD1_LSHFT_MODE: 260 puts("LVL_SHFT_"); 261 /* fall through */ 262 case SD_MODE1: 263 puts("SD_MODE1\n"); 264 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) 265 mode = "mmc1"; 266 #else 267 mode = "mmc0"; 268 #endif 269 break; 270 case NAND_MODE: 271 puts("NAND_MODE\n"); 272 mode = "nand0"; 273 break; 274 default: 275 mode = ""; 276 printf("Invalid Boot Mode:0x%x\n", bootmode); 277 break; 278 } 279 280 /* 281 * One terminating char + one byte for space between mode 282 * and default boot_targets 283 */ 284 new_targets = calloc(1, strlen(mode) + 285 strlen(getenv("boot_targets")) + 2); 286 287 sprintf(new_targets, "%s %s", mode, getenv("boot_targets")); 288 setenv("boot_targets", new_targets); 289 290 return 0; 291 } 292 293 int checkboard(void) 294 { 295 puts("Board: Xilinx ZynqMP\n"); 296 return 0; 297 } 298 299 #ifdef CONFIG_USB_DWC3 300 static struct dwc3_device dwc3_device_data0 = { 301 .maximum_speed = USB_SPEED_HIGH, 302 .base = ZYNQMP_USB0_XHCI_BASEADDR, 303 .dr_mode = USB_DR_MODE_PERIPHERAL, 304 .index = 0, 305 }; 306 307 static struct dwc3_device dwc3_device_data1 = { 308 .maximum_speed = USB_SPEED_HIGH, 309 .base = ZYNQMP_USB1_XHCI_BASEADDR, 310 .dr_mode = USB_DR_MODE_PERIPHERAL, 311 .index = 1, 312 }; 313 314 int usb_gadget_handle_interrupts(int index) 315 { 316 dwc3_uboot_handle_interrupt(index); 317 return 0; 318 } 319 320 int board_usb_init(int index, enum usb_init_type init) 321 { 322 debug("%s: index %x\n", __func__, index); 323 324 #if defined(CONFIG_USB_GADGET_DOWNLOAD) 325 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME); 326 #endif 327 328 switch (index) { 329 case 0: 330 return dwc3_uboot_init(&dwc3_device_data0); 331 case 1: 332 return dwc3_uboot_init(&dwc3_device_data1); 333 }; 334 335 return -1; 336 } 337 338 int board_usb_cleanup(int index, enum usb_init_type init) 339 { 340 dwc3_uboot_exit(index); 341 return 0; 342 } 343 #endif 344