1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/io.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 int board_init(void) 19 { 20 printf("EL Level:\tEL%d\n", current_el()); 21 22 return 0; 23 } 24 25 int board_early_init_r(void) 26 { 27 u32 val; 28 29 val = readl(&crlapb_base->timestamp_ref_ctrl); 30 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 31 writel(val, &crlapb_base->timestamp_ref_ctrl); 32 33 /* Program freq register in System counter and enable system counter */ 34 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 35 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 36 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 37 &iou_scntr->counter_control_register); 38 39 return 0; 40 } 41 42 int dram_init(void) 43 { 44 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 45 46 return 0; 47 } 48 49 int timer_init(void) 50 { 51 return 0; 52 } 53 54 void reset_cpu(ulong addr) 55 { 56 } 57 58 #ifdef CONFIG_SCSI_AHCI_PLAT 59 void scsi_init(void) 60 { 61 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); 62 scsi_scan(1); 63 } 64 #endif 65 66 int board_eth_init(bd_t *bis) 67 { 68 u32 ret = 0; 69 70 #if defined(CONFIG_ZYNQ_GEM) 71 # if defined(CONFIG_ZYNQ_GEM0) 72 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 73 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 74 # endif 75 # if defined(CONFIG_ZYNQ_GEM1) 76 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 77 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 78 # endif 79 # if defined(CONFIG_ZYNQ_GEM2) 80 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, 81 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); 82 # endif 83 # if defined(CONFIG_ZYNQ_GEM3) 84 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, 85 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); 86 # endif 87 #endif 88 return ret; 89 } 90 91 #ifdef CONFIG_CMD_MMC 92 int board_mmc_init(bd_t *bd) 93 { 94 int ret = 0; 95 96 u32 ver = zynqmp_get_silicon_version(); 97 98 if (ver != ZYNQMP_CSU_VERSION_VELOCE) { 99 #if defined(CONFIG_ZYNQ_SDHCI) 100 # if defined(CONFIG_ZYNQ_SDHCI0) 101 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 102 # endif 103 # if defined(CONFIG_ZYNQ_SDHCI1) 104 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 105 # endif 106 #endif 107 } 108 109 return ret; 110 } 111 #endif 112 113 int board_late_init(void) 114 { 115 u32 reg = 0; 116 u8 bootmode; 117 118 reg = readl(&crlapb_base->boot_mode); 119 bootmode = reg & BOOT_MODES_MASK; 120 121 switch (bootmode) { 122 case SD_MODE: 123 case EMMC_MODE: 124 setenv("modeboot", "sdboot"); 125 break; 126 default: 127 printf("Invalid Boot Mode:0x%x\n", bootmode); 128 break; 129 } 130 131 return 0; 132 } 133