1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <zynqpl.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #ifdef CONFIG_FPGA 16 Xilinx_desc fpga; 17 18 /* It can be done differently */ 19 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 20 Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 21 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 22 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 23 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 24 Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 25 #endif 26 27 int board_init(void) 28 { 29 #ifdef CONFIG_FPGA 30 u32 idcode; 31 32 idcode = zynq_slcr_get_idcode(); 33 34 switch (idcode) { 35 case XILINX_ZYNQ_7010: 36 fpga = fpga010; 37 break; 38 case XILINX_ZYNQ_7015: 39 fpga = fpga015; 40 break; 41 case XILINX_ZYNQ_7020: 42 fpga = fpga020; 43 break; 44 case XILINX_ZYNQ_7030: 45 fpga = fpga030; 46 break; 47 case XILINX_ZYNQ_7045: 48 fpga = fpga045; 49 break; 50 case XILINX_ZYNQ_7100: 51 fpga = fpga100; 52 break; 53 } 54 #endif 55 56 #ifdef CONFIG_FPGA 57 fpga_init(); 58 fpga_add(fpga_xilinx, &fpga); 59 #endif 60 61 return 0; 62 } 63 64 int board_late_init(void) 65 { 66 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 67 case ZYNQ_BM_NOR: 68 setenv("modeboot", "norboot"); 69 break; 70 case ZYNQ_BM_SD: 71 setenv("modeboot", "sdboot"); 72 break; 73 case ZYNQ_BM_JTAG: 74 setenv("modeboot", "jtagboot"); 75 break; 76 default: 77 setenv("modeboot", ""); 78 break; 79 } 80 81 return 0; 82 } 83 84 int board_eth_init(bd_t *bis) 85 { 86 u32 ret = 0; 87 88 #ifdef CONFIG_XILINX_AXIEMAC 89 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 90 XILINX_AXIDMA_BASEADDR); 91 #endif 92 #ifdef CONFIG_XILINX_EMACLITE 93 u32 txpp = 0; 94 u32 rxpp = 0; 95 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 96 txpp = 1; 97 # endif 98 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 99 rxpp = 1; 100 # endif 101 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 102 txpp, rxpp); 103 #endif 104 105 #if defined(CONFIG_ZYNQ_GEM) 106 # if defined(CONFIG_ZYNQ_GEM0) 107 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 108 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 109 # endif 110 # if defined(CONFIG_ZYNQ_GEM1) 111 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 112 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 113 # endif 114 #endif 115 return ret; 116 } 117 118 #ifdef CONFIG_CMD_MMC 119 int board_mmc_init(bd_t *bd) 120 { 121 int ret = 0; 122 123 #if defined(CONFIG_ZYNQ_SDHCI) 124 # if defined(CONFIG_ZYNQ_SDHCI0) 125 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 126 # endif 127 # if defined(CONFIG_ZYNQ_SDHCI1) 128 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 129 # endif 130 #endif 131 return ret; 132 } 133 #endif 134 135 int dram_init(void) 136 { 137 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 138 139 zynq_ddrc_init(); 140 141 return 0; 142 } 143