1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 4 * (C) Copyright 2013 - 2018 Xilinx, Inc. 5 */ 6 7 #include <common.h> 8 #include <dm/uclass.h> 9 #include <fdtdec.h> 10 #include <fpga.h> 11 #include <mmc.h> 12 #include <watchdog.h> 13 #include <wdt.h> 14 #include <zynqpl.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/sys_proto.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 21 static struct udevice *watchdog_dev; 22 #endif 23 24 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) 25 int board_early_init_f(void) 26 { 27 # if defined(CONFIG_WDT) 28 /* bss is not cleared at time when watchdog_reset() is called */ 29 watchdog_dev = NULL; 30 # endif 31 32 return 0; 33 } 34 #endif 35 36 int board_init(void) 37 { 38 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 39 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 40 puts("Watchdog: Not found!\n"); 41 } else { 42 wdt_start(watchdog_dev, 0, 0); 43 puts("Watchdog: Started\n"); 44 } 45 # endif 46 47 return 0; 48 } 49 50 int board_late_init(void) 51 { 52 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 53 case ZYNQ_BM_QSPI: 54 env_set("modeboot", "qspiboot"); 55 break; 56 case ZYNQ_BM_NAND: 57 env_set("modeboot", "nandboot"); 58 break; 59 case ZYNQ_BM_NOR: 60 env_set("modeboot", "norboot"); 61 break; 62 case ZYNQ_BM_SD: 63 env_set("modeboot", "sdboot"); 64 break; 65 case ZYNQ_BM_JTAG: 66 env_set("modeboot", "jtagboot"); 67 break; 68 default: 69 env_set("modeboot", ""); 70 break; 71 } 72 73 return 0; 74 } 75 76 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 77 { 78 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 79 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 80 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 81 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 82 ethaddr, 6)) 83 printf("I2C EEPROM MAC address read failed\n"); 84 #endif 85 86 return 0; 87 } 88 89 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 90 int dram_init_banksize(void) 91 { 92 return fdtdec_setup_memory_banksize(); 93 } 94 95 int dram_init(void) 96 { 97 if (fdtdec_setup_memory_size() != 0) 98 return -EINVAL; 99 100 zynq_ddrc_init(); 101 102 return 0; 103 } 104 #else 105 int dram_init(void) 106 { 107 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 108 CONFIG_SYS_SDRAM_SIZE); 109 110 zynq_ddrc_init(); 111 112 return 0; 113 } 114 #endif 115 116 #if defined(CONFIG_WATCHDOG) 117 /* Called by macro WATCHDOG_RESET */ 118 void watchdog_reset(void) 119 { 120 # if !defined(CONFIG_SPL_BUILD) 121 static ulong next_reset; 122 ulong now; 123 124 if (!watchdog_dev) 125 return; 126 127 now = timer_get_us(); 128 129 /* Do not reset the watchdog too often */ 130 if (now > next_reset) { 131 wdt_reset(watchdog_dev); 132 next_reset = now + 1000; 133 } 134 # endif 135 } 136 #endif 137