xref: /openbmc/u-boot/board/xilinx/zynq/board.c (revision a4884831)
1 /*
2  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <fdtdec.h>
9 #include <fpga.h>
10 #include <mmc.h>
11 #include <netdev.h>
12 #include <zynqpl.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
15 
16 DECLARE_GLOBAL_DATA_PTR;
17 
18 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
19     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
20 static xilinx_desc fpga;
21 
22 /* It can be done differently */
23 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
24 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
25 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
26 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
27 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
28 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
29 #endif
30 
31 int board_init(void)
32 {
33 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
34     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
35 	u32 idcode;
36 
37 	idcode = zynq_slcr_get_idcode();
38 
39 	switch (idcode) {
40 	case XILINX_ZYNQ_7010:
41 		fpga = fpga010;
42 		break;
43 	case XILINX_ZYNQ_7015:
44 		fpga = fpga015;
45 		break;
46 	case XILINX_ZYNQ_7020:
47 		fpga = fpga020;
48 		break;
49 	case XILINX_ZYNQ_7030:
50 		fpga = fpga030;
51 		break;
52 	case XILINX_ZYNQ_7045:
53 		fpga = fpga045;
54 		break;
55 	case XILINX_ZYNQ_7100:
56 		fpga = fpga100;
57 		break;
58 	}
59 #endif
60 
61 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
62     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
63 	fpga_init();
64 	fpga_add(fpga_xilinx, &fpga);
65 #endif
66 
67 	return 0;
68 }
69 
70 int board_late_init(void)
71 {
72 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
73 	case ZYNQ_BM_NOR:
74 		setenv("modeboot", "norboot");
75 		break;
76 	case ZYNQ_BM_SD:
77 		setenv("modeboot", "sdboot");
78 		break;
79 	case ZYNQ_BM_JTAG:
80 		setenv("modeboot", "jtagboot");
81 		break;
82 	default:
83 		setenv("modeboot", "");
84 		break;
85 	}
86 
87 	return 0;
88 }
89 
90 int board_eth_init(bd_t *bis)
91 {
92 	u32 ret = 0;
93 
94 #ifdef CONFIG_XILINX_AXIEMAC
95 	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
96 						XILINX_AXIDMA_BASEADDR);
97 #endif
98 #ifdef CONFIG_XILINX_EMACLITE
99 	u32 txpp = 0;
100 	u32 rxpp = 0;
101 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
102 	txpp = 1;
103 # endif
104 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
105 	rxpp = 1;
106 # endif
107 	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
108 			txpp, rxpp);
109 #endif
110 
111 #if defined(CONFIG_ZYNQ_GEM)
112 # if defined(CONFIG_ZYNQ_GEM0)
113 	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
114 						CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
115 # endif
116 # if defined(CONFIG_ZYNQ_GEM1)
117 	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
118 						CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
119 # endif
120 #endif
121 	return ret;
122 }
123 
124 #ifdef CONFIG_CMD_MMC
125 int board_mmc_init(bd_t *bd)
126 {
127 	int ret = 0;
128 
129 #if defined(CONFIG_ZYNQ_SDHCI)
130 # if defined(CONFIG_ZYNQ_SDHCI0)
131 	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
132 # endif
133 # if defined(CONFIG_ZYNQ_SDHCI1)
134 	ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
135 # endif
136 #endif
137 	return ret;
138 }
139 #endif
140 
141 int dram_init(void)
142 {
143 #ifdef CONFIG_OF_CONTROL
144 	int node;
145 	fdt_addr_t addr;
146 	fdt_size_t size;
147 	const void *blob = gd->fdt_blob;
148 
149 	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
150 					     "memory", 7);
151 	if (node == -FDT_ERR_NOTFOUND) {
152 		debug("ZYNQ DRAM: Can't get memory node\n");
153 		return -1;
154 	}
155 	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
156 	if (addr == FDT_ADDR_T_NONE || size == 0) {
157 		debug("ZYNQ DRAM: Can't get base address or size\n");
158 		return -1;
159 	}
160 	gd->ram_size = size;
161 #else
162 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
163 #endif
164 	zynq_ddrc_init();
165 
166 	return 0;
167 }
168