1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * (C) Copyright 2013 - 2018 Xilinx, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm/uclass.h> 10 #include <fdtdec.h> 11 #include <fpga.h> 12 #include <mmc.h> 13 #include <wdt.h> 14 #include <zynqpl.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/ps7_init_gpl.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 22 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 23 static xilinx_desc fpga; 24 25 /* It can be done differently */ 26 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); 27 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 28 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); 29 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); 30 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 31 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 32 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 33 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); 34 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 35 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 36 #endif 37 38 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 39 static struct udevice *watchdog_dev; 40 #endif 41 42 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) 43 int board_early_init_f(void) 44 { 45 # if defined(CONFIG_WDT) 46 /* bss is not cleared at time when watchdog_reset() is called */ 47 watchdog_dev = NULL; 48 # endif 49 50 return 0; 51 } 52 #endif 53 54 int board_init(void) 55 { 56 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 57 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 58 u32 idcode; 59 60 idcode = zynq_slcr_get_idcode(); 61 62 switch (idcode) { 63 case XILINX_ZYNQ_7007S: 64 fpga = fpga007s; 65 break; 66 case XILINX_ZYNQ_7010: 67 fpga = fpga010; 68 break; 69 case XILINX_ZYNQ_7012S: 70 fpga = fpga012s; 71 break; 72 case XILINX_ZYNQ_7014S: 73 fpga = fpga014s; 74 break; 75 case XILINX_ZYNQ_7015: 76 fpga = fpga015; 77 break; 78 case XILINX_ZYNQ_7020: 79 fpga = fpga020; 80 break; 81 case XILINX_ZYNQ_7030: 82 fpga = fpga030; 83 break; 84 case XILINX_ZYNQ_7035: 85 fpga = fpga035; 86 break; 87 case XILINX_ZYNQ_7045: 88 fpga = fpga045; 89 break; 90 case XILINX_ZYNQ_7100: 91 fpga = fpga100; 92 break; 93 } 94 #endif 95 96 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 97 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 98 puts("Watchdog: Not found!\n"); 99 } else { 100 wdt_start(watchdog_dev, 0, 0); 101 puts("Watchdog: Started\n"); 102 } 103 # endif 104 105 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 106 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 107 fpga_init(); 108 fpga_add(fpga_xilinx, &fpga); 109 #endif 110 111 return 0; 112 } 113 114 int board_late_init(void) 115 { 116 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 117 case ZYNQ_BM_QSPI: 118 env_set("modeboot", "qspiboot"); 119 break; 120 case ZYNQ_BM_NAND: 121 env_set("modeboot", "nandboot"); 122 break; 123 case ZYNQ_BM_NOR: 124 env_set("modeboot", "norboot"); 125 break; 126 case ZYNQ_BM_SD: 127 env_set("modeboot", "sdboot"); 128 break; 129 case ZYNQ_BM_JTAG: 130 env_set("modeboot", "jtagboot"); 131 break; 132 default: 133 env_set("modeboot", ""); 134 break; 135 } 136 137 return 0; 138 } 139 140 #ifdef CONFIG_DISPLAY_BOARDINFO 141 int checkboard(void) 142 { 143 u32 version = zynq_get_silicon_version(); 144 145 version <<= 1; 146 if (version > (PCW_SILICON_VERSION_3 << 1)) 147 version += 1; 148 149 puts("Board: Xilinx Zynq\n"); 150 printf("Silicon: v%d.%d\n", version >> 1, version & 1); 151 152 return 0; 153 } 154 #endif 155 156 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 157 { 158 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 159 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 160 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 161 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 162 ethaddr, 6)) 163 printf("I2C EEPROM MAC address read failed\n"); 164 #endif 165 166 return 0; 167 } 168 169 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 170 int dram_init_banksize(void) 171 { 172 return fdtdec_setup_memory_banksize(); 173 } 174 175 int dram_init(void) 176 { 177 if (fdtdec_setup_memory_size() != 0) 178 return -EINVAL; 179 180 zynq_ddrc_init(); 181 182 return 0; 183 } 184 #else 185 int dram_init(void) 186 { 187 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 188 189 zynq_ddrc_init(); 190 191 return 0; 192 } 193 #endif 194 195 #if defined(CONFIG_WATCHDOG) 196 /* Called by macro WATCHDOG_RESET */ 197 void watchdog_reset(void) 198 { 199 # if !defined(CONFIG_SPL_BUILD) 200 static ulong next_reset; 201 ulong now; 202 203 if (!watchdog_dev) 204 return; 205 206 now = timer_get_us(); 207 208 /* Do not reset the watchdog too often */ 209 if (now > next_reset) { 210 wdt_reset(watchdog_dev); 211 next_reset = now + 1000; 212 } 213 # endif 214 } 215 #endif 216