1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <zynqpl.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #ifdef CONFIG_FPGA 16 Xilinx_desc fpga; 17 18 /* It can be done differently */ 19 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 20 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 21 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 22 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 23 Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 24 #endif 25 26 int board_init(void) 27 { 28 #ifdef CONFIG_FPGA 29 u32 idcode; 30 31 idcode = zynq_slcr_get_idcode(); 32 33 switch (idcode) { 34 case XILINX_ZYNQ_7010: 35 fpga = fpga010; 36 break; 37 case XILINX_ZYNQ_7020: 38 fpga = fpga020; 39 break; 40 case XILINX_ZYNQ_7030: 41 fpga = fpga030; 42 break; 43 case XILINX_ZYNQ_7045: 44 fpga = fpga045; 45 break; 46 case XILINX_ZYNQ_7100: 47 fpga = fpga100; 48 break; 49 } 50 #endif 51 52 icache_enable(); 53 54 #ifdef CONFIG_FPGA 55 fpga_init(); 56 fpga_add(fpga_xilinx, &fpga); 57 #endif 58 59 return 0; 60 } 61 62 63 #ifdef CONFIG_CMD_NET 64 int board_eth_init(bd_t *bis) 65 { 66 u32 ret = 0; 67 68 #ifdef CONFIG_XILINX_AXIEMAC 69 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 70 XILINX_AXIDMA_BASEADDR); 71 #endif 72 #ifdef CONFIG_XILINX_EMACLITE 73 u32 txpp = 0; 74 u32 rxpp = 0; 75 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 76 txpp = 1; 77 # endif 78 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 79 rxpp = 1; 80 # endif 81 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 82 txpp, rxpp); 83 #endif 84 85 #if defined(CONFIG_ZYNQ_GEM) 86 # if defined(CONFIG_ZYNQ_GEM0) 87 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 88 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 89 # endif 90 # if defined(CONFIG_ZYNQ_GEM1) 91 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 92 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 93 # endif 94 #endif 95 return ret; 96 } 97 #endif 98 99 #ifdef CONFIG_CMD_MMC 100 int board_mmc_init(bd_t *bd) 101 { 102 int ret = 0; 103 104 #if defined(CONFIG_ZYNQ_SDHCI) 105 # if defined(CONFIG_ZYNQ_SDHCI0) 106 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 107 # endif 108 # if defined(CONFIG_ZYNQ_SDHCI1) 109 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 110 # endif 111 #endif 112 return ret; 113 } 114 #endif 115 116 int dram_init(void) 117 { 118 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 119 120 zynq_ddrc_init(); 121 122 return 0; 123 } 124