1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <netdev.h> 10 #include <zynqpl.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/sys_proto.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #ifdef CONFIG_FPGA 17 Xilinx_desc fpga; 18 19 /* It can be done differently */ 20 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 21 Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 22 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 23 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 24 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 25 Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 26 #endif 27 28 int board_init(void) 29 { 30 #ifdef CONFIG_FPGA 31 u32 idcode; 32 33 idcode = zynq_slcr_get_idcode(); 34 35 switch (idcode) { 36 case XILINX_ZYNQ_7010: 37 fpga = fpga010; 38 break; 39 case XILINX_ZYNQ_7015: 40 fpga = fpga015; 41 break; 42 case XILINX_ZYNQ_7020: 43 fpga = fpga020; 44 break; 45 case XILINX_ZYNQ_7030: 46 fpga = fpga030; 47 break; 48 case XILINX_ZYNQ_7045: 49 fpga = fpga045; 50 break; 51 case XILINX_ZYNQ_7100: 52 fpga = fpga100; 53 break; 54 } 55 #endif 56 57 #ifdef CONFIG_FPGA 58 fpga_init(); 59 fpga_add(fpga_xilinx, &fpga); 60 #endif 61 62 return 0; 63 } 64 65 int board_late_init(void) 66 { 67 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 68 case ZYNQ_BM_NOR: 69 setenv("modeboot", "norboot"); 70 break; 71 case ZYNQ_BM_SD: 72 setenv("modeboot", "sdboot"); 73 break; 74 case ZYNQ_BM_JTAG: 75 setenv("modeboot", "jtagboot"); 76 break; 77 default: 78 setenv("modeboot", ""); 79 break; 80 } 81 82 return 0; 83 } 84 85 int board_eth_init(bd_t *bis) 86 { 87 u32 ret = 0; 88 89 #ifdef CONFIG_XILINX_AXIEMAC 90 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 91 XILINX_AXIDMA_BASEADDR); 92 #endif 93 #ifdef CONFIG_XILINX_EMACLITE 94 u32 txpp = 0; 95 u32 rxpp = 0; 96 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 97 txpp = 1; 98 # endif 99 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 100 rxpp = 1; 101 # endif 102 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 103 txpp, rxpp); 104 #endif 105 106 #if defined(CONFIG_ZYNQ_GEM) 107 # if defined(CONFIG_ZYNQ_GEM0) 108 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 109 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 110 # endif 111 # if defined(CONFIG_ZYNQ_GEM1) 112 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 113 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 114 # endif 115 #endif 116 return ret; 117 } 118 119 #ifdef CONFIG_CMD_MMC 120 int board_mmc_init(bd_t *bd) 121 { 122 int ret = 0; 123 124 #if defined(CONFIG_ZYNQ_SDHCI) 125 # if defined(CONFIG_ZYNQ_SDHCI0) 126 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 127 # endif 128 # if defined(CONFIG_ZYNQ_SDHCI1) 129 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 130 # endif 131 #endif 132 return ret; 133 } 134 #endif 135 136 int dram_init(void) 137 { 138 #ifdef CONFIG_OF_CONTROL 139 int node; 140 fdt_addr_t addr; 141 fdt_size_t size; 142 const void *blob = gd->fdt_blob; 143 144 node = fdt_node_offset_by_prop_value(blob, -1, "device_type", 145 "memory", 7); 146 if (node == -FDT_ERR_NOTFOUND) { 147 debug("ZYNQ DRAM: Can't get memory node\n"); 148 return -1; 149 } 150 addr = fdtdec_get_addr_size(blob, node, "reg", &size); 151 if (addr == FDT_ADDR_T_NONE || size == 0) { 152 debug("ZYNQ DRAM: Can't get base address or size\n"); 153 return -1; 154 } 155 gd->ram_size = size; 156 #else 157 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 158 #endif 159 zynq_ddrc_init(); 160 161 return 0; 162 } 163