1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <zynqpl.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 /* Bootmode setting values */ 16 #define ZYNQ_BM_MASK 0x0F 17 #define ZYNQ_BM_NOR 0x02 18 #define ZYNQ_BM_SD 0x05 19 #define ZYNQ_BM_JTAG 0x0 20 21 #ifdef CONFIG_FPGA 22 Xilinx_desc fpga; 23 24 /* It can be done differently */ 25 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 26 Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 27 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 28 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 29 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 30 Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 31 #endif 32 33 int board_init(void) 34 { 35 #ifdef CONFIG_FPGA 36 u32 idcode; 37 38 idcode = zynq_slcr_get_idcode(); 39 40 switch (idcode) { 41 case XILINX_ZYNQ_7010: 42 fpga = fpga010; 43 break; 44 case XILINX_ZYNQ_7015: 45 fpga = fpga015; 46 break; 47 case XILINX_ZYNQ_7020: 48 fpga = fpga020; 49 break; 50 case XILINX_ZYNQ_7030: 51 fpga = fpga030; 52 break; 53 case XILINX_ZYNQ_7045: 54 fpga = fpga045; 55 break; 56 case XILINX_ZYNQ_7100: 57 fpga = fpga100; 58 break; 59 } 60 #endif 61 62 icache_enable(); 63 64 #ifdef CONFIG_FPGA 65 fpga_init(); 66 fpga_add(fpga_xilinx, &fpga); 67 #endif 68 69 return 0; 70 } 71 72 int board_late_init(void) 73 { 74 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 75 case ZYNQ_BM_NOR: 76 setenv("modeboot", "norboot"); 77 break; 78 case ZYNQ_BM_SD: 79 setenv("modeboot", "sdboot"); 80 break; 81 case ZYNQ_BM_JTAG: 82 setenv("modeboot", "jtagboot"); 83 break; 84 default: 85 setenv("modeboot", ""); 86 break; 87 } 88 89 return 0; 90 } 91 92 #ifdef CONFIG_CMD_NET 93 int board_eth_init(bd_t *bis) 94 { 95 u32 ret = 0; 96 97 #ifdef CONFIG_XILINX_AXIEMAC 98 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 99 XILINX_AXIDMA_BASEADDR); 100 #endif 101 #ifdef CONFIG_XILINX_EMACLITE 102 u32 txpp = 0; 103 u32 rxpp = 0; 104 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 105 txpp = 1; 106 # endif 107 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 108 rxpp = 1; 109 # endif 110 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 111 txpp, rxpp); 112 #endif 113 114 #if defined(CONFIG_ZYNQ_GEM) 115 # if defined(CONFIG_ZYNQ_GEM0) 116 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 117 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 118 # endif 119 # if defined(CONFIG_ZYNQ_GEM1) 120 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 121 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 122 # endif 123 #endif 124 return ret; 125 } 126 #endif 127 128 #ifdef CONFIG_CMD_MMC 129 int board_mmc_init(bd_t *bd) 130 { 131 int ret = 0; 132 133 #if defined(CONFIG_ZYNQ_SDHCI) 134 # if defined(CONFIG_ZYNQ_SDHCI0) 135 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 136 # endif 137 # if defined(CONFIG_ZYNQ_SDHCI1) 138 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 139 # endif 140 #endif 141 return ret; 142 } 143 #endif 144 145 int dram_init(void) 146 { 147 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 148 149 zynq_ddrc_init(); 150 151 return 0; 152 } 153