1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <fpga.h> 10 #include <mmc.h> 11 #include <zynqpl.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/ps7_init_gpl.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 19 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 20 static xilinx_desc fpga; 21 22 /* It can be done differently */ 23 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); 24 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 25 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); 26 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); 27 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 28 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 29 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 30 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); 31 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 32 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 33 #endif 34 35 int board_init(void) 36 { 37 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 38 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 39 u32 idcode; 40 41 idcode = zynq_slcr_get_idcode(); 42 43 switch (idcode) { 44 case XILINX_ZYNQ_7007S: 45 fpga = fpga007s; 46 break; 47 case XILINX_ZYNQ_7010: 48 fpga = fpga010; 49 break; 50 case XILINX_ZYNQ_7012S: 51 fpga = fpga012s; 52 break; 53 case XILINX_ZYNQ_7014S: 54 fpga = fpga014s; 55 break; 56 case XILINX_ZYNQ_7015: 57 fpga = fpga015; 58 break; 59 case XILINX_ZYNQ_7020: 60 fpga = fpga020; 61 break; 62 case XILINX_ZYNQ_7030: 63 fpga = fpga030; 64 break; 65 case XILINX_ZYNQ_7035: 66 fpga = fpga035; 67 break; 68 case XILINX_ZYNQ_7045: 69 fpga = fpga045; 70 break; 71 case XILINX_ZYNQ_7100: 72 fpga = fpga100; 73 break; 74 } 75 #endif 76 77 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 78 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 79 fpga_init(); 80 fpga_add(fpga_xilinx, &fpga); 81 #endif 82 83 return 0; 84 } 85 86 int board_late_init(void) 87 { 88 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 89 case ZYNQ_BM_QSPI: 90 env_set("modeboot", "qspiboot"); 91 break; 92 case ZYNQ_BM_NAND: 93 env_set("modeboot", "nandboot"); 94 break; 95 case ZYNQ_BM_NOR: 96 env_set("modeboot", "norboot"); 97 break; 98 case ZYNQ_BM_SD: 99 env_set("modeboot", "sdboot"); 100 break; 101 case ZYNQ_BM_JTAG: 102 env_set("modeboot", "jtagboot"); 103 break; 104 default: 105 env_set("modeboot", ""); 106 break; 107 } 108 109 return 0; 110 } 111 112 #ifdef CONFIG_DISPLAY_BOARDINFO 113 int checkboard(void) 114 { 115 u32 version = zynq_get_silicon_version(); 116 117 version <<= 1; 118 if (version > (PCW_SILICON_VERSION_3 << 1)) 119 version += 1; 120 121 puts("Board: Xilinx Zynq\n"); 122 printf("Silicon: v%d.%d\n", version >> 1, version & 1); 123 124 return 0; 125 } 126 #endif 127 128 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 129 { 130 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 131 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 132 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 133 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 134 ethaddr, 6)) 135 printf("I2C EEPROM MAC address read failed\n"); 136 #endif 137 138 return 0; 139 } 140 141 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 142 int dram_init_banksize(void) 143 { 144 return fdtdec_setup_memory_banksize(); 145 } 146 147 int dram_init(void) 148 { 149 if (fdtdec_setup_memory_size() != 0) 150 return -EINVAL; 151 152 zynq_ddrc_init(); 153 154 return 0; 155 } 156 #else 157 int dram_init(void) 158 { 159 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 160 161 zynq_ddrc_init(); 162 163 return 0; 164 } 165 #endif 166