1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 4 * (C) Copyright 2013 - 2018 Xilinx, Inc. 5 */ 6 7 #include <common.h> 8 #include <dm/uclass.h> 9 #include <fdtdec.h> 10 #include <fpga.h> 11 #include <mmc.h> 12 #include <wdt.h> 13 #include <zynqpl.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/ps7_init_gpl.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 21 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 22 static xilinx_desc fpga; 23 24 /* It can be done differently */ 25 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); 26 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 27 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); 28 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); 29 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 30 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 31 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 32 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); 33 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 34 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 35 #endif 36 37 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 38 static struct udevice *watchdog_dev; 39 #endif 40 41 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) 42 int board_early_init_f(void) 43 { 44 # if defined(CONFIG_WDT) 45 /* bss is not cleared at time when watchdog_reset() is called */ 46 watchdog_dev = NULL; 47 # endif 48 49 return 0; 50 } 51 #endif 52 53 int board_init(void) 54 { 55 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 56 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 57 u32 idcode; 58 59 idcode = zynq_slcr_get_idcode(); 60 61 switch (idcode) { 62 case XILINX_ZYNQ_7007S: 63 fpga = fpga007s; 64 break; 65 case XILINX_ZYNQ_7010: 66 fpga = fpga010; 67 break; 68 case XILINX_ZYNQ_7012S: 69 fpga = fpga012s; 70 break; 71 case XILINX_ZYNQ_7014S: 72 fpga = fpga014s; 73 break; 74 case XILINX_ZYNQ_7015: 75 fpga = fpga015; 76 break; 77 case XILINX_ZYNQ_7020: 78 fpga = fpga020; 79 break; 80 case XILINX_ZYNQ_7030: 81 fpga = fpga030; 82 break; 83 case XILINX_ZYNQ_7035: 84 fpga = fpga035; 85 break; 86 case XILINX_ZYNQ_7045: 87 fpga = fpga045; 88 break; 89 case XILINX_ZYNQ_7100: 90 fpga = fpga100; 91 break; 92 } 93 #endif 94 95 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 96 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 97 puts("Watchdog: Not found!\n"); 98 } else { 99 wdt_start(watchdog_dev, 0, 0); 100 puts("Watchdog: Started\n"); 101 } 102 # endif 103 104 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 105 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 106 fpga_init(); 107 fpga_add(fpga_xilinx, &fpga); 108 #endif 109 110 return 0; 111 } 112 113 int board_late_init(void) 114 { 115 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 116 case ZYNQ_BM_QSPI: 117 env_set("modeboot", "qspiboot"); 118 break; 119 case ZYNQ_BM_NAND: 120 env_set("modeboot", "nandboot"); 121 break; 122 case ZYNQ_BM_NOR: 123 env_set("modeboot", "norboot"); 124 break; 125 case ZYNQ_BM_SD: 126 env_set("modeboot", "sdboot"); 127 break; 128 case ZYNQ_BM_JTAG: 129 env_set("modeboot", "jtagboot"); 130 break; 131 default: 132 env_set("modeboot", ""); 133 break; 134 } 135 136 return 0; 137 } 138 139 #ifdef CONFIG_DISPLAY_BOARDINFO 140 int checkboard(void) 141 { 142 u32 version = zynq_get_silicon_version(); 143 144 version <<= 1; 145 if (version > (PCW_SILICON_VERSION_3 << 1)) 146 version += 1; 147 148 puts("Board: Xilinx Zynq\n"); 149 printf("Silicon: v%d.%d\n", version >> 1, version & 1); 150 151 return 0; 152 } 153 #endif 154 155 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 156 { 157 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 158 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 159 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 160 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 161 ethaddr, 6)) 162 printf("I2C EEPROM MAC address read failed\n"); 163 #endif 164 165 return 0; 166 } 167 168 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 169 int dram_init_banksize(void) 170 { 171 return fdtdec_setup_memory_banksize(); 172 } 173 174 int dram_init(void) 175 { 176 if (fdtdec_setup_memory_size() != 0) 177 return -EINVAL; 178 179 zynq_ddrc_init(); 180 181 return 0; 182 } 183 #else 184 int dram_init(void) 185 { 186 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 187 CONFIG_SYS_SDRAM_SIZE); 188 189 zynq_ddrc_init(); 190 191 return 0; 192 } 193 #endif 194 195 #if defined(CONFIG_WATCHDOG) 196 /* Called by macro WATCHDOG_RESET */ 197 void watchdog_reset(void) 198 { 199 # if !defined(CONFIG_SPL_BUILD) 200 static ulong next_reset; 201 ulong now; 202 203 if (!watchdog_dev) 204 return; 205 206 now = timer_get_us(); 207 208 /* Do not reset the watchdog too often */ 209 if (now > next_reset) { 210 wdt_reset(watchdog_dev); 211 next_reset = now + 1000; 212 } 213 # endif 214 } 215 #endif 216