1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <fpga.h> 10 #include <mmc.h> 11 #include <zynqpl.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 18 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 19 static xilinx_desc fpga; 20 21 /* It can be done differently */ 22 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); 23 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 24 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); 25 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); 26 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 27 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 28 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 29 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); 30 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 31 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 32 #endif 33 34 int board_init(void) 35 { 36 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 37 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 38 u32 idcode; 39 40 idcode = zynq_slcr_get_idcode(); 41 42 switch (idcode) { 43 case XILINX_ZYNQ_7007S: 44 fpga = fpga007s; 45 break; 46 case XILINX_ZYNQ_7010: 47 fpga = fpga010; 48 break; 49 case XILINX_ZYNQ_7012S: 50 fpga = fpga012s; 51 break; 52 case XILINX_ZYNQ_7014S: 53 fpga = fpga014s; 54 break; 55 case XILINX_ZYNQ_7015: 56 fpga = fpga015; 57 break; 58 case XILINX_ZYNQ_7020: 59 fpga = fpga020; 60 break; 61 case XILINX_ZYNQ_7030: 62 fpga = fpga030; 63 break; 64 case XILINX_ZYNQ_7035: 65 fpga = fpga035; 66 break; 67 case XILINX_ZYNQ_7045: 68 fpga = fpga045; 69 break; 70 case XILINX_ZYNQ_7100: 71 fpga = fpga100; 72 break; 73 } 74 #endif 75 76 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 77 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 78 fpga_init(); 79 fpga_add(fpga_xilinx, &fpga); 80 #endif 81 82 return 0; 83 } 84 85 int board_late_init(void) 86 { 87 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 88 case ZYNQ_BM_QSPI: 89 setenv("modeboot", "qspiboot"); 90 break; 91 case ZYNQ_BM_NAND: 92 setenv("modeboot", "nandboot"); 93 break; 94 case ZYNQ_BM_NOR: 95 setenv("modeboot", "norboot"); 96 break; 97 case ZYNQ_BM_SD: 98 setenv("modeboot", "sdboot"); 99 break; 100 case ZYNQ_BM_JTAG: 101 setenv("modeboot", "jtagboot"); 102 break; 103 default: 104 setenv("modeboot", ""); 105 break; 106 } 107 108 return 0; 109 } 110 111 #ifdef CONFIG_DISPLAY_BOARDINFO 112 int checkboard(void) 113 { 114 puts("Board: Xilinx Zynq\n"); 115 return 0; 116 } 117 #endif 118 119 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 120 { 121 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 122 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 123 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 124 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 125 ethaddr, 6)) 126 printf("I2C EEPROM MAC address read failed\n"); 127 #endif 128 129 return 0; 130 } 131 132 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 133 int dram_init_banksize(void) 134 { 135 fdtdec_setup_memory_banksize(); 136 137 return 0; 138 } 139 140 int dram_init(void) 141 { 142 if (fdtdec_setup_memory_size() != 0) 143 return -EINVAL; 144 145 zynq_ddrc_init(); 146 147 return 0; 148 } 149 #else 150 int dram_init(void) 151 { 152 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 153 154 zynq_ddrc_init(); 155 156 return 0; 157 } 158 #endif 159