1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 4 * (C) Copyright 2013 - 2018 Xilinx, Inc. 5 */ 6 7 #include <common.h> 8 #include <dm/uclass.h> 9 #include <fdtdec.h> 10 #include <fpga.h> 11 #include <mmc.h> 12 #include <wdt.h> 13 #include <zynqpl.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/sys_proto.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 20 static struct udevice *watchdog_dev; 21 #endif 22 23 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) 24 int board_early_init_f(void) 25 { 26 # if defined(CONFIG_WDT) 27 /* bss is not cleared at time when watchdog_reset() is called */ 28 watchdog_dev = NULL; 29 # endif 30 31 return 0; 32 } 33 #endif 34 35 int board_init(void) 36 { 37 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 38 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 39 puts("Watchdog: Not found!\n"); 40 } else { 41 wdt_start(watchdog_dev, 0, 0); 42 puts("Watchdog: Started\n"); 43 } 44 # endif 45 46 return 0; 47 } 48 49 int board_late_init(void) 50 { 51 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 52 case ZYNQ_BM_QSPI: 53 env_set("modeboot", "qspiboot"); 54 break; 55 case ZYNQ_BM_NAND: 56 env_set("modeboot", "nandboot"); 57 break; 58 case ZYNQ_BM_NOR: 59 env_set("modeboot", "norboot"); 60 break; 61 case ZYNQ_BM_SD: 62 env_set("modeboot", "sdboot"); 63 break; 64 case ZYNQ_BM_JTAG: 65 env_set("modeboot", "jtagboot"); 66 break; 67 default: 68 env_set("modeboot", ""); 69 break; 70 } 71 72 return 0; 73 } 74 75 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 76 { 77 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 78 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 79 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 80 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 81 ethaddr, 6)) 82 printf("I2C EEPROM MAC address read failed\n"); 83 #endif 84 85 return 0; 86 } 87 88 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 89 int dram_init_banksize(void) 90 { 91 return fdtdec_setup_memory_banksize(); 92 } 93 94 int dram_init(void) 95 { 96 if (fdtdec_setup_memory_size() != 0) 97 return -EINVAL; 98 99 zynq_ddrc_init(); 100 101 return 0; 102 } 103 #else 104 int dram_init(void) 105 { 106 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 107 CONFIG_SYS_SDRAM_SIZE); 108 109 zynq_ddrc_init(); 110 111 return 0; 112 } 113 #endif 114 115 #if defined(CONFIG_WATCHDOG) 116 /* Called by macro WATCHDOG_RESET */ 117 void watchdog_reset(void) 118 { 119 # if !defined(CONFIG_SPL_BUILD) 120 static ulong next_reset; 121 ulong now; 122 123 if (!watchdog_dev) 124 return; 125 126 now = timer_get_us(); 127 128 /* Do not reset the watchdog too often */ 129 if (now > next_reset) { 130 wdt_reset(watchdog_dev); 131 next_reset = now + 1000; 132 } 133 # endif 134 } 135 #endif 136