1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2014 - 2018 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <malloc.h> 10 #include <asm/io.h> 11 #include <asm/arch/hardware.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 int board_init(void) 16 { 17 printf("EL Level:\tEL%d\n", current_el()); 18 19 return 0; 20 } 21 22 int board_early_init_r(void) 23 { 24 u32 val; 25 26 if (current_el() != 3) 27 return 0; 28 29 debug("iou_switch ctrl div0 %x\n", 30 readl(&crlapb_base->iou_switch_ctrl)); 31 32 writel(IOU_SWITCH_CTRL_CLKACT_BIT | 33 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), 34 &crlapb_base->iou_switch_ctrl); 35 36 /* Global timer init - Program time stamp reference clk */ 37 val = readl(&crlapb_base->timestamp_ref_ctrl); 38 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 39 writel(val, &crlapb_base->timestamp_ref_ctrl); 40 41 debug("ref ctrl 0x%x\n", 42 readl(&crlapb_base->timestamp_ref_ctrl)); 43 44 /* Clear reset of timestamp reg */ 45 writel(0, &crlapb_base->rst_timestamp); 46 47 /* 48 * Program freq register in System counter and 49 * enable system counter. 50 */ 51 writel(COUNTER_FREQUENCY, 52 &iou_scntr_secure->base_frequency_id_register); 53 54 debug("counter val 0x%x\n", 55 readl(&iou_scntr_secure->base_frequency_id_register)); 56 57 writel(IOU_SCNTRS_CONTROL_EN, 58 &iou_scntr_secure->counter_control_register); 59 60 debug("scntrs control 0x%x\n", 61 readl(&iou_scntr_secure->counter_control_register)); 62 debug("timer 0x%llx\n", get_ticks()); 63 debug("timer 0x%llx\n", get_ticks()); 64 65 return 0; 66 } 67 68 int dram_init_banksize(void) 69 { 70 fdtdec_setup_memory_banksize(); 71 72 return 0; 73 } 74 75 int dram_init(void) 76 { 77 if (fdtdec_setup_mem_size_base() != 0) 78 return -EINVAL; 79 80 return 0; 81 } 82 83 void reset_cpu(ulong addr) 84 { 85 } 86