1 /*
2  * (C) Copyright 2007 Michal Simek
3  *
4  * Michal  SIMEK <monstr@monstr.eu>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  *
8  * CAUTION: This file is a faked configuration !!!
9  *          There is no real target for the microblaze-generic
10  *          configuration. You have to replace this file with
11  *          the generated file from your Xilinx design flow.
12  */
13 
14 #define XILINX_BOARD_NAME	microblaze-generic
15 
16 /* System Clock Frequency */
17 #define XILINX_CLOCK_FREQ	100000000
18 
19 /* Microblaze is microblaze_0 */
20 #define XILINX_USE_MSR_INSTR	1
21 #define XILINX_FSL_NUMBER	3
22 
23 /* Interrupt controller is opb_intc_0 */
24 #define XILINX_INTC_BASEADDR	0x41200000
25 #define XILINX_INTC_NUM_INTR_INPUTS	6
26 
27 /* Timer pheriphery is opb_timer_1 */
28 #define XILINX_TIMER_BASEADDR	0x41c00000
29 #define XILINX_TIMER_IRQ	0
30 
31 /* Uart pheriphery is RS232_Uart */
32 #define XILINX_UARTLITE_BASEADDR	0x40600000
33 #define XILINX_UARTLITE_BAUDRATE	115200
34 
35 /* IIC pheriphery is IIC_EEPROM */
36 #define XILINX_IIC_0_BASEADDR	0x40800000
37 #define XILINX_IIC_0_FREQ	100000
38 #define XILINX_IIC_0_BIT	0
39 
40 /* GPIO is LEDs_4Bit*/
41 #define XILINX_GPIO_BASEADDR	0x40000000
42 
43 /* Flash Memory is FLASH_2Mx32 */
44 #define XILINX_FLASH_START	0x2c000000
45 #define XILINX_FLASH_SIZE	0x00800000
46 
47 /* Main Memory is DDR_SDRAM_64Mx32 */
48 #define XILINX_RAM_START	0x28000000
49 #define XILINX_RAM_SIZE	0x04000000
50 
51 /* Sysace Controller is SysACE_CompactFlash */
52 #define XILINX_SYSACE_BASEADDR	0x41800000
53 #define XILINX_SYSACE_HIGHADDR	0x4180ffff
54 #define XILINX_SYSACE_MEM_WIDTH	16
55 
56 /* Ethernet controller is Ethernet_MAC */
57 #define XILINX_EMACLITE_BASEADDR       0x40C00000
58 
59 /* Watchdog IP is wxi_timebase_wdt_0 */
60 #define XILINX_WATCHDOG_BASEADDR	0x50000000
61 #define XILINX_WATCHDOG_IRQ		1
62