1 /* 2 * (C) Copyright 2007 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 * 24 * CAUTION: This file is a faked configuration !!! 25 * There is no real target for the microblaze-generic 26 * configuration. You have to replace this file with 27 * the generated file from your Xilinx design flow. 28 */ 29 30 #define XILINX_BOARD_NAME microblaze-generic 31 32 /* System Clock Frequency */ 33 #define XILINX_CLOCK_FREQ 100000000 34 35 /* Microblaze is microblaze_0 */ 36 #define XILINX_USE_MSR_INSTR 1 37 #define XILINX_FSL_NUMBER 3 38 39 /* Interrupt controller is opb_intc_0 */ 40 #define XILINX_INTC_BASEADDR 0x41200000 41 #define XILINX_INTC_NUM_INTR_INPUTS 6 42 43 /* Timer pheriphery is opb_timer_1 */ 44 #define XILINX_TIMER_BASEADDR 0x41c00000 45 #define XILINX_TIMER_IRQ 0 46 47 /* Uart pheriphery is RS232_Uart */ 48 #define XILINX_UARTLITE_BASEADDR 0x40600000 49 #define XILINX_UARTLITE_BAUDRATE 115200 50 51 /* IIC pheriphery is IIC_EEPROM */ 52 #define XILINX_IIC_0_BASEADDR 0x40800000 53 #define XILINX_IIC_0_FREQ 100000 54 #define XILINX_IIC_0_BIT 0 55 56 /* GPIO is LEDs_4Bit*/ 57 #define XILINX_GPIO_BASEADDR 0x40000000 58 59 /* Flash Memory is FLASH_2Mx32 */ 60 #define XILINX_FLASH_START 0x2c000000 61 #define XILINX_FLASH_SIZE 0x00800000 62 63 /* Main Memory is DDR_SDRAM_64Mx32 */ 64 #define XILINX_RAM_START 0x28000000 65 #define XILINX_RAM_SIZE 0x04000000 66 67 /* Sysace Controller is SysACE_CompactFlash */ 68 #define XILINX_SYSACE_BASEADDR 0x41800000 69 #define XILINX_SYSACE_HIGHADDR 0x4180ffff 70 #define XILINX_SYSACE_MEM_WIDTH 16 71 72 /* Ethernet controller is Ethernet_MAC */ 73 #define XILINX_EMACLITE_BASEADDR 0x40C00000 74 75 /* LL_TEMAC Ethernet controller */ 76 #define XILINX_LLTEMAC_BASEADDR 0x44000000 77 #define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 78 #define XILINX_LLTEMAC_BASEADDR1 0x44200000 79 #define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 80 81 /* Watchdog IP is wxi_timebase_wdt_0 */ 82 #define XILINX_WATCHDOG_BASEADDR 0x50000000 83 #define XILINX_WATCHDOG_IRQ 1 84