1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 252a822edSMichal Simek /* 352a822edSMichal Simek * (C) Copyright 2007 Michal Simek 452a822edSMichal Simek * 552a822edSMichal Simek * Michal SIMEK <monstr@monstr.eu> 652a822edSMichal Simek * 720637888SStephan Linz * CAUTION: This file is a faked configuration !!! 820637888SStephan Linz * There is no real target for the microblaze-generic 920637888SStephan Linz * configuration. You have to replace this file with 1020637888SStephan Linz * the generated file from your Xilinx design flow. 1152a822edSMichal Simek */ 1252a822edSMichal Simek 13330e5545SMichal Simek #define XILINX_BOARD_NAME microblaze-generic 14330e5545SMichal Simek 1552a822edSMichal Simek /* Microblaze is microblaze_0 */ 1652a822edSMichal Simek #define XILINX_FSL_NUMBER 3 1752a822edSMichal Simek 1852a822edSMichal Simek /* GPIO is LEDs_4Bit*/ 1952a822edSMichal Simek #define XILINX_GPIO_BASEADDR 0x40000000 2052a822edSMichal Simek 2152a822edSMichal Simek /* Flash Memory is FLASH_2Mx32 */ 2252a822edSMichal Simek #define XILINX_FLASH_START 0x2c000000 2352a822edSMichal Simek #define XILINX_FLASH_SIZE 0x00800000 2452a822edSMichal Simek 250f21f98dSMichal Simek /* Watchdog IP is wxi_timebase_wdt_0 */ 260f21f98dSMichal Simek #define XILINX_WATCHDOG_BASEADDR 0x50000000 270f21f98dSMichal Simek #define XILINX_WATCHDOG_IRQ 1 28