1*52a822edSMichal Simek /* 2*52a822edSMichal Simek * (C) Copyright 2007 Michal Simek 3*52a822edSMichal Simek * 4*52a822edSMichal Simek * Michal SIMEK <monstr@monstr.eu> 5*52a822edSMichal Simek * 6*52a822edSMichal Simek * See file CREDITS for list of people who contributed to this 7*52a822edSMichal Simek * project. 8*52a822edSMichal Simek * 9*52a822edSMichal Simek * This program is free software; you can redistribute it and/or 10*52a822edSMichal Simek * modify it under the terms of the GNU General Public License as 11*52a822edSMichal Simek * published by the Free Software Foundation; either version 2 of 12*52a822edSMichal Simek * the License, or (at your option) any later version. 13*52a822edSMichal Simek * 14*52a822edSMichal Simek * This program is distributed in the hope that it will be useful, 15*52a822edSMichal Simek * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*52a822edSMichal Simek * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*52a822edSMichal Simek * GNU General Public License for more details. 18*52a822edSMichal Simek * 19*52a822edSMichal Simek * You should have received a copy of the GNU General Public License 20*52a822edSMichal Simek * along with this program; if not, write to the Free Software 21*52a822edSMichal Simek * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*52a822edSMichal Simek * MA 02111-1307 USA 23*52a822edSMichal Simek * 24*52a822edSMichal Simek * CAUTION: This file is automatically generated by libgen. 25*52a822edSMichal Simek * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 26*52a822edSMichal Simek */ 27*52a822edSMichal Simek 28*52a822edSMichal Simek /* System Clock Frequency */ 29*52a822edSMichal Simek #define XILINX_CLOCK_FREQ 100000000 30*52a822edSMichal Simek 31*52a822edSMichal Simek /* Microblaze is microblaze_0 */ 32*52a822edSMichal Simek #define XILINX_USE_MSR_INSTR 1 33*52a822edSMichal Simek #define XILINX_FSL_NUMBER 3 34*52a822edSMichal Simek 35*52a822edSMichal Simek /* Interrupt controller is opb_intc_0 */ 36*52a822edSMichal Simek #define XILINX_INTC_BASEADDR 0x41200000 37*52a822edSMichal Simek #define XILINX_INTC_NUM_INTR_INPUTS 6 38*52a822edSMichal Simek 39*52a822edSMichal Simek /* Timer pheriphery is opb_timer_1 */ 40*52a822edSMichal Simek #define XILINX_TIMER_BASEADDR 0x41c00000 41*52a822edSMichal Simek #define XILINX_TIMER_IRQ 0 42*52a822edSMichal Simek 43*52a822edSMichal Simek /* Uart pheriphery is RS232_Uart */ 44*52a822edSMichal Simek #define XILINX_UARTLITE_BASEADDR 0x40600000 45*52a822edSMichal Simek #define XILINX_UARTLITE_BAUDRATE 115200 46*52a822edSMichal Simek 47*52a822edSMichal Simek /* IIC pheriphery is IIC_EEPROM */ 48*52a822edSMichal Simek #define XILINX_IIC_0_BASEADDR 0x40800000 49*52a822edSMichal Simek #define XILINX_IIC_0_FREQ 100000 50*52a822edSMichal Simek #define XILINX_IIC_0_BIT 0 51*52a822edSMichal Simek 52*52a822edSMichal Simek /* GPIO is LEDs_4Bit*/ 53*52a822edSMichal Simek #define XILINX_GPIO_BASEADDR 0x40000000 54*52a822edSMichal Simek 55*52a822edSMichal Simek /* Flash Memory is FLASH_2Mx32 */ 56*52a822edSMichal Simek #define XILINX_FLASH_START 0x2c000000 57*52a822edSMichal Simek #define XILINX_FLASH_SIZE 0x00800000 58*52a822edSMichal Simek 59*52a822edSMichal Simek /* Main Memory is DDR_SDRAM_64Mx32 */ 60*52a822edSMichal Simek #define XILINX_RAM_START 0x28000000 61*52a822edSMichal Simek #define XILINX_RAM_SIZE 0x04000000 62*52a822edSMichal Simek 63*52a822edSMichal Simek /* Sysace Controller is SysACE_CompactFlash */ 64*52a822edSMichal Simek #define XILINX_SYSACE_BASEADDR 0x41800000 65*52a822edSMichal Simek #define XILINX_SYSACE_HIGHADDR 0x4180ffff 66*52a822edSMichal Simek #define XILINX_SYSACE_MEM_WIDTH 16 67*52a822edSMichal Simek 68*52a822edSMichal Simek /* Ethernet controller is Ethernet_MAC */ 69*52a822edSMichal Simek #define XILINX_EMACLITE_BASEADDR 0x40C00000 70