183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 252a822edSMichal Simek /* 352a822edSMichal Simek * (C) Copyright 2007 Michal Simek 452a822edSMichal Simek * 552a822edSMichal Simek * Michal SIMEK <monstr@monstr.eu> 652a822edSMichal Simek */ 752a822edSMichal Simek 835912528SShreenidhi Shedi /* 935912528SShreenidhi Shedi * This is a board specific file. It's OK to include board specific 1035912528SShreenidhi Shedi * header files 1135912528SShreenidhi Shedi */ 1252a822edSMichal Simek 1352a822edSMichal Simek #include <common.h> 1452a822edSMichal Simek #include <config.h> 15e945f6dcSMichal Simek #include <fdtdec.h> 162380b8f5SMichal Simek #include <asm/processor.h> 1752a822edSMichal Simek #include <asm/microblaze_intc.h> 1852a822edSMichal Simek #include <asm/asm.h> 194e779ad2SMichal Simek #include <asm/gpio.h> 20*6ec6f584SShreenidhi Shedi #include <dm/uclass.h> 21*6ec6f584SShreenidhi Shedi #include <wdt.h> 224e779ad2SMichal Simek 23e945f6dcSMichal Simek DECLARE_GLOBAL_DATA_PTR; 24e945f6dcSMichal Simek 254e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 264e779ad2SMichal Simek static int reset_pin = -1; 274e779ad2SMichal Simek #endif 2852a822edSMichal Simek 29*6ec6f584SShreenidhi Shedi #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 30*6ec6f584SShreenidhi Shedi static struct udevice *watchdog_dev; 31*6ec6f584SShreenidhi Shedi #endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */ 32*6ec6f584SShreenidhi Shedi 33e945f6dcSMichal Simek ulong ram_base; 34e945f6dcSMichal Simek 3576b00acaSSimon Glass int dram_init_banksize(void) 36e945f6dcSMichal Simek { 37e945f6dcSMichal Simek gd->bd->bi_dram[0].start = ram_base; 38e945f6dcSMichal Simek gd->bd->bi_dram[0].size = get_effective_memsize(); 3976b00acaSSimon Glass 4076b00acaSSimon Glass return 0; 41e945f6dcSMichal Simek } 42e945f6dcSMichal Simek 43e945f6dcSMichal Simek int dram_init(void) 44e945f6dcSMichal Simek { 45e945f6dcSMichal Simek int node; 46e945f6dcSMichal Simek fdt_addr_t addr; 47e945f6dcSMichal Simek fdt_size_t size; 48e945f6dcSMichal Simek const void *blob = gd->fdt_blob; 49e945f6dcSMichal Simek 50e945f6dcSMichal Simek node = fdt_node_offset_by_prop_value(blob, -1, "device_type", 51e945f6dcSMichal Simek "memory", 7); 52e945f6dcSMichal Simek if (node == -FDT_ERR_NOTFOUND) { 53e945f6dcSMichal Simek debug("DRAM: Can't get memory node\n"); 54e945f6dcSMichal Simek return 1; 55e945f6dcSMichal Simek } 56e945f6dcSMichal Simek addr = fdtdec_get_addr_size(blob, node, "reg", &size); 57e945f6dcSMichal Simek if (addr == FDT_ADDR_T_NONE || size == 0) { 58e945f6dcSMichal Simek debug("DRAM: Can't get base address or size\n"); 59e945f6dcSMichal Simek return 1; 60e945f6dcSMichal Simek } 61e945f6dcSMichal Simek ram_base = addr; 62e945f6dcSMichal Simek 63e945f6dcSMichal Simek gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */ 64e945f6dcSMichal Simek gd->ram_size = size; 65e945f6dcSMichal Simek 66e945f6dcSMichal Simek return 0; 67e945f6dcSMichal Simek }; 68e945f6dcSMichal Simek 69d6c856c0SMichal Simek #if !defined(CONFIG_SYSRESET) || defined(CONFIG_SPL_BUILD) 70882b7d72SMike Frysinger int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 7152a822edSMichal Simek { 72b5e9b9a9SMichal Simek #ifndef CONFIG_SPL_BUILD 734e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 744e779ad2SMichal Simek if (reset_pin != -1) 754e779ad2SMichal Simek gpio_direction_output(reset_pin, 1); 7652a822edSMichal Simek #endif 77b5e9b9a9SMichal Simek #endif 7835912528SShreenidhi Shedi puts("Resetting board\n"); 798848668eSMichal Simek __asm__ __volatile__ (" mts rmsr, r0;" \ 808848668eSMichal Simek "bra r0"); 81b364727aSMichal Simek 82882b7d72SMike Frysinger return 0; 8352a822edSMichal Simek } 84d6c856c0SMichal Simek #endif 8552a822edSMichal Simek 8638c4761cSMichal Simek static int gpio_init(void) 8752a822edSMichal Simek { 884e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 894e779ad2SMichal Simek reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); 904e779ad2SMichal Simek if (reset_pin != -1) 914e779ad2SMichal Simek gpio_request(reset_pin, "reset_pin"); 9252a822edSMichal Simek #endif 9352a822edSMichal Simek return 0; 9452a822edSMichal Simek } 9552a822edSMichal Simek 96*6ec6f584SShreenidhi Shedi #ifdef CONFIG_WDT 97*6ec6f584SShreenidhi Shedi /* Called by macro WATCHDOG_RESET */ 98*6ec6f584SShreenidhi Shedi void watchdog_reset(void) 99*6ec6f584SShreenidhi Shedi { 100*6ec6f584SShreenidhi Shedi #if !defined(CONFIG_SPL_BUILD) 101*6ec6f584SShreenidhi Shedi ulong now; 102*6ec6f584SShreenidhi Shedi static ulong next_reset; 103*6ec6f584SShreenidhi Shedi 104*6ec6f584SShreenidhi Shedi if (!watchdog_dev) 105*6ec6f584SShreenidhi Shedi return; 106*6ec6f584SShreenidhi Shedi 107*6ec6f584SShreenidhi Shedi now = timer_get_us(); 108*6ec6f584SShreenidhi Shedi 109*6ec6f584SShreenidhi Shedi /* Do not reset the watchdog too often */ 110*6ec6f584SShreenidhi Shedi if (now > next_reset) { 111*6ec6f584SShreenidhi Shedi wdt_reset(watchdog_dev); 112*6ec6f584SShreenidhi Shedi next_reset = now + 1000; 113*6ec6f584SShreenidhi Shedi } 114*6ec6f584SShreenidhi Shedi #endif /* !CONFIG_SPL_BUILD */ 115*6ec6f584SShreenidhi Shedi } 116*6ec6f584SShreenidhi Shedi #endif /* CONFIG_WDT */ 117*6ec6f584SShreenidhi Shedi 11838c4761cSMichal Simek int board_late_init(void) 1192380b8f5SMichal Simek { 1202380b8f5SMichal Simek gpio_init(); 12138c4761cSMichal Simek 122*6ec6f584SShreenidhi Shedi #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) 123*6ec6f584SShreenidhi Shedi watchdog_dev = NULL; 124*6ec6f584SShreenidhi Shedi 125*6ec6f584SShreenidhi Shedi if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { 126*6ec6f584SShreenidhi Shedi debug("Watchdog: Not found by seq!\n"); 127*6ec6f584SShreenidhi Shedi if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 128*6ec6f584SShreenidhi Shedi puts("Watchdog: Not found!\n"); 129*6ec6f584SShreenidhi Shedi return 0; 130*6ec6f584SShreenidhi Shedi } 131*6ec6f584SShreenidhi Shedi } 132*6ec6f584SShreenidhi Shedi 133*6ec6f584SShreenidhi Shedi wdt_start(watchdog_dev, 0, 0); 134*6ec6f584SShreenidhi Shedi puts("Watchdog: Started\n"); 135*6ec6f584SShreenidhi Shedi #endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */ 136*6ec6f584SShreenidhi Shedi 13738c4761cSMichal Simek return 0; 1382380b8f5SMichal Simek } 139