xref: /openbmc/u-boot/board/xes/xpedite550x/ddr.c (revision bfc93fb4)
1 /*
2  * Copyright 2010 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #include <common.h>
25 #include <i2c.h>
26 
27 #include <asm/fsl_ddr_sdram.h>
28 #include <asm/fsl_ddr_dimm_params.h>
29 
30 void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
31 {
32 	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
33 		 sizeof(ddr3_spd_eeprom_t));
34 }
35 
36 /*
37  *     There are traditionally three board-specific SDRAM timing parameters
38  *     which must be calculated based on the particular PCB artwork.  These are:
39  *     1.) CPO (Read Capture Delay)
40  *	       - TIMING_CFG_2 register
41  *	       Source: Calculation based on board trace lengths and
42  *		       chip-specific internal delays.
43  *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
44  *	       - DDR_SDRAM_CLK_CNTL register
45  *	       Source: Signal Integrity Simulations
46  *     3.) 2T Timing on Addr/Ctl
47  *	       - TIMING_CFG_2 register
48  *	       Source: Signal Integrity Simulations
49  *	       Usually only needed with heavy load/very high speed (>DDR2-800)
50  *
51  *     ====== XPedite550x DDR3-800 read delay calculations ======
52  *
53  *     The P2020 processor provides an autoleveling option. Setting CPO to
54  *     0x1f enables this auto configuration.
55  */
56 
57 typedef struct {
58 	unsigned short datarate_mhz_low;
59 	unsigned short datarate_mhz_high;
60 	unsigned char clk_adjust;
61 	unsigned char cpo;
62 } board_specific_parameters_t;
63 
64 const board_specific_parameters_t board_specific_parameters[][20] = {
65 	{
66 		/* Controller 0 */
67 		{
68 			/* DDR3-600/667 */
69 			.datarate_mhz_low	= 500,
70 			.datarate_mhz_high	= 750,
71 			.clk_adjust		= 5,
72 			.cpo			= 31,
73 		},
74 		{
75 			/* DDR3-800 */
76 			.datarate_mhz_low	= 750,
77 			.datarate_mhz_high	= 850,
78 			.clk_adjust		= 5,
79 			.cpo			= 31,
80 		},
81 	},
82 };
83 
84 void fsl_ddr_board_options(memctl_options_t *popts,
85 				dimm_params_t *pdimm,
86 				unsigned int ctrl_num)
87 {
88 	const board_specific_parameters_t *pbsp =
89 				&(board_specific_parameters[ctrl_num][0]);
90 	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
91 				sizeof(board_specific_parameters[0][0]);
92 	u32 i;
93 	ulong ddr_freq;
94 
95 	/*
96 	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
97 	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
98 	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
99 	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
100 	 */
101 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
102 		if (i&1) {	/* odd CS */
103 			popts->cs_local_opts[i].odt_rd_cfg = 0;
104 			popts->cs_local_opts[i].odt_wr_cfg = 0;
105 		} else {	/* even CS */
106 			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
107 				popts->cs_local_opts[i].odt_rd_cfg = 0;
108 				popts->cs_local_opts[i].odt_wr_cfg = 4;
109 			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
110 				popts->cs_local_opts[i].odt_rd_cfg = 3;
111 				popts->cs_local_opts[i].odt_wr_cfg = 3;
112 			}
113 		}
114 	}
115 
116 	/*
117 	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
118 	 * freqency and n_banks specified in board_specific_parameters table.
119 	 */
120 	ddr_freq = get_ddr_freq(0) / 1000000;
121 
122 	for (i = 0; i < num_params; i++) {
123 		if (ddr_freq >= pbsp->datarate_mhz_low &&
124 		    ddr_freq <= pbsp->datarate_mhz_high) {
125 			popts->clk_adjust = pbsp->clk_adjust;
126 			popts->cpo_override = pbsp->cpo;
127 			popts->twoT_en = 0;
128 			break;
129 		}
130 		pbsp++;
131 	}
132 
133 	if (i == num_params) {
134 		printf("Warning: board specific timing not found "
135 		"for data rate %lu MT/s!\n", ddr_freq);
136 	}
137 
138 	/*
139 	 * Factors to consider for half-strength driver enable:
140 	 *	- number of DIMMs installed
141 	 */
142 	popts->half_strength_driver_enable = 0;
143 
144 	/*
145 	 * Enable on-die termination.
146 	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
147 	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
148 	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
149 	 */
150 	popts->rtt_override = 1;
151 	popts->rtt_override_value = 3;
152 }
153