1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 27 #include <asm/fsl_ddr_sdram.h> 28 #include <asm/fsl_ddr_dimm_params.h> 29 30 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) 31 { 32 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, 33 sizeof(ddr3_spd_eeprom_t)); 34 } 35 36 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, 37 unsigned int ctrl_num) 38 { 39 unsigned int i; 40 unsigned int i2c_address = 0; 41 42 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 43 if (ctrl_num == 0 && i == 0) 44 i2c_address = SPD_EEPROM_ADDRESS1; 45 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 46 } 47 } 48 49 /* 50 * There are traditionally three board-specific SDRAM timing parameters 51 * which must be calculated based on the particular PCB artwork. These are: 52 * 1.) CPO (Read Capture Delay) 53 * - TIMING_CFG_2 register 54 * Source: Calculation based on board trace lengths and 55 * chip-specific internal delays. 56 * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control) 57 * - DDR_SDRAM_CLK_CNTL register 58 * Source: Signal Integrity Simulations 59 * 3.) 2T Timing on Addr/Ctl 60 * - TIMING_CFG_2 register 61 * Source: Signal Integrity Simulations 62 * Usually only needed with heavy load/very high speed (>DDR2-800) 63 * 64 * ====== XPedite550x DDR3-800 read delay calculations ====== 65 * 66 * The P2020 processor provides an autoleveling option. Setting CPO to 67 * 0x1f enables this auto configuration. 68 */ 69 70 typedef struct { 71 unsigned short datarate_mhz_low; 72 unsigned short datarate_mhz_high; 73 unsigned char clk_adjust; 74 unsigned char cpo; 75 } board_specific_parameters_t; 76 77 const board_specific_parameters_t board_specific_parameters[][20] = { 78 { 79 /* Controller 0 */ 80 { 81 /* DDR3-600/667 */ 82 .datarate_mhz_low = 500, 83 .datarate_mhz_high = 750, 84 .clk_adjust = 5, 85 .cpo = 31, 86 }, 87 { 88 /* DDR3-800 */ 89 .datarate_mhz_low = 750, 90 .datarate_mhz_high = 850, 91 .clk_adjust = 5, 92 .cpo = 31, 93 }, 94 }, 95 }; 96 97 void fsl_ddr_board_options(memctl_options_t *popts, 98 dimm_params_t *pdimm, 99 unsigned int ctrl_num) 100 { 101 const board_specific_parameters_t *pbsp = 102 &(board_specific_parameters[ctrl_num][0]); 103 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / 104 sizeof(board_specific_parameters[0][0]); 105 u32 i; 106 ulong ddr_freq; 107 108 /* 109 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in 110 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If 111 * there are two dimms in the controller, set odt_rd_cfg to 3 and 112 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. 113 */ 114 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 115 if (i&1) { /* odd CS */ 116 popts->cs_local_opts[i].odt_rd_cfg = 0; 117 popts->cs_local_opts[i].odt_wr_cfg = 0; 118 } else { /* even CS */ 119 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { 120 popts->cs_local_opts[i].odt_rd_cfg = 0; 121 popts->cs_local_opts[i].odt_wr_cfg = 4; 122 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { 123 popts->cs_local_opts[i].odt_rd_cfg = 3; 124 popts->cs_local_opts[i].odt_wr_cfg = 3; 125 } 126 } 127 } 128 129 /* 130 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 131 * freqency and n_banks specified in board_specific_parameters table. 132 */ 133 ddr_freq = get_ddr_freq(0) / 1000000; 134 135 for (i = 0; i < num_params; i++) { 136 if (ddr_freq >= pbsp->datarate_mhz_low && 137 ddr_freq <= pbsp->datarate_mhz_high) { 138 popts->clk_adjust = pbsp->clk_adjust; 139 popts->cpo_override = pbsp->cpo; 140 popts->twoT_en = 0; 141 } 142 pbsp++; 143 } 144 145 /* 146 * Factors to consider for half-strength driver enable: 147 * - number of DIMMs installed 148 */ 149 popts->half_strength_driver_enable = 0; 150 151 /* 152 * Enable on-die termination. 153 * From the Micron Technical Node TN-41-04, RTT_Nom should typically 154 * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR 155 * is handled in the Freescale DDR3 driver. Set RTT_Nom here. 156 */ 157 popts->rtt_override = 1; 158 popts->rtt_override_value = 3; 159 } 160