1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2bfe18815SJohn Schmoller /*
3bfe18815SJohn Schmoller * Copyright 2010 Extreme Engineering Solutions, Inc.
4bfe18815SJohn Schmoller * Copyright 2007-2008 Freescale Semiconductor, Inc.
5bfe18815SJohn Schmoller */
6bfe18815SJohn Schmoller
7bfe18815SJohn Schmoller #include <common.h>
8bfe18815SJohn Schmoller #include <i2c.h>
9bfe18815SJohn Schmoller
105614e71bSYork Sun #include <fsl_ddr_sdram.h>
115614e71bSYork Sun #include <fsl_ddr_dimm_params.h>
12bfe18815SJohn Schmoller
get_spd(ddr3_spd_eeprom_t * spd,u8 i2c_address)13c39f44dcSKumar Gala void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
14bfe18815SJohn Schmoller {
15bfe18815SJohn Schmoller i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
16bfe18815SJohn Schmoller sizeof(ddr3_spd_eeprom_t));
17bfe18815SJohn Schmoller }
18bfe18815SJohn Schmoller
19bfe18815SJohn Schmoller /*
20bfe18815SJohn Schmoller * There are traditionally three board-specific SDRAM timing parameters
21bfe18815SJohn Schmoller * which must be calculated based on the particular PCB artwork. These are:
22bfe18815SJohn Schmoller * 1.) CPO (Read Capture Delay)
23bfe18815SJohn Schmoller * - TIMING_CFG_2 register
24bfe18815SJohn Schmoller * Source: Calculation based on board trace lengths and
25bfe18815SJohn Schmoller * chip-specific internal delays.
26bfe18815SJohn Schmoller * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
27bfe18815SJohn Schmoller * - DDR_SDRAM_CLK_CNTL register
28bfe18815SJohn Schmoller * Source: Signal Integrity Simulations
29bfe18815SJohn Schmoller * 3.) 2T Timing on Addr/Ctl
30bfe18815SJohn Schmoller * - TIMING_CFG_2 register
31bfe18815SJohn Schmoller * Source: Signal Integrity Simulations
32bfe18815SJohn Schmoller * Usually only needed with heavy load/very high speed (>DDR2-800)
33bfe18815SJohn Schmoller *
34bfe18815SJohn Schmoller * ====== XPedite550x DDR3-800 read delay calculations ======
35bfe18815SJohn Schmoller *
36bfe18815SJohn Schmoller * The P2020 processor provides an autoleveling option. Setting CPO to
37bfe18815SJohn Schmoller * 0x1f enables this auto configuration.
38bfe18815SJohn Schmoller */
39bfe18815SJohn Schmoller
40bfe18815SJohn Schmoller typedef struct {
41bfe18815SJohn Schmoller unsigned short datarate_mhz_low;
42bfe18815SJohn Schmoller unsigned short datarate_mhz_high;
43bfe18815SJohn Schmoller unsigned char clk_adjust;
44bfe18815SJohn Schmoller unsigned char cpo;
45bfe18815SJohn Schmoller } board_specific_parameters_t;
46bfe18815SJohn Schmoller
47bfe18815SJohn Schmoller const board_specific_parameters_t board_specific_parameters[][20] = {
48bfe18815SJohn Schmoller {
49bfe18815SJohn Schmoller /* Controller 0 */
50bfe18815SJohn Schmoller {
51bfe18815SJohn Schmoller /* DDR3-600/667 */
52bfe18815SJohn Schmoller .datarate_mhz_low = 500,
53bfe18815SJohn Schmoller .datarate_mhz_high = 750,
54bfe18815SJohn Schmoller .clk_adjust = 5,
55bfe18815SJohn Schmoller .cpo = 31,
56bfe18815SJohn Schmoller },
57bfe18815SJohn Schmoller {
58bfe18815SJohn Schmoller /* DDR3-800 */
59bfe18815SJohn Schmoller .datarate_mhz_low = 750,
60bfe18815SJohn Schmoller .datarate_mhz_high = 850,
61bfe18815SJohn Schmoller .clk_adjust = 5,
62bfe18815SJohn Schmoller .cpo = 31,
63bfe18815SJohn Schmoller },
64bfe18815SJohn Schmoller },
65bfe18815SJohn Schmoller };
66bfe18815SJohn Schmoller
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)67bfe18815SJohn Schmoller void fsl_ddr_board_options(memctl_options_t *popts,
68bfe18815SJohn Schmoller dimm_params_t *pdimm,
69bfe18815SJohn Schmoller unsigned int ctrl_num)
70bfe18815SJohn Schmoller {
71bfe18815SJohn Schmoller const board_specific_parameters_t *pbsp =
72bfe18815SJohn Schmoller &(board_specific_parameters[ctrl_num][0]);
73bfe18815SJohn Schmoller u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
74bfe18815SJohn Schmoller sizeof(board_specific_parameters[0][0]);
75bfe18815SJohn Schmoller u32 i;
76bfe18815SJohn Schmoller ulong ddr_freq;
77bfe18815SJohn Schmoller
78bfe18815SJohn Schmoller /*
79bfe18815SJohn Schmoller * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
80bfe18815SJohn Schmoller * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
81bfe18815SJohn Schmoller * there are two dimms in the controller, set odt_rd_cfg to 3 and
82bfe18815SJohn Schmoller * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
83bfe18815SJohn Schmoller */
84bfe18815SJohn Schmoller for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
85bfe18815SJohn Schmoller if (i&1) { /* odd CS */
86bfe18815SJohn Schmoller popts->cs_local_opts[i].odt_rd_cfg = 0;
87bfe18815SJohn Schmoller popts->cs_local_opts[i].odt_wr_cfg = 0;
88bfe18815SJohn Schmoller } else { /* even CS */
89bfe18815SJohn Schmoller if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
90bfe18815SJohn Schmoller popts->cs_local_opts[i].odt_rd_cfg = 0;
91bfe18815SJohn Schmoller popts->cs_local_opts[i].odt_wr_cfg = 4;
92bfe18815SJohn Schmoller } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
93bfe18815SJohn Schmoller popts->cs_local_opts[i].odt_rd_cfg = 3;
94bfe18815SJohn Schmoller popts->cs_local_opts[i].odt_wr_cfg = 3;
95bfe18815SJohn Schmoller }
96bfe18815SJohn Schmoller }
97bfe18815SJohn Schmoller }
98bfe18815SJohn Schmoller
99bfe18815SJohn Schmoller /*
100bfe18815SJohn Schmoller * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
101bfe18815SJohn Schmoller * freqency and n_banks specified in board_specific_parameters table.
102bfe18815SJohn Schmoller */
103bfe18815SJohn Schmoller ddr_freq = get_ddr_freq(0) / 1000000;
104bfe18815SJohn Schmoller
105bfe18815SJohn Schmoller for (i = 0; i < num_params; i++) {
106bfe18815SJohn Schmoller if (ddr_freq >= pbsp->datarate_mhz_low &&
107bfe18815SJohn Schmoller ddr_freq <= pbsp->datarate_mhz_high) {
108bfe18815SJohn Schmoller popts->clk_adjust = pbsp->clk_adjust;
109bfe18815SJohn Schmoller popts->cpo_override = pbsp->cpo;
1100dd38a35SPriyanka Jain popts->twot_en = 0;
111939e5bf9SYork Sun break;
112bfe18815SJohn Schmoller }
113bfe18815SJohn Schmoller pbsp++;
114bfe18815SJohn Schmoller }
115bfe18815SJohn Schmoller
116939e5bf9SYork Sun if (i == num_params) {
117939e5bf9SYork Sun printf("Warning: board specific timing not found "
118939e5bf9SYork Sun "for data rate %lu MT/s!\n", ddr_freq);
119939e5bf9SYork Sun }
120939e5bf9SYork Sun
121bfe18815SJohn Schmoller /*
122bfe18815SJohn Schmoller * Factors to consider for half-strength driver enable:
123bfe18815SJohn Schmoller * - number of DIMMs installed
124bfe18815SJohn Schmoller */
125bfe18815SJohn Schmoller popts->half_strength_driver_enable = 0;
126bfe18815SJohn Schmoller
127bfe18815SJohn Schmoller /*
128bfe18815SJohn Schmoller * Enable on-die termination.
129bfe18815SJohn Schmoller * From the Micron Technical Node TN-41-04, RTT_Nom should typically
130bfe18815SJohn Schmoller * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
131bfe18815SJohn Schmoller * is handled in the Freescale DDR3 driver. Set RTT_Nom here.
132bfe18815SJohn Schmoller */
133bfe18815SJohn Schmoller popts->rtt_override = 1;
134bfe18815SJohn Schmoller popts->rtt_override_value = 3;
135bfe18815SJohn Schmoller }
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