1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008 Extreme Engineering Solutions, Inc. 4 * Copyright 2008 Freescale Semiconductor, Inc. 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 */ 9 10 #include <common.h> 11 #include <asm/mmu.h> 12 13 struct fsl_e_tlb_entry tlb_table[] = { 14 /* TLB 0 - for temp stack in cache */ 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28 MAS3_SX|MAS3_SW|MAS3_SR, 0, 29 0, 0, BOOKE_PAGESZ_4K, 0), 30 31 /* W**G* - NOR flashes */ 32 /* This will be changed to *I*G* after relocation to RAM. */ 33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, 34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 35 0, 0, BOOKE_PAGESZ_256M, 1), 36 37 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 38 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39 0, 1, BOOKE_PAGESZ_1M, 1), 40 41 /* *I*G* - NAND flash */ 42 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, 43 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 44 0, 2, BOOKE_PAGESZ_1M, 1), 45 46 #if CONFIG_PCI1 47 /* *I*G* - PCI MEM */ 48 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50 0, 3, BOOKE_PAGESZ_1G, 1), 51 #endif 52 53 #if CONFIG_PCI2 54 /* *I*G* - PCI MEM */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 4, BOOKE_PAGESZ_256M, 1), 58 #endif 59 60 #if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) 61 /* *I*G* - PCI IO */ 62 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64 0, 5, BOOKE_PAGESZ_16M, 1), 65 #endif 66 }; 67 68 int num_tlb_entries = ARRAY_SIZE(tlb_table); 69