1*c00ac259SPeter Tyser /* 2*c00ac259SPeter Tyser * Copyright 2008 Extreme Engineering Solutions, Inc. 3*c00ac259SPeter Tyser * Copyright 2008 Freescale Semiconductor, Inc. 4*c00ac259SPeter Tyser * 5*c00ac259SPeter Tyser * (C) Copyright 2000 6*c00ac259SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7*c00ac259SPeter Tyser * 8*c00ac259SPeter Tyser * See file CREDITS for list of people who contributed to this 9*c00ac259SPeter Tyser * project. 10*c00ac259SPeter Tyser * 11*c00ac259SPeter Tyser * This program is free software; you can redistribute it and/or 12*c00ac259SPeter Tyser * modify it under the terms of the GNU General Public License as 13*c00ac259SPeter Tyser * published by the Free Software Foundation; either version 2 of 14*c00ac259SPeter Tyser * the License, or (at your option) any later version. 15*c00ac259SPeter Tyser * 16*c00ac259SPeter Tyser * This program is distributed in the hope that it will be useful, 17*c00ac259SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*c00ac259SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*c00ac259SPeter Tyser * GNU General Public License for more details. 20*c00ac259SPeter Tyser * 21*c00ac259SPeter Tyser * You should have received a copy of the GNU General Public License 22*c00ac259SPeter Tyser * along with this program; if not, write to the Free Software 23*c00ac259SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24*c00ac259SPeter Tyser * MA 02111-1307 USA 25*c00ac259SPeter Tyser */ 26*c00ac259SPeter Tyser 27*c00ac259SPeter Tyser #include <common.h> 28*c00ac259SPeter Tyser #include <asm/mmu.h> 29*c00ac259SPeter Tyser 30*c00ac259SPeter Tyser struct fsl_e_tlb_entry tlb_table[] = { 31*c00ac259SPeter Tyser /* TLB 0 - for temp stack in cache */ 32*c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 33*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 34*c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 35*c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36*c00ac259SPeter Tyser CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 37*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 38*c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 39*c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40*c00ac259SPeter Tyser CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 41*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 42*c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 43*c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44*c00ac259SPeter Tyser CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 45*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 46*c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 47*c00ac259SPeter Tyser 48*c00ac259SPeter Tyser /* W**G* - NOR flashes */ 49*c00ac259SPeter Tyser /* This will be changed to *I*G* after relocation to RAM. */ 50*c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, 51*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 52*c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_256M, 1), 53*c00ac259SPeter Tyser 54*c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 55*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 56*c00ac259SPeter Tyser 0, 1, BOOKE_PAGESZ_1M, 1), 57*c00ac259SPeter Tyser 58*c00ac259SPeter Tyser /* *I*G* - NAND flash */ 59*c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, 60*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61*c00ac259SPeter Tyser 0, 2, BOOKE_PAGESZ_1M, 1), 62*c00ac259SPeter Tyser 63*c00ac259SPeter Tyser #if CONFIG_PCI1 64*c00ac259SPeter Tyser /* *I*G* - PCI MEM */ 65*c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 66*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67*c00ac259SPeter Tyser 0, 3, BOOKE_PAGESZ_1G, 1), 68*c00ac259SPeter Tyser #endif 69*c00ac259SPeter Tyser 70*c00ac259SPeter Tyser #if CONFIG_PCI2 71*c00ac259SPeter Tyser /* *I*G* - PCI MEM */ 72*c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, 73*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 74*c00ac259SPeter Tyser 0, 4, BOOKE_PAGESZ_256M, 1), 75*c00ac259SPeter Tyser #endif 76*c00ac259SPeter Tyser 77*c00ac259SPeter Tyser #if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) 78*c00ac259SPeter Tyser /* *I*G* - PCI IO */ 79*c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, 80*c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81*c00ac259SPeter Tyser 0, 5, BOOKE_PAGESZ_16M, 1), 82*c00ac259SPeter Tyser #endif 83*c00ac259SPeter Tyser }; 84*c00ac259SPeter Tyser 85*c00ac259SPeter Tyser int num_tlb_entries = ARRAY_SIZE(tlb_table); 86