1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 12 #include <fsl_ddr_sdram.h> 13 #include <fsl_ddr_dimm_params.h> 14 15 void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 16 { 17 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 18 19 /* We use soldered memory, but use an SPD EEPROM to describe it. 20 * The SPD has an unspecified dimm type, but the DDR2 initialization 21 * code requires a specific type to be specified. This sets the type 22 * as a standard unregistered SO-DIMM. */ 23 if (spd->dimm_type == 0) { 24 spd->dimm_type = 0x4; 25 ((uchar *)spd)[63] += 0x4; 26 } 27 } 28 29 void fsl_ddr_board_options(memctl_options_t *popts, 30 dimm_params_t *pdimm, 31 unsigned int ctrl_num) 32 { 33 /* 34 * Factors to consider for clock adjust: 35 * - number of chips on bus 36 * - position of slot 37 * - DDR1 vs. DDR2? 38 * - ??? 39 * 40 * This needs to be determined on a board-by-board basis. 41 * 0110 3/4 cycle late 42 * 0111 7/8 cycle late 43 */ 44 popts->clk_adjust = 7; 45 46 /* 47 * Factors to consider for CPO: 48 * - frequency 49 * - ddr1 vs. ddr2 50 */ 51 popts->cpo_override = 9; 52 53 /* 54 * Factors to consider for write data delay: 55 * - number of DIMMs 56 * 57 * 1 = 1/4 clock delay 58 * 2 = 1/2 clock delay 59 * 3 = 3/4 clock delay 60 * 4 = 1 clock delay 61 * 5 = 5/4 clock delay 62 * 6 = 3/2 clock delay 63 */ 64 popts->write_data_delay = 3; 65 66 /* 67 * Factors to consider for half-strength driver enable: 68 * - number of DIMMs installed 69 */ 70 popts->half_strength_driver_enable = 0; 71 } 72