1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <pci.h> 26 #include <asm/fsl_pci.h> 27 #include <asm/fsl_serdes.h> 28 #include <asm/io.h> 29 #include <linux/compiler.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 33 34 #ifdef CONFIG_PCI1 35 static struct pci_controller pci1_hose; 36 #endif 37 #ifdef CONFIG_PCIE1 38 static struct pci_controller pcie1_hose; 39 #endif 40 #ifdef CONFIG_PCIE2 41 static struct pci_controller pcie2_hose; 42 #endif 43 #ifdef CONFIG_PCIE3 44 static struct pci_controller pcie3_hose; 45 #endif 46 47 /* 48 * 85xx and 86xx share naming conventions, but different layout. 49 * Correlate names to CPU-specific values to share common 50 * PCI code. 51 */ 52 #if defined(CONFIG_MPC85xx) 53 #define MPC8xxx_DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 54 #define MPC8xxx_DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 55 #define MPC8xxx_DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 56 #define MPC8xxx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL 57 #define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC85xx_PORDEVSR_IO_SEL_SHIFT 58 #define MPC8xxx_PORBMSR_HA MPC85xx_PORBMSR_HA 59 #define MPC8xxx_PORBMSR_HA_SHIFT MPC85xx_PORBMSR_HA_SHIFT 60 #elif defined(CONFIG_MPC86xx) 61 #define MPC8xxx_DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIEX1 62 #define MPC8xxx_DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIEX2 63 #define MPC8xxx_DEVDISR_PCIE3 0 /* 8641 doesn't have PCIe3 */ 64 #define MPC8xxx_PORDEVSR_IO_SEL MPC8641_PORDEVSR_IO_SEL 65 #define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC8641_PORDEVSR_IO_SEL_SHIFT 66 #define MPC8xxx_PORBMSR_HA MPC8641_PORBMSR_HA 67 #define MPC8xxx_PORBMSR_HA_SHIFT MPC8641_PORBMSR_HA_SHIFT 68 #endif 69 70 void pci_init_board(void) 71 { 72 struct fsl_pci_info pci_info[3]; 73 int first_free_busno = 0; 74 int num = 0; 75 int pcie_ep; 76 __maybe_unused int pcie_configured; 77 78 #if defined(CONFIG_MPC85xx) 79 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 80 #elif defined(CONFIG_MPC86xx) 81 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 82 volatile ccsr_gur_t *gur = &immap->im_gur; 83 #endif 84 u32 devdisr = in_be32(&gur->devdisr); 85 86 #ifdef CONFIG_PCI1 87 u32 pordevsr = in_be32(&gur->pordevsr); 88 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; 89 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; 90 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; 91 uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; 92 uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; 93 94 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 95 SET_STD_PCI_INFO(pci_info[num], 1); 96 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 97 printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n", 98 pci_32 ? 32 : 64, 99 pcix ? "PCIX" : "PCI", 100 pci_spd_norm ? ">=" : "<=", 101 pcix ? freq * 2 : freq, 102 pcie_ep ? "agent" : "host", 103 pci_arb ? "arbiter" : "external-arbiter"); 104 105 first_free_busno = fsl_pci_init_port(&pci_info[num++], 106 &pci1_hose, first_free_busno); 107 } else { 108 printf("PCI1: disabled\n"); 109 } 110 #elif defined CONFIG_MPC8548 111 /* PCI1 not present on MPC8572 */ 112 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); 113 #endif 114 115 #ifdef CONFIG_PCIE1 116 pcie_configured = is_serdes_configured(PCIE1); 117 118 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { 119 SET_STD_PCIE_INFO(pci_info[num], 1); 120 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 121 printf("PCIE1: connected as %s\n", 122 pcie_ep ? "Endpoint" : "Root Complex"); 123 first_free_busno = fsl_pci_init_port(&pci_info[num++], 124 &pcie1_hose, first_free_busno); 125 } else { 126 printf("PCIE1: disabled\n"); 127 } 128 #else 129 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1); 130 #endif /* CONFIG_PCIE1 */ 131 132 #ifdef CONFIG_PCIE2 133 pcie_configured = is_serdes_configured(PCIE2); 134 135 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { 136 SET_STD_PCIE_INFO(pci_info[num], 2); 137 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 138 printf("PCIE2: connected as %s\n", 139 pcie_ep ? "Endpoint" : "Root Complex"); 140 first_free_busno = fsl_pci_init_port(&pci_info[num++], 141 &pcie2_hose, first_free_busno); 142 } else { 143 printf("PCIE2: disabled\n"); 144 } 145 #else 146 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2); 147 #endif /* CONFIG_PCIE2 */ 148 149 #ifdef CONFIG_PCIE3 150 pcie_configured = is_serdes_configured(PCIE3); 151 152 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { 153 SET_STD_PCIE_INFO(pci_info[num], 3); 154 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 155 printf("PCIE3: connected as %s\n", 156 pcie_ep ? "Endpoint" : "Root Complex"); 157 first_free_busno = fsl_pci_init_port(&pci_info[num++], 158 &pcie3_hose, first_free_busno); 159 } else { 160 printf("PCIE3: disabled\n"); 161 } 162 #else 163 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3); 164 #endif /* CONFIG_PCIE3 */ 165 } 166 167 #if defined(CONFIG_OF_BOARD_SETUP) 168 void ft_board_pci_setup(void *blob, bd_t *bd) 169 { 170 FT_FSL_PCI_SETUP; 171 } 172 #endif /* CONFIG_OF_BOARD_SETUP */ 173