1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <pci.h> 26 #include <asm/fsl_pci.h> 27 #include <asm/io.h> 28 #include <linux/compiler.h> 29 #include <libfdt.h> 30 #include <fdt_support.h> 31 32 33 #ifdef CONFIG_PCI1 34 static struct pci_controller pci1_hose; 35 #endif 36 #ifdef CONFIG_PCIE1 37 static struct pci_controller pcie1_hose; 38 #endif 39 #ifdef CONFIG_PCIE2 40 static struct pci_controller pcie2_hose; 41 #endif 42 #ifdef CONFIG_PCIE3 43 static struct pci_controller pcie3_hose; 44 #endif 45 46 /* 47 * 85xx and 86xx share naming conventions, but different layout. 48 * Correlate names to CPU-specific values to share common 49 * PCI code. 50 */ 51 #if defined(CONFIG_MPC85xx) 52 #define MPC8xxx_DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 53 #define MPC8xxx_DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 54 #define MPC8xxx_DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 55 #define MPC8xxx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL 56 #define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC85xx_PORDEVSR_IO_SEL_SHIFT 57 #define MPC8xxx_PORBMSR_HA MPC85xx_PORBMSR_HA 58 #define MPC8xxx_PORBMSR_HA_SHIFT MPC85xx_PORBMSR_HA_SHIFT 59 #elif defined(CONFIG_MPC86xx) 60 #define MPC8xxx_DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIEX1 61 #define MPC8xxx_DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIEX2 62 #define MPC8xxx_DEVDISR_PCIE3 0 /* 8641 doesn't have PCIe3 */ 63 #define MPC8xxx_PORDEVSR_IO_SEL MPC8641_PORDEVSR_IO_SEL 64 #define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC8641_PORDEVSR_IO_SEL_SHIFT 65 #define MPC8xxx_PORBMSR_HA MPC8641_PORBMSR_HA 66 #define MPC8xxx_PORBMSR_HA_SHIFT MPC8641_PORBMSR_HA_SHIFT 67 #endif 68 69 void pci_init_board(void) 70 { 71 struct fsl_pci_info pci_info[3]; 72 int first_free_busno = 0; 73 int num = 0; 74 int pcie_ep; 75 __maybe_unused int pcie_configured; 76 77 #if defined(CONFIG_MPC85xx) 78 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 79 #elif defined(CONFIG_MPC86xx) 80 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 81 volatile ccsr_gur_t *gur = &immap->im_gur; 82 #endif 83 u32 devdisr = in_be32(&gur->devdisr); 84 u32 pordevsr = in_be32(&gur->pordevsr); 85 __maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >> 86 MPC8xxx_PORDEVSR_IO_SEL_SHIFT; 87 88 #ifdef CONFIG_PCI1 89 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; 90 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; 91 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; 92 uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; 93 uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; 94 95 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 96 SET_STD_PCI_INFO(pci_info[num], 1); 97 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 98 printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", 99 pci_32 ? 32 : 64, 100 pcix ? "PCIX" : "PCI", 101 pci_spd_norm ? ">=" : "<=", 102 pcix ? freq * 2 : freq, 103 pcie_ep ? "agent" : "host", 104 pci_arb ? "arbiter" : "external-arbiter"); 105 106 first_free_busno = fsl_pci_init_port(&pci_info[num++], 107 &pci1_hose, first_free_busno); 108 } else { 109 printf(" PCI1: disabled\n"); 110 } 111 #elif defined CONFIG_MPC8548 112 /* PCI1 not present on MPC8572 */ 113 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); 114 #endif 115 116 #ifdef CONFIG_PCIE1 117 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 118 119 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { 120 SET_STD_PCIE_INFO(pci_info[num], 1); 121 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 122 printf(" PCIE1 connected as %s\n", 123 pcie_ep ? "Endpoint" : "Root Complex"); 124 first_free_busno = fsl_pci_init_port(&pci_info[num++], 125 &pcie1_hose, first_free_busno); 126 } else { 127 printf(" PCIE1: disabled\n"); 128 } 129 #else 130 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1); 131 #endif /* CONFIG_PCIE1 */ 132 133 #ifdef CONFIG_PCIE2 134 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 135 136 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { 137 SET_STD_PCIE_INFO(pci_info[num], 2); 138 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 139 printf(" PCIE2 connected as %s\n", 140 pcie_ep ? "Endpoint" : "Root Complex"); 141 first_free_busno = fsl_pci_init_port(&pci_info[num++], 142 &pcie2_hose, first_free_busno); 143 } else { 144 printf(" PCIE2: disabled\n"); 145 } 146 #else 147 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2); 148 #endif /* CONFIG_PCIE2 */ 149 150 #ifdef CONFIG_PCIE3 151 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 152 153 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { 154 SET_STD_PCIE_INFO(pci_info[num], 3); 155 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 156 printf(" PCIE3 connected as %s\n", 157 pcie_ep ? "Endpoint" : "Root Complex"); 158 first_free_busno = fsl_pci_init_port(&pci_info[num++], 159 &pcie3_hose, first_free_busno); 160 } else { 161 printf(" PCIE3: disabled\n"); 162 } 163 #else 164 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3); 165 #endif /* CONFIG_PCIE3 */ 166 } 167 168 #if defined(CONFIG_OF_BOARD_SETUP) 169 void ft_board_pci_setup(void *blob, bd_t *bd) 170 { 171 FT_FSL_PCI_SETUP; 172 } 173 #endif /* CONFIG_OF_BOARD_SETUP */ 174