1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * WORK Microwave work_92105 board support
4  *
5  * (C) Copyright 2014  DENX Software Engineering GmbH
6  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/emc.h>
14 #include <asm/gpio.h>
15 #include <spl.h>
16 #include "work_92105_display.h"
17 
18 struct emc_dram_settings dram_64mb = {
19 	.cmddelay = 0x0001C000,
20 	.config0 = 0x00005682,
21 	.rascas0 = 0x00000302,
22 	.rdconfig = 0x00000011,
23 	.trp = 52631578,
24 	.tras = 20833333,
25 	.tsrex = 12500000,
26 	.twr = 66666666,
27 	.trc = 13888888,
28 	.trfc = 10256410,
29 	.txsr = 12500000,
30 	.trrd = 1,
31 	.tmrd = 1,
32 	.tcdlr = 0,
33 	.refresh = 128000,
34 	.mode = 0x00018000,
35 	.emode = 0x02000000
36 };
37 
38 const struct emc_dram_settings dram_128mb = {
39 	.cmddelay = 0x0001C000,
40 	.config0 = 0x00005882,
41 	.rascas0 = 0x00000302,
42 	.rdconfig = 0x00000011,
43 	.trp = 52631578,
44 	.tras = 22222222,
45 	.tsrex = 8333333,
46 	.twr = 66666666,
47 	.trc = 14814814,
48 	.trfc = 10256410,
49 	.txsr = 8333333,
50 	.trrd = 1,
51 	.tmrd = 1,
52 	.tcdlr = 0,
53 	.refresh = 128000,
54 	.mode = 0x00030000,
55 	.emode = 0x02000000
56 };
57 
58 void spl_board_init(void)
59 {
60 	/* initialize serial port for console */
61 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
62 	/* initialize console */
63 	preloader_console_init();
64 	/* init DDR and NAND to chainload U-Boot */
65 	ddr_init(&dram_128mb);
66 	/*
67 	 * If this is actually a 64MB module, then the highest column
68 	 * bit in any address will be ignored, and thus address 0x80000000
69 	 * should be mirrored at address 0x80000800. Test this.
70 	 */
71 	writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */
72 	writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */
73 	if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ {
74 		/* actually 64MB mirrored: reconfigure controller */
75 		ddr_init(&dram_64mb);
76 	}
77 	/* initialize NAND controller to load U-Boot from NAND */
78 	lpc32xx_mlc_nand_init();
79 }
80 
81 u32 spl_boot_device(void)
82 {
83 	return BOOT_DEVICE_NAND;
84 }
85